Re: [AArch64] PR105162: emit barrier for __sync and __atomic builtins on CPUs without LSE

2022-05-16 Thread Richard Sandiford via Gcc-patches
"Pop, Sebastian" writes: > Please see attached the patch back-ported to branches 12, 11, 10, and 9. > Tested on aarch64-linux with bootstrap and regression test. > Ok to commit to the GCC active branches? OK, thanks. Only very safe patches are supposed to be going into GCC 9 at this stage, and I

Re: [AArch64] PR105162: emit barrier for __sync and __atomic builtins on CPUs without LSE

2022-05-13 Thread Pop, Sebastian via Gcc-patches
Please see attached the patch back-ported to branches 12, 11, 10, and 9. Tested on aarch64-linux with bootstrap and regression test. Ok to commit to the GCC active branches? Thanks, SebastianFrom bba8d09284f3478f7d542ca4e7812d4c55e25bd4 Mon Sep 17 00:00:00 2001 From: Sebastian Pop Date: Mon, 18 A

Re: [AArch64] PR105162: emit barrier for __sync and __atomic builtins on CPUs without LSE

2022-05-13 Thread Wilco Dijkstra via Gcc-patches
Hi Sebastian, >> Note the patch still needs an appropriate commit message. > > Added the following ChangeLog entry to the commit message. > > * config/aarch64/aarch64-protos.h (atomic_ool_names): Increase >dimension > of str array. > * config/aarch64/aarch64.cc (aarch64_at

Re: [AArch64] PR105162: emit barrier for __sync and __atomic builtins on CPUs without LSE

2022-05-13 Thread Richard Sandiford via Gcc-patches
"Pop, Sebastian via Gcc-patches" writes: >> Yes this looks good to me (still needs maintainer approval). > > Thanks again Wilco for your review. > >> One minor nitpick, >> a few of the tests check for __aarch64_cas2 - this should be >> __aarch64_cas2_sync. > > Fixed in the attached patch. > >> N

Re: [AArch64] PR105162: emit barrier for __sync and __atomic builtins on CPUs without LSE

2022-05-04 Thread Pop, Sebastian via Gcc-patches
> Yes this looks good to me (still needs maintainer approval). Thanks again Wilco for your review. > One minor nitpick, > a few of the tests check for __aarch64_cas2 - this should be > __aarch64_cas2_sync. Fixed in the attached patch. > Note the patch still needs an appropriate commit message

Re: [AArch64] PR105162: emit barrier for __sync and __atomic builtins on CPUs without LSE

2022-05-03 Thread Wilco Dijkstra via Gcc-patches
Hi Sebastian, > Please find attached the patch amended following your recommendations. > The number of new functions for _sync is reduced by 3x. > I tested the patch on Graviton2 aarch64-linux. > I also checked by hand that the outline functions in libgcc look similar to > what GCC produces for t

Re: [AArch64] PR105162: emit barrier for __sync and __atomic builtins on CPUs without LSE

2022-04-25 Thread Pop, Sebastian via Gcc-patches
produces for the inline version. Thanks, Sebastian From: Wilco Dijkstra Sent: Tuesday, April 19, 2022 7:51 AM To: Pop, Sebastian; gcc-patches@gcc.gnu.org Cc: Kyrylo Tkachov Subject: RE: [EXTERNAL] [AArch64] PR105162: emit barrier for __sync and __atomic

Re: [AArch64] PR105162: emit barrier for __sync and __atomic builtins on CPUs without LSE

2022-04-19 Thread Wilco Dijkstra via Gcc-patches
Hi Sebastian, > Wilco pointed out in https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105162#c7​ > that > "Only __sync needs the extra full barrier, but __atomic does not." > The attached patch does that by adding out-of-line functions for > MEMMODEL_SYNC_*. > Those new functions contain a barrier o

Re: [AArch64] PR105162: emit barrier for __sync and __atomic builtins on CPUs without LSE

2022-04-18 Thread Pop, Sebastian via Gcc-patches
n the path without LSE instructions. I tested the patch on aarch64-linux with bootstrap and make check. Sebastian From: Pop, Sebastian Sent: Thursday, April 7, 2022 3:15 PM To: gcc-patches@gcc.gnu.org Cc: Kyrylo Tkachov Subject: [AArch64] PR105162: emit barrier for

[AArch64] PR105162: emit barrier for __sync and __atomic builtins on CPUs without LSE

2022-04-07 Thread Pop, Sebastian via Gcc-patches
Hi, With -moutline-atomics gcc stops generating a barrier for __sync builtins: https://gcc.gnu.org/PR105162 This is a problem on CPUs without LSE instructions where the ld/st exclusives do not guarantee a full barrier. The attached patch ad