Yuliang Wang writes:
> Thanks very much, updated.
>
> Regards,
> Yuliang
>
>
> gcc/ChangeLog:
>
> 2019-10-17 Yuliang Wang
>
> * config/aarch64/aarch64-sve2.md (aarch64_sve2_eor3)
> (aarch64_sve2_nor, aarch64_sve2_nand)
> (aarch64_sve2_bsl, aarch64_sve2_nbsl)
> (aarch64_s
On Wed, Oct 16, 2019 at 11:44:37PM +0100, Richard Sandiford wrote:
> Segher Boessenkool writes:
> >> If someone wants to add a new canonical form then the ports should of
> >> course adapt, but until then I think the patch is doing the right thing.
> >
> > We used to generate this, until GCC 5. T
\
+}
+
+TEMPLATE (8);
+TEMPLATE (16);
+TEMPLATE (32);
+TEMPLATE (64);
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect"
} } */
+
+/* { dg-final { scan-assembler-not {\tand\tz[0-9]+\.[bhsd]} } } */
+/* { dg-final { scan-assem
Yuliang Wang writes:
> Hi Richard,
>
> Thanks for the suggestions, updated.
>
> Regards,
> Yuliang
>
>
> gcc/ChangeLog:
>
> 2019-10-17 Yuliang Wang
>
> * config/aarch64/aarch64-sve2.md (aarch64_sve2_eor3)
> (aarch64_sve2_nor, aarch64_sve2_nand)
> (aarch64_sve2_bsl, aarch64_sve
\
+ for (int i = 0; i < n; i++) \
+a[i] = OP (b[i], c[i]);\
+}
+
+TEMPLATE (8);
+TEMPLATE (16);
+TEMPLATE (32);
+TEMPLATE (64);
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 &q
Segher Boessenkool writes:
> On Wed, Oct 16, 2019 at 09:04:18PM +0100, Richard Sandiford wrote:
>> Segher Boessenkool writes:
>> > This isn't canonical RTL. Does combine not simplify this?
>> >
>> > Or, rather, it should not be what we canonicalise to: nothing is defined
>> > here.
>>
>> But wh
On Wed, Oct 16, 2019 at 09:04:18PM +0100, Richard Sandiford wrote:
> Segher Boessenkool writes:
> > This isn't canonical RTL. Does combine not simplify this?
> >
> > Or, rather, it should not be what we canonicalise to: nothing is defined
> > here.
>
> But when nothing is defined, let's match wh
Segher Boessenkool writes:
> Hi,
>
> [ Please don't use application/octet-stream attachments. Thanks! ]
>
> On Wed, Oct 16, 2019 at 04:24:29PM +, Yuliang Wang wrote:
>> +;; Unpredicated bitwise select.
>> +(define_insn "*aarch64_sve2_bsl"
>> + [(set (match_operand:SVE_I 0 "register_operand"
Thanks for the patch, looks really good.
Yuliang Wang writes:
> +;; Use NBSL for vector NOR.
> +(define_insn_and_rewrite "*aarch64_sve2_nor"
> + [(set (match_operand:SVE_I 0 "register_operand" "=w, w, ?&w")
> + (unspec:SVE_I
> + [(match_operand 3)
> +(and:SVE_I
> + (no
Hi,
[ Please don't use application/octet-stream attachments. Thanks! ]
On Wed, Oct 16, 2019 at 04:24:29PM +, Yuliang Wang wrote:
> +;; Unpredicated bitwise select.
> +(define_insn "*aarch64_sve2_bsl"
> + [(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w")
> + (xor:SVE_I
> +
Hi,
This patch adds combine pass support for the following SVE2 bitwise logic
instructions:
- EOR3 (3-way vector exclusive OR)
- BSL (bitwise select)
- NBSL (inverted ")
- BSL1N (" with first input inverted)
- BSL2N (" with second input inverted)
Exam
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