[PATCH] Enable shrink wrapping for the RISC-V target.

This commit implements the target macros (TARGET_SHRINK_WRAP_*) that enable separate shrink wrapping for function prologues/epilogues in RISC-V. Tested against SPEC CPU 2017, this change always has a net-positive effect on the dynamic instruction count. See the following table for the breakdown o

[PATCH] Add pattern to convert vector shift + bitwise and + multiply to vector compare in some cases.

cmp w2, w1 bhi .L20 The effect is similar for x86-64. gcc/ChangeLog: * match.pd: Simplify vector shift + bit_and + multiply in some cases. gcc/testsuite/ChangeLog: * gcc.target/aarch64/swar_to_vec_cmp.c: New test. Signed-off-by: mtsamis --- gcc/match.pd