[PATCH] RISC-V: Fix double mode under RV32 not utilize vf

gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c: Ditto * gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c: Ditto Signed-off-by: demin.han --- gcc/config/riscv/vector.md| 3 ++- .../riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c | 4 ++-- .../riscv/r

[PATCH v2] RISC-V: More support of vx and vf for autovec comparison

There are still some cases which can't utilize vx or vf after last_combine pass. 1. integer comparison when imm isn't in range of [-16, 15] 2. float imm is 0.0 3. DI or DF mode under RV32 This patch fix above mentioned issues. Tested on RV32 and RV64. Signed-off-by: demin.han gcc

[PATCH] RISC-V: More support of vx and vf for autovec comparison

gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c: Ditto * gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c: Ditto * gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c: Ditto * gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c: Ditto Signed-off-by: demin.han --- gcc/config/riscv/

[PATCH v2] RISC-V: Remove integer vector eqne pattern

(*pred_eqne_scalar_narrow): Ditto (*pred_eqne_extended_scalar_merge_tie_mask): Ditto (*pred_eqne_extended_scalar): Ditto (*pred_eqne_extended_scalar_narrow): Ditto gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/integer-cmp-eqne.c: New test. Signed-off-by: demin.han

[PATCH v2] RISC-V: Remove float vector eqne pattern

(*pred_eqne_scalar): Ditto (*pred_eqne_scalar_narrow): Ditto gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-cmp-eqne.c: New test. Signed-off-by: demin.han --- v2 changes: 1. add test Only intrinsics utilize those removed vf patterns. Auto vectorization use vv

[PATCH] RISC-V: Minor fix for max_point

The program points start from 1, so max_point should be equal to length(). Tested on RV64 and no regression. gcc/ChangeLog: * config/riscv/riscv-vector-costs.cc: Use length() Signed-off-by: demin.han --- gcc/config/riscv/riscv-vector-costs.cc | 2 +- 1 file changed, 1 insertion(+), 1

[PATCH v2] RISC-V: Refine the condition for add additional vars in RVV cost model

/ChangeLog: * config/riscv/riscv-vector-costs.cc (non_contiguous_memory_access_p): Rename (need_additional_vector_vars_p): Rename and refine condition gcc/testsuite/ChangeLog: * gcc.dg/vect/costmodel/riscv/rvv/pr114506.c: New test. Signed-off-by: demin.han --- V2 changes

[PATCH] RISC-V: Refine the condition for add additional vars in RVV cost model

: * config/riscv/riscv-vector-costs.cc (non_contiguous_memory_access_p): Rename (need_additional_vector_vars_p): Rename and refine condition gcc/testsuite/ChangeLog: * gcc.dg/vect/costmodel/riscv/rvv/pr114506.c: New test. Signed-off-by: demin.han --- gcc/config/riscv

[PATCH v2] RISC-V: Fix ICE in riscv vector costs

ChangeLog: * gcc.dg/vect/costmodel/riscv/rvv/pr114264.c: New test. Signed-off-by: demin.han --- gcc/config/riscv/riscv-vector-costs.cc| 2 ++ .../gcc.dg/vect/costmodel/riscv/rvv/pr114264.c| 15 +++ 2 files changed, 17 insertions(+) create mode 100644 gcc/testsuite/gc

[PATCH] RISC-V: Fix ICE in riscv vector costs

)(samp + (long)Rb >> 1); } } One biggest_mode update missed in one branch and trigger assertion fail. gcc_assert (biggest_size >= mode_size); Tested On RV64 and no regression. gcc/ChangeLog: * config/riscv/riscv-vector-costs.cc: Fix ICE Signed-off-by: demin.han --- gcc/con

[PATCH] MAINTAINERS: Add myself to write after approval

ChangeLog: * MAINTAINERS: Add myself Signed-off-by: demin.han --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index b01fab16061..a681518d704 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -448,6 +448,7 @@ Wei Guozhi

[PATCH 4/5] RISC-V: Remove integer vector eqne pattern

(*pred_eqne_scalar_narrow): Ditto (*pred_eqne_extended_scalar_merge_tie_mask): Ditto (*pred_eqne_extended_scalar): Ditto (*pred_eqne_extended_scalar_narrow): Ditto Signed-off-by: demin.han --- gcc/config/riscv/predicates.md| 4 +- gcc/config/riscv/riscv-string.cc

[PATCH 3/5] RISC-V: Support vmfxx.vf for autovec comparison of vec and imm

/rvv/autovec/cmp/vcond-1.c: Add new tests Signed-off-by: demin.han --- gcc/config/riscv/autovec.md | 2 +- gcc/config/riscv/riscv-v.cc | 23 + gcc/config/riscv/riscv.cc | 2 +- .../riscv/rvv/autovec/cmp/vcond-1.c | 34

[PATCH 2/5] RISC-V: Refactor expand_vec_cmp

): Use default arguments (expand_vec_cmp_float): Adapt arguments Signed-off-by: demin.han --- gcc/config/riscv/riscv-protos.h | 2 +- gcc/config/riscv/riscv-v.cc | 44 +++-- 2 files changed, 15 insertions(+), 31 deletions(-) diff --git a/gcc/config/riscv

[PATCH 5/5] RISC-V: Support vmsxx.vx for autovec comparison of vec and imm

c_cmp): Ditto gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/cmp/vcond-1.c: Update expect Signed-off-by: demin.han --- gcc/config/riscv/riscv-v.cc | 33 --- .../riscv/rvv/autovec/cmp/vcond-1.c | 14 ++-- 2 files changed, 26 inser

[PATCH 1/5] RISC-V: Remove float vector eqne pattern

(*pred_eqne_scalar): Ditto (*pred_eqne_scalar_narrow): Ditto Signed-off-by: demin.han --- .../riscv/riscv-vector-builtins-bases.cc | 4 - gcc/config/riscv/vector.md| 86 --- 2 files changed, 90 deletions(-) diff --git a/gcc/config/riscv/riscv-vector

[PATCH 0/5] RISC-V: Support vf and vx for autovec comparison of

We expect: flw ... vmfxx.vf For simplicity of supporting vx and vf, two refactors completed first. 1. remove eqne pattern; any special case or reason for eqne when first added? 2. refactor duplicate code. demin.han (5): RISC-V: Remove float vector eqne pattern RISC-V: Refactor