Ping.
I have incorporated review comments from Peter in this revised patch. The
comment was to remove -mvsx option from dg-options as this is implied by
-mcpu=power8.
Ok for trunk?
Regards,
Surya
On 09/01/25 8:53 pm, Surya Kumari Jangala wrote:
> Ping
>
> On 02/12/24 2:20 pm, Sur
On 31/01/25 8:24 am, Michael Meissner wrote:
> Fix PR 118541, do not generate unordered fp cmoves for IEEE compares.
>
> In bug PR target/118541 on power9, power10, and power11 systems, for the
> function:
>
> extern double __ieee754_acos (double);
>
> double
> __acosp
ister is referenced in the RTL because any such
register usage should count as the "first" usage. A hard register
reference can occur in the RTL due to inline asm specifying a register
for a local variable, or a target’s machine pattern can explicitly
reference a hard register.
2025-01-2
On 08/01/25 2:30 pm, jeevitha wrote:
> Hi All,
>
> The following patch has been bootstrapped and regtested on powerpc64le-linux.
>
> Changes to amo.h include the addition of the following load atomic operations:
> Compare and Swap Not Equal, Fetch and Increment Bounded, Fetch and Increment
> E
Ping
On 02/12/24 2:20 pm, Surya Kumari Jangala wrote:
> I have incorporated review comments in this patch.
>
> Regards,
> Surya
>
>
> rs6000: Inefficient vector splat of small V2DI constants [PR107757]
>
> On P8, for vector splat of double word constants, s
one instruction (vspltisw)
for -1. And for constant 1, this patch generates two instructions
(vspltisw and vupkhsw).
2024-11-20 Surya Kumari Jangala
gcc/
PR target/107757
* config/rs6000/rs6000.cc (vspltisw_vupkhsw_constant_p):
Return false for -1 and return true for 1
generates two instructions
(vspltisw and vupkhsw).
2024-11-20 Surya Kumari Jangala
gcc/
PR target/107757
* config/rs6000/rs6000.cc (vspltisw_vupkhsw_constant_p):
Return false for -1 and return true for 1.
gcc/testsuite/
PR target/107757
* gcc.target/powerpc
Hi Segher,
Pinging the patch. Please let me know if it is ok for trunk.
Regards,
Surya
On 06/05/24 1:54 pm, Surya Kumari Jangala wrote:
> Ping
>
> On 08/01/24 11:19 am, Surya Kumari Jangala wrote:
>> Ping
>>
>> On 28/11/23 6:24 pm, Surya Kumari Jangala wrote:
>>
I am looking into this failure.
Thanks,
Surya
On 09/08/24 2:37 am, Andrew Pinski wrote:
> On Fri, Aug 2, 2024 at 7:30 AM Jeff Law wrote:
>>
>>
>>
>> On 8/1/24 4:12 AM, Surya Kumari Jangala wrote:
>>> lra: emit caller-save register spills before call insn [
spill now
occurs only in the path containing the call.
2024-08-01 Surya Kumari Jangala
gcc/
PR rtl-optimization/PR116028
* lra-constraints.cc (split_reg): Spill register before call
insn.
(latest_call_insn): New variable.
(inherit_in_ebb): Track the
Ping
On 08/01/24 11:19 am, Surya Kumari Jangala wrote:
> Ping
>
> On 28/11/23 6:24 pm, Surya Kumari Jangala wrote:
>> Ping
>>
>> On 10/11/23 12:27 pm, Surya Kumari Jangala wrote:
>>> Ping
>>>
>>> On 03/11/23 1:14 pm, Surya Kumari Jangala wrot
Ping
On 08/01/24 11:19 am, Surya Kumari Jangala wrote:
> Ping
>
> On 28/11/23 6:24 pm, Surya Kumari Jangala wrote:
>> Ping
>>
>> On 10/11/23 12:27 pm, Surya Kumari Jangala wrote:
>>> Ping
>>>
>>> On 03/11/23 1:14 pm, Surya Kumari Jangala wrot
Hi Ajit,
I have taken a quick look at the patch and my comments are inlined:
On 09/01/24 4:44 pm, Ajit Agarwal wrote:
> Hello All:
>
> This pass is registered before ira rtl pass.
> Bootstrapped and regtested for powerpc64-linux-gnu.
>
> No regressions for spec 2017 benchmarks and improvements f
Ping
On 28/11/23 6:24 pm, Surya Kumari Jangala wrote:
> Ping
>
> On 10/11/23 12:27 pm, Surya Kumari Jangala wrote:
>> Ping
>>
>> On 03/11/23 1:14 pm, Surya Kumari Jangala wrote:
>>> Hi Segher,
>>> I have incorporated changes in the code as per the
Ping
On 10/11/23 12:27 pm, Surya Kumari Jangala wrote:
> Ping
>
> On 03/11/23 1:14 pm, Surya Kumari Jangala wrote:
>> Hi Segher,
>> I have incorporated changes in the code as per the review comments provided
>> by you
>> for version 2 of the patch. Pleas
Ping
On 03/11/23 1:14 pm, Surya Kumari Jangala wrote:
> Hi Segher,
> I have incorporated changes in the code as per the review comments provided
> by you
> for version 2 of the patch. Please review.
>
> Regards,
> Surya
>
>
> rs6000/p8swap: Fix incorrect
.
- webs where swap(load(vector constant)) instructions are replaced with
load(swapped vector constant).
2023-09-10 Surya Kumari Jangala
gcc/
PR rtl-optimization/PR106770
* config/rs6000/rs6000-p8swap.cc (non_permuting_mem_insn): New function.
(handle_non_permuting_mem_insn
Hi Segher,
My replies are inlined:
On 29/10/23 10:16 am, Segher Boessenkool wrote:
> Hi!
>
> Please say "rs6000/p8swap:" in the subject, not "swap:" :-)
>
> On Sun, Sep 10, 2023 at 10:58:32PM +0530, Surya Kumari Jangala wrote:
>> Another issue with alway
Ping
On 03/10/23 3:53 pm, Surya Kumari Jangala wrote:
> Ping
>
> On 20/09/23 7:31 am, Surya Kumari Jangala wrote:
>> Ping
>>
>> On 10/09/23 10:58 pm, Surya Kumari Jangala wrote:
>>> swap: Fix incorrect lane extraction by vec_extract() [PR106770]
>>
and across a call will cause shrink wrap to fail.
2023-10-03 Surya Kumari Jangala
gcc/
PR rtl-optimization/111673
* ira-color.cc (assign_hard_reg): Scale save/restore costs of
callee save registers with block frequency.
gcc/testsuite/
PR rtl-optimization/111673
Ping
On 20/09/23 7:31 am, Surya Kumari Jangala wrote:
> Ping
>
> On 10/09/23 10:58 pm, Surya Kumari Jangala wrote:
>> swap: Fix incorrect lane extraction by vec_extract() [PR106770]
>>
>> In the routine rs6000_analyze_swaps(), special handling of swappable
>>
Ping
On 10/09/23 10:58 pm, Surya Kumari Jangala wrote:
> swap: Fix incorrect lane extraction by vec_extract() [PR106770]
>
> In the routine rs6000_analyze_swaps(), special handling of swappable
> instructions is done even if the webs that contain the swappable
> instructions ar
, overriding a
non-callee save register assigned to the pseudo by graph coloring. So
the entry basic block requires a prolog, thereby causing shrink wrap to
fail.
2023-09-14 Surya Kumari Jangala
gcc/
PR rtl-optimization/110071
* ira-color.cc (improve_allocation): Consider cost of callee
constant)) instructions are replaced with
load(swapped vector constant), the swappable instructions should not be
modified.
2023-09-10 Surya Kumari Jangala
gcc/
PR rtl-optimization/PR106770
* config/rs6000/rs6000-p8swap.cc (non_permuting_mem_insn): New
function
Ping
On 21/07/23 3:43 pm, Surya Kumari Jangala via Gcc-patches wrote:
> The improve_allocation() routine does not update the
> allocated_hardreg_p[] array after an allocno is assigned a register.
>
> If the register chosen in improve_allocation() is one that already has
> bee
to TRUE, so nothing needs to be
done.
But improve_allocation() can also choose a register that has not been
assigned to a conflicting allocno, and also has not been assigned to any
other allocno. In this case, allocated_hardreg_p[] has to be updated.
2023-07-21 Surya Kumari Jangala
gcc
On 25/02/23 3:20 pm, Ajit Agarwal via Gcc-patches wrote:
> Hello All:
>
> Here is the patch that uses xxlor instead of fmr where possible.
> Performance results shows that fmr is better in power9 and
> power10 architectures whereas xxlor is better in power7 and
> power 8 architectures. fmr is
On 21/04/23 8:51 pm, Ajit Agarwal via Gcc-patches wrote:
> +/* Return TRUE if the cfg has following properties.
> + bb1
> + |\
> + | \
> + | bb2
> + | /
> + bb3
> +
> + whereas bb1 has IF_THEN_ELSE and bb2 has the definition and bb3 has
> + zero/sign/AND extension
The issue of suboptimal code exists even for integer return value and not just
bool return value. See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103784#c9
So the patch would need to take care of integer return values too.
On 16/03/23 10:50 am, Ajit Agarwal via Gcc-patches wrote:
> Hello All:
>
On 27/02/23 9:58 pm, Segher Boessenkool wrote:
> Hi!
>
> On Wed, Jan 04, 2023 at 01:58:19PM +0530, Surya Kumari Jangala wrote:
>> In the routine rs6000_analyze_swaps(), special handling of swappable
>> instructions is done even if the webs that contain the swappable
&g
Hello,
Ping https://gcc.gnu.org/pipermail/gcc-patches/2023-January/609374.html
Thanks,
Surya
On 04/01/23 1:58 pm, Surya Kumari Jangala via Gcc-patches wrote:
> swap: Fix incorrect lane extraction by vec_extract() [PR106770]
>
> In the routine rs6000_analyze_swaps(), special ha
Ping. Please review the patch.
On 12/01/23 10:21 pm, Surya Kumari Jangala via Gcc-patches wrote:
> Ping
>
> On 04/01/23 1:58 pm, Surya Kumari Jangala via Gcc-patches wrote:
>> swap: Fix incorrect lane extraction by vec_extract() [PR106770]
>>
>> In the routine rs60
Ping
On 04/01/23 1:58 pm, Surya Kumari Jangala via Gcc-patches wrote:
> swap: Fix incorrect lane extraction by vec_extract() [PR106770]
>
> In the routine rs6000_analyze_swaps(), special handling of swappable
> instructions is done even if the webs that contain the swappable
> i
/stvx.
Similarly, in webs where swap(load(vector constant)) instructions are
replaced with load(swapped vector constant), the swappable
instructions should not be modified.
2023-01-04 Surya Kumari Jangala
gcc/
PR rtl-optimization/106770
* rs6000-p8swap.cc (rs6000_analyze_swaps
Hi Richard,
On 21/09/22 1:03 pm, Richard Biener wrote:
> On Tue, Sep 20, 2022 at 9:18 AM Surya Kumari Jangala via Gcc-patches
> wrote:
>>
>> Hi Jeff, Richard,
>> Thank you for reviewing the patch!
>> I have committed the patch to the gcc repo.
>> Can I back
testsuite: Fix failure in test pr105586.c [PR107171]
The test pr105586.c fails on a big endian system when run in 32bit
mode. The failure occurs as the test case does not guard against
unsupported __int128.
2022-10-13 Surya Kumari Jangala
gcc/testsuite/
PR testsuite/107171
wrote:
>
>
> On 8/23/2022 5:49 AM, Surya Kumari Jangala via Gcc-patches wrote:
>> sched1: Fix -fcompare-debug issue in schedule_region [PR105586]
>>
>> In schedule_region(), a basic block that does not contain any real insns
>> is not scheduled and the dfa state at
Hi Peter, Segher,
Thanks for going thru the patch!
I will make the proposed changes to the Changelog.
Regards,
Surya
On 23/08/22 6:58 pm, Segher Boessenkool wrote:
> Hi!
>
> On Tue, Aug 23, 2022 at 07:55:22AM -0500, Peter Bergner wrote:
>> It looks good to me, but I cannot approve it.
>
> Same
ot contain real insns.
2022-08-22 Surya Kumari Jangala
gcc/
PR rtl-optimization/105586
* sched-rgn.cc (schedule_region): Always copy dfa state to
fallthru block.
gcc/testsuite/
PR rtl-optimization/105586
* gcc.target/powerpc/pr105586.c: New test.
diff -
need
not be the same as the rest of the elements in the du chain. This
was resulting in fcompare-debug failure as check_new_reg_p was returning a
different result with -g for the same candidate register. We can instead obtain
nregs from the du chain itself.
2022-06-10 Surya Kumari Jangala
gcc
2022-05-13 Surya Kumari Jangala
* MAINTAINERS: Add myself to write after approval.
diff --git a/MAINTAINERS b/MAINTAINERS
index a1b84ac5646..8bca7a636b7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -464,6 +464,7 @@ Daniel Jacobowitz
Andreas Jaeger
Harsha Jagasia
Fariborz Jahanian
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