[PATCH][RISC-V][PR target/70557] Improve storing 0 to memory on rv32

2025-05-21 Thread Shreya Munnangi
Patch is originally from Siarhei Volkau . RISC-V has a zero register (x0) which we can use to store zero into memory without loading the constant into a distinct register. Adjust the constraints of the 32-bit movdi_32bit pattern to recognize that we can store 0.0 into memory using x0 as the source

[PATCH][RISC-V][PR target/70557] Improve storing 0 to memory on rv32

2025-05-21 Thread Shreya Munnangi
Patch is originally from Siarhei Volkau . RISC-V has a zero register (x0) which we can use to store zero into memory without loading the constant into a distinct register. Adjust the constraints of the 32-bit movdi_32bit pattern to recognize that we can store 0.0 into memory using x0 as the source