Re: [PATCH 2/3] RISC-V: Additional large constant synthesis improvements

On Thu, Sep 5, 2024 at 3:41 PM Jeff Law wrote: > > > > On 9/5/24 12:38 PM, Raphael Zinsly wrote: > > On Thu, Sep 5, 2024 at 3:10 PM Jeff Law wrote: > >> On 9/5/24 6:16 AM, Raphael Zinsly wrote: > >>> On Wed, Sep 4, 2024 at 8:32 PM Jeff Law wrote: > >

Re: [PATCH 2/3] RISC-V: Additional large constant synthesis improvements

On Thu, Sep 5, 2024 at 3:10 PM Jeff Law wrote: > On 9/5/24 6:16 AM, Raphael Zinsly wrote: > > On Wed, Sep 4, 2024 at 8:32 PM Jeff Law wrote: > >> On 9/2/24 2:01 PM, Raphael Moreira Zinsly wrote: > >> ... > >>> + bool bit31 = (hival & 0x8000

Re: [PATCH 3/3] RISC-V: Constant synthesis of inverted halves

On Wed, Sep 4, 2024 at 8:35 PM Jeff Law wrote: > On 9/2/24 2:01 PM, Raphael Moreira Zinsly wrote: >... > > +unsigned long foo_0x4afe605fb5019fa0(void) { return 0x4afe605fb5019fa0UL; } > > +unsigned long foo_0x07a80d21f857f2de(void) { return 0x07a80d21f857f2deUL; } > > +unsigned long foo_0x6699f19c

Re: [PATCH 2/3] RISC-V: Additional large constant synthesis improvements

On Wed, Sep 4, 2024 at 8:32 PM Jeff Law wrote: > On 9/2/24 2:01 PM, Raphael Moreira Zinsly wrote: > ... > > + bool bit31 = (hival & 0x8000) != 0; > > + int trailing_shift = ctz_hwi (loval) - ctz_hwi (hival); > > + int leading_shift = clz_hwi (loval) - clz_hwi (hival); > > +

Re: [PATCH v2] RISC-V: Add support to vector stack-clash protection

On Thu, Aug 1, 2024 at 3:40 PM Jeff Law wrote: > On 8/1/24 6:01 AM, Raphael Moreira Zinsly wrote: > > +/* Both prologue temp registers are used in the vector probe loop for when > > + stack-clash protection is enabled, so we need to copy SP to a new > > register > > + and set it as CFA during

Re: [PATCH 4/5] RISC-V: Add support to vector stack-clash protection

On Tue, Jul 30, 2024 at 4:29 PM Jeff Law wrote: >... > You define: > +#define RISCV_STACK_CLASH_VECTOR_CFA_REGNUM (GP_TEMP_FIRST + 4) > > Where: > #define GP_REG_FIRST 0 > #define GP_TEMP_FIRST (GP_REG_FIRST + 5) > > So RISCV_STACK_CLASH_VECTOR_CFA_REGNUM defined as "9" which I think is > "s1". T

Re: [PATCH 4/5] RISC-V: Add support to vector stack-clash protection

On Mon, Jul 29, 2024 at 11:20 AM Jeff Law wrote: > > > > On 7/29/24 6:18 AM, Raphael Zinsly wrote: > > On Fri, Jul 26, 2024 at 6:48 PM Jeff Law wrote: > >> > >> > >> > >> On 7/24/24 12:00 PM, Raphael Moreira Zinsly wrote: > >>> A

Re: [PATCH 4/5] RISC-V: Add support to vector stack-clash protection

On Fri, Jul 26, 2024 at 6:48 PM Jeff Law wrote: > > > > On 7/24/24 12:00 PM, Raphael Moreira Zinsly wrote: > > Adds basic support to vector stack-clash protection using a loop to do > > the probing and stack adjustments. > > > > gcc/ChangeLog: > > * config/riscv/riscv.cc > > (riscv_all

Re: [PATCH 1/5] RISC-V: Small stack tie changes

On Fri, Jul 26, 2024 at 2:00 PM Jeff Law wrote: > On 7/24/24 12:00 PM, Raphael Moreira Zinsly wrote: > ... > > diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md > > index 46c46039c33..5780c5abacf 100644 > > --- a/gcc/config/riscv/riscv.md > > +++ b/gcc/config/riscv/riscv.md > > @@

Re: [PATCH] RISC-V: Optimize min/max with SImode sources on 64-bit

On Wed, Dec 28, 2022 at 10:36 PM Jeff Law wrote: > > > > On 12/28/22 11:18, Raphael Moreira Zinsly wrote: > > The Zbb min/max pattern was not matching 32-bit sources when > > compiling for 64-bit. > > This patch separates the pattern into SImode and DImode, and > > use a define_expand to handle SI