On 1/7/25 10:25, Patrick O'Neill wrote:
On 1/7/25 10:18, Richard Sandiford wrote:
Jeff Law writes:
On 1/7/25 2:09 AM, Tsung Chun Lin wrote:
Hi,
Could someone help merge this patch if there are no further concerns?
It'll get addressed. Many contributors have been on holid
From: Jim Tsung-Chun Lin
Re-sending this via git send-email to avoid the application/octet-stream
attachement type that prevents Patchworks/CI from finding the patch.
---
Don't use the QI vector if its size is equal to UNITS_PER_WORD for
better code generation.
Before patch:
vsetivliz
On 1/7/25 10:18, Richard Sandiford wrote:
Jeff Law writes:
On 1/7/25 2:09 AM, Tsung Chun Lin wrote:
Hi,
Could someone help merge this patch if there are no further concerns?
It'll get addressed. Many contributors have been on holiday and are
still catching up.
FWIW, I'm happy to push the
On 1/7/25 07:37, Andreas Schwab wrote:
gcc:
PR target/118137
* config/riscv/sync.md ("lrsc_atomic_exchange"): Apply mask
to shifted value.
gcc/testsuite:
PR target/118137
* gcc.dg/atomic/pr118137.c: New.
---
Thanks for fixing this - I can't give approva
On 11/18/24 10:30, Jeff Law wrote:
On 11/18/24 11:09 AM, Patrick O'Neill wrote:
On 11/18/24 09:57, Jeff Law wrote:
And stage3 begins...
Zdenek's fuzzer caught this one. Essentially using
simplify_gen_subreg directly with an offset of 0 when we just needed
a lowpart.
The o
On 11/18/24 09:57, Jeff Law wrote:
And stage3 begins...
Zdenek's fuzzer caught this one. Essentially using
simplify_gen_subreg directly with an offset of 0 when we just needed a
lowpart.
The offset of 0 works for little endian, but for big endian it's
simply wrong. simplify_gen_subreg wil
From: Greg McGary
Add option -m(no-)autovec-segment to enable/disable autovectorizer
from emitting vector segment load/store instructions. This is useful for
performance experiments.
gcc/ChangeLog:
* config/riscv/autovec.md (vec_mask_len_load_lanes,
vec_mask_len_store_lanes):
On 10/11/24 09:16, Patrick O'Neill wrote:
Sending this with a text attachment to see if patchworks accepts a
'text/x-patch' attachment type.
Review can still happen on the original thread:
https://inbox.sourceware.org/gcc-patches/cafryf0mmb9hs9cng4w8y5n06d+4tfuvg
technical difficulties Tsung Chun!
- Patrick
From 9b37cebb78d6f0e4fa1c6555ccdda4b946daca88 Mon Sep 17 00:00:00 2001
From: Patrick O'Neill
Date: Tue, 23 Jan 2024 16:36:53 -0800
Subject: [PATCH] RISC-V: Add regression test for vsetvl bug pr113429
The reduced testcase for pr113429 (cam4 failure) ne
On 10/9/24 14:50, Jeff Law wrote:
On 10/9/24 3:21 PM, Patrick O'Neill wrote:
On 10/9/24 14:07, Jeff Law wrote:
Also note that if you use the tag "[RISC-V]" in your subject line
your patch will be automatically picked up by a pre-commit tester
that can be subsequen
On 10/9/24 14:07, Jeff Law wrote:
Also note that if you use the tag "[RISC-V]" in your subject line your
patch will be automatically picked up by a pre-commit tester that can
be subsequently examined to verify behavior.
This patch's subject line looks good to me. It would've been picked u
On Mon, Sep 2, 2024 at 11:54 AM Jeff Law wrote:
>
> This time with the RISC-V marker so the pre-commit testing system will
> pick it up...
Hi Jeff,
Just a meta-note about precommit:
If the patch contains riscv or risc-v anywhere in the patch file pre commit
will run [1]. You can also cc patchw
Thanks for the ping - It's running now:
https://github.com/ewlu/gcc-precommit-ci/issues/2146
Patrick
On 8/27/24 18:22, Li, Pan2 wrote:
Hi Patrick,
Could you please help to re-trigger the pre-commit?
Thanks in advance!
Pan
-Original Message-
From: Patrick O'Neill
Sen
On 8/27/24 08:04, Jeff Law wrote:
On 8/26/24 6:37 PM, Patrick O'Neill wrote:
These subroutines will be used in expand_const_vector in a future patch.
Relocate so expand_const_vector can use them.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (expand_vector_init_insert_elems):
Rel
On 8/27/24 08:04, Jeff Law wrote:
On 8/26/24 6:37 PM, Patrick O'Neill wrote:
Currently we assert when encountering a non-duplicate boolean vector.
This patch allows non-duplicate vectors to fall through to the
gcc_unreachable and assert there.
This will be useful when adding a catc
On 8/27/24 08:02, Jeff Law wrote:
On 8/26/24 6:36 PM, Patrick O'Neill wrote:
The comment previously here stated that the Wc0/Wc1 cases are handled by
the vi constraint but that is not true for the 0.0 Wc0 case.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_const_insns): Handl
On 8/27/24 08:01, Jeff Law wrote:
On 8/26/24 6:36 PM, Patrick O'Neill wrote:
These cases are handled in the expander
(riscv-v.cc:expand_const_vector). We need the vector builder to detect
these cases so extract that out into a new riscv-v.h header file.
gcc/ChangeLog:
* config/
On 8/27/24 08:00, Jeff Law wrote:
On 8/26/24 6:36 PM, Patrick O'Neill wrote:
This manifests in RTL that is optimized away which causes runtime
failures
in the testsuite. Update all patterns to use a temp result register
if required.
gcc/ChangeLog:
* config/riscv/riscv
On 8/27/24 07:56, Jeff Law wrote:
On 8/26/24 6:36 PM, Patrick O'Neill wrote:
The corresponding expander (riscv-v.cc:expand_const_vector) matches
const_vec_duplicate_p before const_vec_series_p. Reorder to match this
behavior when calculating costs.
gcc/ChangeLog:
* config/
On 8/27/24 07:55, Jeff Law wrote:
On 8/26/24 6:36 PM, Patrick O'Neill wrote:
Prior to this patch the expander would emit vectors like:
{ 0, 0, 5, 5, 10, 10, ...}
as:
{ 0, 0, 2, 2, 4, 4, ...}
This patch sets the step size to the requested value.
gcc/ChangeLog:
* config/riscv/
On 8/27/24 08:19, Jeff Law wrote:
On 8/26/24 6:37 PM, Patrick O'Neill wrote:
This patch adds some advanced checking to assert that the emitted
costs match
emitted patterns for const_vecs.
Flow:
Costing: Insert into hashmap>
Expand: Check for membership in hashmap
-> Not
These subroutines will be used in expand_const_vector in a future patch.
Relocate so expand_const_vector can use them.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (expand_vector_init_insert_elems): Relocate.
(expand_vector_init_trailing_same_elem): Ditto.
Signed-off-by: Patrick
The comment previously here stated that the Wc0/Wc1 cases are handled by
the vi constraint but that is not true for the 0.0 Wc0 case.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_const_insns): Handle 0.0 floating-point
case.
Signed-off-by: Patrick O'Neill
---
Ack&#
* config/riscv/riscv.cc (riscv_const_insns): Ditto.
* config/riscv/riscv-v.h (insert_expected_pattern): Add helper function
to insert hash collisions into hash map vec key.
(get_expected_costed_type): Add helper function to get the expected
cost type for a given rtx pattern
The corresponding expander (riscv-v.cc:expand_const_vector) matches
const_vec_duplicate_p before const_vec_series_p. Reorder to match this
behavior when calculating costs.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_const_insns): Relocate.
Signed-off-by: Patrick O'Neill
---
This manifests in RTL that is optimized away which causes runtime failures
in the testsuite. Update all patterns to use a temp result register if required.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (expand_const_vector): Use tmp register if
needed.
Signed-off-by: Patrick O'
/rvv/autovec/materialize-3.c: New test.
* gcc.target/riscv/rvv/autovec/materialize-4.c: New test.
* gcc.target/riscv/rvv/autovec/materialize-5.c: New test.
* gcc.target/riscv/rvv/autovec/materialize-6.c: New test.
Signed-off-by: Patrick O'Neill
---
This causes
/riscv/riscv-v.cc (expand_const_vector): Allow non-duplicate
to fall through other patterns before asserting.
Signed-off-by: Patrick O'Neill
---
gcc/config/riscv/riscv-v.cc | 23 ---
1 file changed, 8 insertions(+), 15 deletions(-)
diff --git a/gcc/config/riscv/
/riscv.cc (riscv_const_insns): Emit placeholder costs for
bool/stepped const vectors.
* config/riscv/riscv-v.h: New file.
Signed-off-by: Patrick O'Neill
---
Ack'd here:
https://inbox.sourceware.org/gcc-patches/cd634c30-caf0-4375-a623-d9cd86498...@gmail.com/
---
gcc/config/r
: Patrick O'Neill
---
Detected with the existing testsuite after patch 8/9 is applied:
FAIL: gcc.dg/torture/vshuf-v16qi.c -O2 execution test
FAIL: gcc.dg/torture/vshuf-v8hi.c -O2 execution test
FAIL: gcc.dg/torture/vshuf-v8qi.c -O2 execution test
---
gcc/config/riscv/riscv-v.cc
* Reorder "Handle 0.0 floating point pattern ..." to use riscv-v.h.
* Fix build failure on patches 6-8 that was previously fixed by patch 9.
* Append RFC to series.
Patrick O'Neill (9):
RISC-V: Fix vid const vector expander for non-npatterns size steps
RISC-V: Reorder insn cost match
On 8/22/24 13:45, Robin Dapp wrote:
+ /* Constants in range -16 ~ 15 integer or 0.0 floating-point
+ can be emitted using vmv.v.i. */
+ if (satisfies_constraint_vi (x) || satisfies_constraint_Wc0 (x))
return 1;
Just a nit but whil
On 8/22/24 13:41, Robin Dapp wrote:
Before looking at the rest (tomorrow) - this is OK.
Committed - thanks!
Patrick
On 8/22/24 12:46, Patrick O'Neill wrote:
These cases are handled in the expander
(riscv-v.cc:expand_const_vector). We need the vector builder to detect
these cases so extract that out into a new riscv-v.h header file.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (class rvv_builder):
These subroutines will be used in expand_const_vector in a future patch.
Relocate so expand_const_vector can use them.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (expand_vector_init_insert_elems): Relocate.
(expand_vector_init_trailing_same_elem): Ditto.
Signed-off-by: Patrick
/riscv/riscv-v.cc (expand_const_vector): Allow non-duplicate
to fall through other patterns before asserting.
Signed-off-by: Patrick O'Neill
---
gcc/config/riscv/riscv-v.cc | 23 ---
1 file changed, 8 insertions(+), 15 deletions(-)
diff --git a/gcc/config/riscv/
uestions:
* How heavy-weight is it to store a copy of every costed
const RTX vector (and ideally other costed expressions later).
* Does this belong in release or gated behind rtx checking?
Signed-off-by: Patrick O'Neill
---
gcc/config/riscv/riscv-v.cc | 29 +
g
/riscv.cc (riscv_const_insns): Emit placeholder costs for
bool/stepped const vectors.
* config/riscv/riscv-v.h: New file.
Signed-off-by: Patrick O'Neill
---
gcc/config/riscv/riscv-v.cc | 53 +-
gcc/config/riscv/riscv-v.h | 88 +
This manifests in RTL that is optimized away which causes runtime failures
in the testsuite. Update all patterns to use a temp result register if required.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (expand_const_vector): Use tmp register if
needed.
Signed-off-by: Patrick O'
The corresponding expander (riscv-v.cc:expand_const_vector) matches
const_vec_duplicate_p before const_vec_series_p. Reorder to match this
behavior when calculating costs.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_const_insns): Relocate.
Signed-off-by: Patrick O'Neill
---
::can_duplicate_repeating_sequence_p):
Use encoded_nelts when calling repeating_sequence_p.
(rvv_builder::is_repeating_sequence): Ditto.
(rvv_builder::repeating_sequence_use_merge_profitable_p): Ditto.
Signed-off-by: Patrick O'Neill
---
gcc/config/riscv/riscv-v.cc | 10 +++-
/rvv/autovec/materialize-3.c: New test.
* gcc.target/riscv/rvv/autovec/materialize-4.c: New test.
* gcc.target/riscv/rvv/autovec/materialize-5.c: New test.
* gcc.target/riscv/rvv/autovec/materialize-6.c: New test.
Signed-off-by: Patrick O'Neill
---
This causes
The comment previously here stated that the Wc0/Wc1 cases are handled by
the vi constraint but that is not true for the 0.0 Wc0 case.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_const_insns): Handle 0.0 floating-point
case.
Signed-off-by: Patrick O'Neill
---
gcc/config/
: Patrick O'Neill
---
gcc/config/riscv/riscv-v.cc | 48 -
1 file changed, 42 insertions(+), 6 deletions(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index c89603669e3..a3039a2cb19 100644
--- a/gcc/config/riscv/riscv-v.cc
+++
Constant vectors are currently spilled/loaded from memory often. This series
increases the number of costed patterns via a catch-all pattern and fixes a
variety of bugs I found along the way.
Patrick O'Neill (9):
RISC-V: Use encoded nelts when calling repeating_sequence_p
RISC-V: Fi
https://inbox.sourceware.org/gcc-patches/cafiyyc09+uadzt-pg6etnnhf16jmo70q4u9upnqg+wme-vy...@mail.gmail.com/
On 5/29/24 17:05, Patrick O'Neill wrote:
From: Greg McGary
Add option -m(no-)autovec-segment to enable/disable autovectorizer
from emitting vector segment load/store instructions. This
Hi Pan,
Once the postcommit baseline moves forward (trunk is currently failing
to build linux targets [1] [2]) I'll re-trigger precommit for you.
Thanks,
Patrick
[1]: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116409
[2]: https://github.com/patrick-rivos/gcc-postcommit-ci/issues/1564
On 8/
On 8/5/24 15:29, Patrick O'Neill wrote:
This fixes the remainder of the typos I found when reading various parts of the
RISC-V backend.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (legitimize_move): extrac -> extract.
(expand_vec_cmp_float): Remove duplicate
Hi Jin Ma,
Precommit has flagged a large number of ICEs with this patch on vector
targets when applied to yesterday's daily bump[1]:
https://github.com/ewlu/gcc-precommit-ci/issues/2037#issuecomment-2277469412
Thanks,
Patrick
[1]
https://github.com/gcc-mirror/gcc/commit/77ccfa6ac8d6e4dfefdea
On 8/5/24 20:20, Jeff Law wrote:
On 8/5/24 4:29 PM, Patrick O'Neill wrote:
This fixes typos in function names and executed code.
gcc/ChangeLog:
* config/riscv/riscv-target-attr.cc (num_occurences_in_str):
Rename...
(num_occurrences_in_str): here.
(riscv_process_target
On 8/5/24 20:19, Jeff Law wrote:
On 8/5/24 4:29 PM, Patrick O'Neill wrote:
This fixes most of the typos I found when reading various parts of
the RISC-V
backend.
Comment typos are always OK to fix under the "obvious" rule. No need
to wait for an ACK.
Jeff
Committed.
Patrick
On 8/6/24 09:12, Palmer Dabbelt wrote:
On Tue, 06 Aug 2024 09:07:26 PDT (-0700), Patrick O'Neill wrote:
gcc/ChangeLog:
PR target/116152
* config/riscv/riscv.cc (riscv_option_override): Fix url
formatting.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/predef-9.c: U
gcc/ChangeLog:
PR target/116152
* config/riscv/riscv.cc (riscv_option_override): Fix url
formatting.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/predef-9.c: Update testcase.
Co-authored-by: Jakub Jelinek
Signed-off-by: Patrick O'Neill
---
Tested using r
On 8/5/24 07:21, Jeff Law wrote:
On 7/30/24 6:32 PM, Patrick O'Neill wrote:
gcc/ChangeLog:
PR 116152
* config/riscv/riscv.cc (riscv_option_override): Add deprecation
warning.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/predef-9.c: Add check for warning.
OK
jeff
Re
gcc/ChangeLog:
PR target/116152
* config/riscv/riscv.cc (riscv_option_override): Add deprecation
warning.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/predef-9.c: Add check for warning.
Signed-off-by: Patrick O'Neill
---
gcc/config/riscv/ris
ins -> insns.
* config/riscv/riscv.cc (riscv_init_machine_status): mwrvv -> mrvv.
* config/riscv/vector-iterators.md: RVVM8QImde -> RVVM8QImode
* config/riscv/vector.md: Replaced non-existant vsetivl with vsetivli.
Signed-off-by: Patrick O'Neill
---
I split thes
/vector.md: Ditto.
* config/riscv/zc.md: Ditto.
Signed-off-by: Patrick O'Neill
---
gcc/config/riscv/arch-canonicalize| 2 +-
gcc/config/riscv/autovec.md | 2 +-
gcc/config/riscv/riscv-avlprop.cc | 8 ++---
gcc/config/riscv/riscv-mode
tor-crypto.md: boardcast_scalar -> broadcast_scalar.
* config/riscv/vector.md: Ditto.
Signed-off-by: Patrick O'Neill
---
Relying on precommit for full testing.
---
gcc/config/riscv/riscv-target-attr.cc | 4 +-
gcc/config/riscv/riscv-v.cc | 10 +--
gcc/config/riscv/r
On 8/5/24 01:23, Liao Shihua wrote:
PR 116150: Zvk* and Zvb* extensions requires v or zve* extension, but
on gcc v is implied.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Removed the zvk extension's
implicit expansion of v extension.
* config/riscv/arch-
On 8/2/24 07:10, Jeff Law wrote:
On 8/1/24 10:25 PM, Patrick O'Neill wrote:
gcc/ChangeLog:
* config/riscv/sync-rvwmo.md: Add conditional length attributes.
* config/riscv/sync-ztso.md: Ditto.
* config/riscv/sync.md: Fix incorrect insn length attributes and
reformat exi
gcc/ChangeLog:
* config/riscv/sync-rvwmo.md: Add conditional length attributes.
* config/riscv/sync-ztso.md: Ditto.
* config/riscv/sync.md: Fix incorrect insn length attributes and
reformat existing conditional checks.
Signed-off-by: Patrick O'Neill
---
: New test.
Signed-off-by: Patrick O'Neill
---
gcc/config/riscv/riscv.cc | 5 +
gcc/testsuite/gcc.target/riscv/arch-41.c | 7 +++
gcc/testsuite/gcc.target/riscv/pr116111.c | 7 +++
3 files changed, 19 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/ar
gcc/ChangeLog:
PR 116152
* config/riscv/riscv.cc (riscv_option_override): Add deprecation
warning.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/predef-9.c: Add check for warning.
Signed-off-by: Patrick O'Neill
---
v2 ChangeLog:
Shorten message and split
On 7/30/24 16:08, Andrew Pinski wrote:
On Tue, Jul 30, 2024 at 4:04 PM Patrick O'Neill wrote:
gcc/ChangeLog:
PR 116152
* config/riscv/riscv.cc (riscv_option_override): Add deprecation
warning.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/predef-9.c
gcc/ChangeLog:
PR 116152
* config/riscv/riscv.cc (riscv_option_override): Add deprecation
warning.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/predef-9.c: Add check for warning.
Signed-off-by: Patrick O'Neill
---
Tested prior to adding link. Relyi
Also add a testcase for -mabi=lp64d where 'd' is required.
gcc/ChangeLog:
PR 116111
* config/riscv/riscv.cc (riscv_option_override):
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-41.c: New test.
* gcc.target/riscv/pr116111.c: New test.
Signed-off-b
Committed w/changelog fixup/sign-off and sent final version to the lists
here:
https://inbox.sourceware.org/gcc-patches/20240730152448.4089002-1-patr...@rivosinc.com/T/#u
Approved during risc-v patchworks meeting by Jeff Law.
Patrick
On 7/29/24 15:13, Patrick O'Neill wrote:
From: Gia
test.
* gcc.target/riscv/amo/zacas-ztso-compare-exchange-short.c: New test.
Co-authored-by: Patrick O'Neill
Tested-by: Andrea Parri
Signed-Off-By: Gianluca Guida
---
Added missing riscv-common.cc changelog entry and Gianluca Guida's sign-off
that he gave.
---
gcc/common/co
Committed with spaces -> tabs ChangeLog fix.
Patrick
On 7/29/24 20:27, Kito Cheng wrote:
LGTM, thanks :)
On Tue, Jul 30, 2024 at 10:53 AM Patrick O'Neill wrote:
This patch removes the zabha configure check since it's not a breaking change
and updates the existing zaamo/zalrsc
zaamo/zalrsc comment.
* config.in: Regenerate.
* configure: Regenerate.
* configure.ac: Remove zabha configure check.
Signed-off-by: Patrick O'Neill
---
The user has to specify zabha in order for binutils to throw an error.
This is in contrast to zaamo/zalrsc which ar
-short.c: New test.
Co-authored-by: Patrick O'Neill
Tested-by: Andrea Parri
---
V3 Changelog:
* Make insn lengths dynamic to account for leading fence.
* Remove config-check for old binutils versions.
Tested locally with zaamo, zalrsc, ztso, and zacas with amo.exp.
---
V2 Changelog
* Fix funct
On 7/26/24 06:30, Richard Biener wrote:
On Thu, May 30, 2024 at 2:11 AM Patrick O'Neill wrote:
From: Greg McGary
gcc/ChangeLog:
* gcc/tree-vect-stmts.cc (gcc/tree-vect-stmts.cc): Prevent
divide-by-zero.
* testsuite/gcc.target/riscv/rvv/autovec/no-segment.c: Remove d
On 7/23/24 19:48, Kito Cheng wrote:
I incline do not add skip_zacas stuffs (although skip_zabha is already
there but that's fine), because that's different situation compare to
the zaamo/zalrsc, zaamo/zalrsc should automatically append if a
extension is available, which is new behavior and new ex
On 7/24/24 08:37, Robin Dapp wrote:
It's really GCC's implementation of the V extension that requires M, not
the actul ISA V extension. So I think the wording could be a little
confusing for users here, but no big deal either way on my end so
Reviewed-by: Palmer Dabbelt
Hmm, fair. How abou
(define_expand "atomic_compare_and_swap"
[(match_operand:SI 0 "register_operand" "") ;; bool output
(match_operand:GPR 1 "register_operand" "") ;; val output
(match_operand:GPR 2 "memory_operand" "");; memory
- (match_operand:GPR 3 "reg_or_0_operand" "") ;; expected value
-cst.c: New
test.
* gcc.target/riscv/amo/zacas-ztso-compare-exchange-int.c: New test.
* gcc.target/riscv/amo/zacas-ztso-compare-exchange-short-seq-cst.c: New
test.
* gcc.target/riscv/amo/zacas-ztso-compare-exchange-short.c: New test.
Co-authored-by: Patrick O'Neill
-
On 7/8/24 13:36, Jeff Law wrote:
On 7/8/24 1:25 PM, Patrick O'Neill wrote:
https://gcc.gnu.org/onlinedocs/gccint/Machine-Independent-Predicates.html
| Function: const_int_operand
| This predicate allows any CONST_INT expression that fits in
mode. It is an appropriate choice f
On 7/6/24 07:20, Jeff Law wrote:
On 7/3/24 3:16 PM, Patrick O'Neill wrote:
Regarding the amocas.q follow-up patch:
I'm having trouble with matching any TImode compare-and-swap
patterns. Here's the RTL I'm trying:
(define_mode_iterator SUPERGPR [SI D
On 7/6/24 06:50, Jeff Law wrote:
On 7/2/24 7:28 PM, Patrick O'Neill wrote:
gcc/ChangeLog:
* doc/invoke.texi: Remove trailing whitespace.
OK
jeff
Committed.
Patrick
0627 (experimental)"
.section.note.GNU-stack,"",@progbits
The SI/DI patterns match fine but TI generates a call.
I've also tried doing things similar to:
(define_expand "mulditi3"
where only the define_expand has TImode operands and the define_
-authored-by: Patrick O'Neill
---
Gianluca Guida created the initial patch. Rebased and added more
testcases/docs/etc.
Tested using amo.exp with rv64gc_zalrsc and rv64gc_ztso.
Relying on precommit for full testing.
---
gcc/common/config/riscv/riscv-common.cc | 11 +++
gcc/conf
Committed.
Patrick
On 7/2/24 18:29, Kito Cheng wrote:
LGTM, BTW, based on the discussion[1], my understanding is: depend
== require == imply for the RISC-V ISA spec.
[1]
https://github.com/riscv/riscv-v-spec/issues/723#issuecomment-922153867
On Wed, Jul 3, 2024 at 9:21 AM Patrick O'
Committed w/ fixup to changelog to add missing:
* lib/target-supports.exp: Add zabha testsuite infra support.
Patrick
On 7/2/24 18:05, Patrick O'Neill wrote:
From: Gianluca Guida
The Zabha extension adds support for subword Zaamo ops.
Extension: https://github.com/riscv/riscv-zabh
gcc/ChangeLog:
* doc/invoke.texi: Remove trailing whitespace.
Signed-off-by: Patrick O'Neill
---
gcc/doc/invoke.texi | 392 ++--
1 file changed, 196 insertions(+), 196 deletions(-)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
From: Palmer Dabbelt
gcc/ChangeLog:
* doc/invoke.texi: Describe -march behavior for dependent extensions on
RISC-V.
---
Ok'd by Jeff Law here:
https://inbox.sourceware.org/gcc-patches/fae68675-519f-4d80-b0fb-dfd5d8a22...@gmail.com/
I'll let it sit on the lists overnight and comm
/amo/zabha-ztso-amo-add-short.c: New test.
Co-Authored-By: Patrick O'Neill
Signed-Off-By: Gianluca Guida
Tested-by: Andrea Parri
---
v2 ChangeLog:
Rebase to resolve conflict with testsuite cleanup. Regenerate gcc/testsuite
ChangeLog.
Add Signed-Off-By that Gianluca gave.
Ok'd by Jef
Hi Feng,
Precommit results for the series:
https://github.com/ewlu/gcc-precommit-ci/issues/1809#issuecomment-2193980567
https://patchwork.sourceware.org/project/gcc/patch/20240627070121.32461-3-wangf...@eswincomputing.com/
It looks like there are 5 minor testsuite failures added.
Log from t
On 6/25/24 14:34, Jeff Law wrote:
On 6/25/24 3:14 PM, Patrick O'Neill wrote:
This is another round of AMO testcase cleanup. Consolidates a lot of
testcases
and unifies the testcase names.
Patrick O'Neill (3):
RISC-V: Rename amo testcases
RISC-V: Consolidate amo testcas
On 6/26/24 08:50, Andrea Parri wrote:
Tested using amo.exp with rv64gc_zalrsc, rv64id_zaamo, rv64id_zalrsc,
rv64id_zabha (using tip-of-tree qemu w/ zabha patches [2] applied for
execution tests).
My interpretation of the Zabha specification, in particular of "The Zabha
extension depends upon th
: New test.
Co-Authored-By: Patrick O'Neill
---
Gianluca Guida created the initial patch. Rebased and added more
testcases/docs/etc.
This will trivially conflict with the testsuite cleanup [1] I sent but
I'll rebase as needed.
Tested using amo.exp with rv64gc_zalrsc, rv64id_zaamo, rv6
.
* gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-relaxed.c:
Ditto.
* gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-release.c:
Ditto.
* gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-seq-cst.c:
Ditto.
Signed-off-by: Patrick O'Neill
---
gcc/test
aamo-rvwmo-amo-add-int.c: New test.
* gcc.target/riscv/amo/zaamo-ztso-amo-add-int.c: New test.
* gcc.target/riscv/amo/zalrsc-rvwmo-amo-add-int.c: New test.
* gcc.target/riscv/amo/zalrsc-ztso-amo-add-int.c: New test.
Signed-off-by: Patrick O'Neill
---
.../gcc.target/ri
/riscv/amo/amo-table-ztso-subword-amo-add-5.c: Move to...
* gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-seq-cst.c:
...here.
Signed-off-by: Patrick O'Neill
---
.../riscv/amo/{amo-table-a-6-load-2.c => a-rvwmo-load-acquire.c} | 0
.../riscv/amo/{amo-table-a-6-load-1
This is another round of AMO testcase cleanup. Consolidates a lot of testcases
and unifies the testcase names.
Patrick O'Neill (3):
RISC-V: Rename amo testcases
RISC-V: Consolidate amo testcase variants
RISC-V: Update testcase comments to point to PSABI rather than Table
Committed.
Patrick
On 6/24/24 12:06, Patrick O'Neill wrote:
This introduces testsuite support infra for removing extensions.
Since z* extensions don't have ordering requirements the logic for
adding/removing those extensions has also been consolidated.
This fixes RVWMO compile
code.
Signed-off-by: Patrick O'Neill
---
Tested using rv64gcv_ztso/rv64id but relying on precommit to run the targets
there.
Beyond testing Ztso/Zalrsc this is also helpful for the Zabha patch I'm
working on. We can continue to test the atomic subword emulation
routines without spe
code.
Signed-off-by: Patrick O'Neill
---
Tested using rv64gcv_ztso/rv64id but relying on precommit to run the targets
there.
Beyond testing Ztso/Zalrsc this is also helpful for the Zabha patch I'm
working on. We can continue to test the atomic subword emulation
routines without spe
Hi Feng,
Pre-commit has flagged a build-failure for patch 2/3:
https://github.com/ewlu/gcc-precommit-ci/issues/1786#issuecomment-2181962244
When applied to 9a76db24e04 i386: Allow all register_operand SUBREGs in
x86_ternlog_idx.
Re-confirmed locally with 5320bcbd342 xstormy16: Fix
xs_hi_nonm
g.exp: Add dg-remove-options.
* lib/target-supports.exp: Add dg-remove-options and consolidate z*
extension add/remove-option code.
Signed-off-by: Patrick O'Neill
---
Tested using rv64gcv_ztso/rv64id but relying on precommit to run the targets
there.
Beyond testing Ztso/Zalr
: Add dg-remove-options.
* lib/target-supports.exp: Add dg-remove-options and consolidate z*
extension add/remove-option code.
Signed-off-by: Patrick O'Neill
---
Tested using rv64gcv_ztso but relying on precommit to run the targets
there.
Beyond testing Ztso/Zalrsc this is al
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