:44 PM Jin Ma wrote:
> Hi, Monk Chiang
>
> I noticed that at -O0, static functions are emitting lpad instructions,
> whereas
> they do not at -O2. I'm not sure if this is expected behavior.
>
> Upon further investigation, I found that c_node->only_called_directly_p(
Hi Robin,
Thanks for your comment. I think your point is correct, especially the part
about SEWmin.
I will revise this patch again.
On Wed, Feb 5, 2025 at 4:18 PM Robin Dapp wrote:
> > Hi Robin,
> > Sorry, I should have simplified the problem by presenting it in terms of
> > Zve32x, because Zve3
Hi Robin,
Sorry, I should have simplified the problem by presenting it in terms of
Zve32x, because Zve32f implies Zve32x.
As the specification states, the requirement is to support LMUL ≥ SEW/ELEN.
Regarding the implementation,
I followed this rule to fix the problem.
In this link: https://godbolt
According to Section 3.4.2, Vector Register Grouping, in the RISC-V
Vector Specification, the rule for LMUL is LMUL >= SEW/ELEN
gcc/ChangeLog:
* config/riscv/riscv-v.cc: Add restrict for insert LMUL.
config/riscv/riscv-vector-builtins-types.def:
Use RVV_REQUIRE_ELEN_64 to c
According to Section 3.4.2, Vector Register Grouping, in the RISC-V
Vector Specification, the rule for LMUL is LMUL >= SEW/ELEN
---
gcc/config/riscv/riscv-v.cc | 8 +-
gcc/config/riscv/riscv-vector-switch.def | 84 ++---
.../gcc.target/riscv/rvv/autovec/pr111391-2
Thanks, I will fix it.
> Mark Wielaard 於 2025年1月17日 晚上10:32 寫道：
>
> Hi Monk,
>
>> On Fri, Nov 15, 2024 at 06:53:09PM +0800, Monk Chiang wrote:
>> gcc/ChangeLog:
>>* gcc/config/riscv/riscv.cc
>>(riscv_file_end_indicate_exec_stack): Add .note.gn
gcc/ChangeLog:
* gcc/config/riscv/riscv.cc
(is_zicfilp_p): New function.
(is_zicfiss_p): New function.
* gcc/config/riscv/riscv-zicfilp.cc: Update.
* gcc/config/riscv/riscv.h: Update.
* gcc/config/riscv/riscv.md: Update.
gcc/testsuite/ChangeLog:
This patch only support landing pad value is 0.
The next version will implement function signature based labeling
scheme.
RISC-V CFI SPEC: https://github.com/riscv/riscv-cfi
gcc/ChangeLog:
* gcc/common/config/riscv/riscv-common.cc: Add ZICFILP ISA
string.
* gcc/config.gc
gcc/ChangeLog:
* gcc/config/riscv/riscv.cc
(riscv_file_end_indicate_exec_stack): Add .note.gnu.property.
* gcc/config/riscv/linux.h (TARGET_ASM_FILE_END): Define.
libgcc/ChangeLog:
* libgcc/config/riscv/crti.S: Add lpad instructions.
* libgcc/config/riscv/cr
This patch is implemented according to the RISC-V CFI specification.
It supports the generation of shadow stack instructions in the prologue,
epilogue, non-local gotos, and unwinding.
RISC-V CFI SPEC: https://github.com/riscv/riscv-cfi
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc:
cGary wrote:
>
>> On Mon, Jan 13, 2025 at 1:02 AM Monk Chiang
>> wrote:
>>
>>>
>>> * gcc/config/riscv/riscv.cc
>>> (riscv_file_end_indicate_exec_stack): Add .note.gnu.property.
>>>
>>> * libgcc/config/
This patch only support landing pad value is 0.
The next version will implement function signature based labeling
scheme.
RISC-V CFI SPEC: https://github.com/riscv/riscv-cfi
gcc/ChangeLog:
* gcc/common/config/riscv/riscv-common.cc: Add ZICFILP ISA
string.
* gcc/config.gc
gcc/ChangeLog:
* gcc/config/riscv/riscv.cc
(is_zicfilp_p): New function.
(is_zicfiss_p): New function.
* gcc/config/riscv/riscv-zicfilp.cc: Update.
* gcc/config/riscv/riscv.h: Update.
* gcc/config/riscv/riscv.md: Update.
gcc/testsuite/ChangeLog:
gcc/ChangeLog:
* gcc/config/riscv/riscv.cc
(riscv_file_end_indicate_exec_stack): Add .note.gnu.property.
* gcc/config/riscv/linux.h (TARGET_ASM_FILE_END): Define.
libgcc/ChangeLog:
* libgcc/config/riscv/crti.S: Add lpad instructions.
* libgcc/config/riscv/cr
This patch is implemented according to the RISC-V CFI specification.
It supports the generation of shadow stack instructions in the prologue,
epilogue, non-local gotos, and unwinding.
RISC-V CFI SPEC: https://github.com/riscv/riscv-cfi
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc:
gcc/ChangeLog:
* gcc/config/riscv/riscv.cc
(is_zicfilp_p): New function.
(is_zicfiss_p): New function.
* gcc/config/riscv/riscv-zicfilp.cc: Update.
* gcc/config/riscv/riscv.h: Update.
* gcc/config/riscv/riscv.md: Update.
gcc/testsuite/ChangeLog:
Update gcc/testsuite/c-c++-common/fcf-protection-[1-7].c.
On Wed, Jan 15, 2025 at 3:54 PM Monk Chiang wrote:
> gcc/ChangeLog:
> * gcc/config/riscv/riscv.cc
> (is_zicfilp_p): New function.
> (is_zicfiss_p): New function.
> * gcc/config/riscv/r
gcc/ChangeLog:
* gcc/config/riscv/riscv.cc
(riscv_file_end_indicate_exec_stack): Add .note.gnu.property.
* gcc/config/riscv/linux.h (TARGET_ASM_FILE_END): Define.
libgcc/ChangeLog:
* libgcc/config/riscv/crti.S: Add lpad instructions.
* libgcc/config/riscv/cr
This patch is implemented according to the RISC-V CFI specification.
It supports the generation of shadow stack instructions in the prologue,
epilogue, non-local gotos, and unwinding.
RISC-V CFI SPEC: https://github.com/riscv/riscv-cfi
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc:
This patch only support landing pad value is 1.
The next version will implement function signature based labeling
scheme.
RISC-V CFI SPEC: https://github.com/riscv/riscv-cfi
gcc/ChangeLog:
* gcc/common/config/riscv/riscv-common.cc: Add ZICFILP ISA
string.
* gcc/config.gc
gcc/ChangeLog:
* gcc/config/riscv/riscv.cc
(riscv_file_end_indicate_exec_stack): Add .note.gnu.property.
* gcc/config/riscv/linux.h (TARGET_ASM_FILE_END): Define.
libgcc/ChangeLog:
* libgcc/config/riscv/crti.S: Add lpad instructions.
* libgcc/config/riscv/cr
This patch is implemented according to the RISC-V CFI specification.
It supports the generation of shadow stack instructions in the prologue,
epilogue, non-local gotos, and unwinding.
RISC-V CFI SPEC: https://github.com/riscv/riscv-cfi
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc:
gcc/ChangeLog:
* gcc/config/riscv/riscv.cc
(is_zicfilp_p): New function.
(is_zicfiss_p): New function.
* gcc/config/riscv/riscv-zicfilp.cc: Update.
* gcc/config/riscv/riscv.h: Update.
* gcc/config/riscv/riscv.md: Update.
gcc/testsuite/ChangeLog:
This patch only support landing pad value is 1.
The next version will implement function signature based labeling
scheme.
RISC-V CFI SPEC: https://github.com/riscv/riscv-cfi
gcc/ChangeLog:
* gcc/common/config/riscv/riscv-common.cc: Add ZICFILP ISA
string.
* gcc/config.gc
gcc/ChangeLog:
* gcc/config/riscv/riscv.cc
(riscv_file_end_indicate_exec_stack): Add .note.gnu.property.
* gcc/config/riscv/linux.h (TARGET_ASM_FILE_END): Define.
libgcc/ChangeLog:
* libgcc/config/riscv/crti.S: Add lpad instructions.
* libgcc/config/riscv/cr
gcc/ChangeLog:
* gcc/config/riscv/riscv.cc
(is_zicfilp_p): New function.
(is_zicfiss_p): New function.
* gcc/config/riscv/riscv-zicfilp.cc: Update.
* gcc/config/riscv/riscv.h: Update.
* gcc/config/riscv/riscv.md: Update.
---
gcc/config/riscv/risc
This patch only support landing pad value is 1.
The next version will implement function signature based labeling
scheme.
RISC-V CFI SPEC: https://github.com/riscv/riscv-cfi
gcc/ChangeLog:
* gcc/common/config/riscv/riscv-common.cc: Add ZICFILP ISA
string.
* gcc/config.gc
This patch is implemented according to the RISC-V CFI specification.
It supports the generation of shadow stack instructions in the prologue,
epilogue, non-local gotos, and unwinding.
RISC-V CFI SPEC: https://github.com/riscv/riscv-cfi
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc:
The patch add the Zihintntl instructions in the prefetch pattern.
Zicbop has prefetch instructions. Zihintntl has NTL instructions.
Insert NTL instructions before prefetch instruction, if target
has Zihintntl extension.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_print_operand): Add 'L'
The patch add the Zihintntl instructions in the prefetch pattern.
Zicbop has prefetch instructions. Zihintntl has NTL instructions.
Insert NTL instructions before prefetch instruction, if target
has Zihintntl extension.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_print_operand): Add 'L'
Dehao Chen
Fabien Ch??ne
+Monk Chiang
Cl??ment Chigot
Harshit Chopra
Tamar
Hi Edwin,
I think just replace to:
/* { dg-options "-O2 -finstrument-functions -mabi=lp64d -march=rv64gc
-mtune=sifive-p600-series" } */
On Thu, Feb 15, 2024 at 7:43 PM Robin Dapp wrote:
> > Ah oops I glanced over the /* { dg-do compile } */part. It should be
> > fine to add '-march=rv64gc' inst
Hi Jeff,
I don't have permission to commit, can you push it for me? If you look good
to you.
> Jeff Law 於 2024年2月14日 凌晨12:03 寫道：
>
>
>
>> On 2/4/24 20:20, Monk Chiang wrote:
>> gcc/ChangeLog:
>> PR target/113742
>> * config/riscv/
Hi Jeff,
I don't have permission to commit, can you push it for me? If you look good
to you.
> Jeff Law 於 2024年2月14日 凌晨12:03 寫道：
>
>
>
>> On 2/4/24 20:20, Monk Chiang wrote:
>> gcc/ChangeLog:
>>PR target/113742
>>* config/riscv/
Yes, this test needs "--enable-checking=rtl" build.
On Mon, Feb 5, 2024 at 11:28 AM Jeff Law wrote:
>
>
> On 2/4/24 20:20, Monk Chiang wrote:
> > gcc/ChangeLog:
> >
> > PR target/113742
> > * config/riscv/riscv.cc (riscv_macro_fusion_pai
gcc/ChangeLog:
PR target/113742
* config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Fix
recognizes UNSPEC_AUIPC for RISCV_FUSE_LUI_ADDI.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/pr113742.c: New test.
---
gcc/config/riscv/riscv.cc | 2 +-
gcc/t
gcc/ChangeLog:
* config/riscv/riscv-cores.def: Add sifive-p450, sifive-p670.
* doc/invoke.texi (RISC-V Options): Add sifive-p450,
sifive-p670.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/mcpu-sifive-p450.c: New test.
* gcc.target/riscv/mcpu-sifive-p670.c:
Add sifive p400 series scheduler module. For more information
see https://www.sifive.com/cores/performance-p450-470.
gcc/ChangeLog:
* config/riscv/riscv.md: Include sifive-p400.md.
* config/riscv/sifive-p400.md: New file.
* config/riscv/riscv-cores.def (RISCV_TUNE): Add pa
The RISC-V Profiles specification here:
https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#7-new-isa-extensions
These extensions don't add any new features but
describe existing features. So this patch only adds parsing.
Za64rs: Reservation set size of 64 bytes
Za128rs: Reservation s
The RISC-V Profiles specification here:
https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#7-new-isa-extensions
These extensions don't add any new features but
describe existing features. So this patch only adds parsing.
Za64rs: Reservation set size of 64 bytes
Za128rs: Reservation s
Hi Juzhe,
The vector part is complicated, I will add it last.
On Thu, Feb 1, 2024 at 11:08 AM juzhe.zh...@rivai.ai
wrote:
> Hi, Monk.
>
> This model doesn't include vector. Will you add vector pipeline in the
> followup patches ?
>
> --
> juzhe.zh...@rivai.ai
>
Add sifive p600 series scheduler module. For more information
see https://www.sifive.com/cores/performance-p650-670.
Add sifive-p650, sifive-p670 for mcpu option will come in separate patches.
gcc/ChangeLog:
* config/riscv/riscv.md: Add "fcvt_i2f", "fcvt_f2i" type
attribute, and in
tly committed changes modifying the scheduling reservations. Some
> things may need to be retested with the newly enabled asserts.
>
> Edwin
>
> On 1/31/2024 1:40 AM, Monk Chiang wrote:
> > Add sifive p600 series scheduler module. For more information
> > see https://ww
Add sifive p600 series scheduler module. For more information
see https://www.sifive.com/cores/performance-p650-670.
Add sifive-p650, sifive-p670 for mcpu option will come in separate patches.
gcc/ChangeLog:
* config/riscv/riscv.md: Add "fcvt_i2f", "fcvt_f2i" type
attribute, and in
Since the match.pd transforms (zero_one == 0) ? y : z y,
into ((typeof(y))zero_one * z) y. Add splitters to recongize
this expression to generate SFB instructions.
gcc/ChangeLog:
PR target/113095
* config/riscv/sfb.md: New splitters to rewrite single bit
sign extension as
Thank you for your help. I will update the test case.
I test on the Coremark and have 5% improvement on the SiFive CPU.
On Tue, Jan 23, 2024 at 12:24 PM Jeff Law wrote:
>
>
> On 1/21/24 23:12, Monk Chiang wrote:
> > Since the match.pd transforms (zero_one == 0) ? y : z y,
>
Since the match.pd transforms (zero_one == 0) ? y : z y,
into ((typeof(y))zero_one * z) y. Add splitters to recongize
this expression to generate SFB instructions.
gcc/ChangeLog:
PR target/113095
* config/riscv/sfb.md: New splitters to rewrite single bit
sign extension as
Since the match.pd transforms (zero_one == 0) ? y : z y,
into ((typeof(y))zero_one * z) y. Add splitters to recongize
this expression to generate SFB instructions.
gcc/ChangeLog:
PR target/113095
* config/riscv/sfb.md: New splitters to rewrite single bit
sign extension as
Thanks for your advice!! I agree it should be fixed in the RISC-V backend
when expansion.
On Wed, Jan 17, 2024 at 10:37 PM Jeff Law wrote:
>
>
> On 1/17/24 05:14, Richard Biener wrote:
> > On Wed, 17 Jan 2024, Monk Chiang wrote:
> >
> >> This allows the backend
This allows the backend to generate movcc instructions, if target
machine has movcc pattern.
branchless-cond.c needs to be updated since some target machines have
conditional move instructions, and the experssion will not change to
branchless expression.
gcc/ChangeLog:
PR target/113095
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_print_operand):
Add 'N' for print a non-temporal locality hints instruction.
* config/riscv/riscv.md (prefetch):
Add NTLH instruction for prefetch.r and prefetch.w.
gcc/testsuite/ChangeLog:
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc:
(riscv_implied_info): Add zihintntl item.
(riscv_ext_version_table): Ditto.
(riscv_ext_flag_table): Ditto.
* config/riscv/riscv-opts.h (MASK_ZIHINTNTL): New macro.
(TAR
Avoid VL_REGS, VTYPE_REGS join register allocation.
gcc/ChangeLog:
* config/riscv/riscv.h: Remove VL_REGS, VTYPE_REGS class.
* config/riscv/riscv.cc: Ditto.
---
gcc/config/riscv/riscv.cc | 8 +---
gcc/config/riscv/riscv.h | 6 --
2 files changed, 1 insertion(+), 13 delet
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc (riscv_ext_version_table):
Add svinval and svnapot extension.
(riscv_ext_flag_table): Ditto.
* config/riscv/riscv-opts.h (MASK_SVINVAL): New.
(MASK_SVNAPOT): Ditto.
(TARGET_SVINVAL): Ditto.
gcc/ChangeLog:
* config/riscv/riscv.md: Add atomic type attribute.
* config/riscv/sync.md: Add atomic type for atomic instructions.
---
gcc/config/riscv/riscv.md | 2 +-
gcc/config/riscv/sync.md | 15 ++-
2 files changed, 11 insertions(+), 6 deletions(-)
diff --git
- When expanding the call pattern, choose t1 register be a jump register.
Epilogue also uses a t1 register to adjust Stack point. The call pattern
and epilogue will initial t1 twice, if both are generated in the same
function. The call pattern will emit 'la t1,symbol' and 'jalr
t1'in
- When expanding the call pattern, choose t1 register be a jump register.
Epilogue also uses a t1 register to adjust Stack point. The call pattern
and epilogue will initial t1 twice, if both are generated in the same
function. The call pattern will emit 'la t1,symbol' and 'jalr
t1'in
2013/12/13 Chung-Ju Wu :
> 2013/12/11 Monk Chiang :
>> Hi,
>>
>> Recently I used --target=nds32be-elf to configure nds32 gcc,
>> it seems that the big endian is not set as default.
>>
> [...]
>>
>> The following is the patch to fix this issue. Teste
OV)
Index: ChangeLog
===
--- ChangeLog (revision 205880)
+++ ChangeLog (working copy)
@@ -1,3 +1,8 @@
+2013-12-11 Monk Chiang
+
+ * common/config/nds32/nds32-common.c (TARGET_DEFAULT_TARGET_FLAGS):
+ Redefine.
+
2
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