On Sat, Jun 7, 2025 at 10:05 PM Takayuki 'January June' Suwa
wrote:
>
> By using the previously unused CEIL|FLOOR.S floating-point coprocessor
> instructions. In addition, two instruction operand format codes are added
> to output the scale value as assembler source.
>
> /* example */
>
On Thu, Jun 5, 2025 at 7:20 PM Takayuki 'January June' Suwa
wrote:
>
> On 2025/06/06 8:55, Max Filippov wrote:
>
> > On Thu, Jun 05, 2025 at 09:19:19PM +0900, Takayuki 'January June' Suwa
> > wrote:
> >> On 2025/06/05 5:09, Max Filippov wr
On Thu, Jun 05, 2025 at 09:19:19PM +0900, Takayuki 'January June' Suwa wrote:
> On 2025/06/05 5:09, Max Filippov wrote:
> > On Tue, Jun 3, 2025 at 7:44 AM Takayuki 'January June' Suwa
> > wrote:
> > >
> > > By using the previously unused
Hi Suwa-san,
On Tue, Jun 3, 2025 at 7:44 AM Takayuki 'January June' Suwa
wrote:
>
> By using the previously unused CEIL|FLOOR|ROUND.S floating-point coprocessor
> instructions. In addition, two instruction operand format codes are added
> to output the scale value as assembler source.
>
> /
On Mon, May 26, 2025 at 11:59 PM Takayuki 'January June' Suwa
wrote:
>
> As one of the last steps in removing old reload.
>
> gcc/ChangeLog:
>
> * gcc/config/xtensa/xtensa.cc
> Remove include of reload.h.
> ---
> gcc/config/xtensa/xtensa.cc | 1 -
> 1 file changed, 1 deletion(-)
Add new function check_effective_target_xtensa_atomic and use it in the
check_effective_target_sync_int_long and
check_effective_target_sync_char_short.
gcc/testsuite/ChangeLog:
* lib/target-supports.exp
(check_effective_target_xtensa_atomic): New function.
(check_effectiv
On Sat, May 10, 2025 at 12:51 PM Takayuki 'January June' Suwa
wrote:
>
> Until now (presumably after transition to LRA), hard registers storing
> function arguments or return values were spilling undesirably when
> TARGET_HARD_FLOAT is enabled.
>
> /* example */
> float test0(float a, fl
Hi Suwa-san,
On Thu, Apr 24, 2025 at 12:07 AM Takayuki 'January June' Suwa
wrote:
>
> Recent gcc versions tend to convert constants for which
> TARGET_LEGITIMATE_CONSTANT_P returns false into references to literal pool
> entries during the RTL instruction combination pass for pattern matching.
>
On Sat, Nov 9, 2024 at 10:39 PM Takayuki 'January June' Suwa
wrote:
>
> The second source register of insn "*extzvsi-1bit_addsubx" cannot be the
> same as the destination register, because that register will be overwritten
> with an intermediate value after insn splitting.
>
> /* example #1 *
On Tue, Oct 22, 2024 at 7:31 PM Takayuki 'January June' Suwa
wrote:
>
> In commit bc5a9dab55d13f888a3cdd150c8cf5c2244f35e0 ("gcc: xtensa: reorder
> movsi_internal patterns for better code generation during LRA"), the
> instruction order in "movsi_internal" MD definition was changed to make LRA
>
On Tue, Jul 23, 2024 at 5:52 PM Takayuki 'January June' Suwa
wrote:
>
> According to the implemented pipeline model, this cost can be assumed to be
> 1 clock cycle.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.cc (xtensa_insn_cost):
> Add a case statement for TYPE_FARITH.
Regtest
On Tue, Jul 23, 2024 at 5:52 PM Takayuki 'January June' Suwa
wrote:
>
> We would like to implement the following to store a single-precision FP
> constant in a hardware FP register:
>
> - Load the bit-exact integer image of the pooled single-precision FP
>constant into an address (integer) reg
On Fri, Jul 19, 2024 at 1:35 PM Takayuki 'January June' Suwa
wrote:
>
> It is not wrong but also not optimal to specify that sibcalls require
> register A0 in RTX generation pass, by misleading DFA into thinking it
> is being used in function body.
> It would be better to specify it in pro_and_epi
On Sun, Jul 14, 2024 at 4:05 AM Takayuki 'January June' Suwa
wrote:
>
> They were once mistakenly removed with
> "xtensa: Remove old broken tweak for leaf function", but caused unwanted
> register spills.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.h (LEAF_REGISTERS, LEAF_REG_REMAP):
>
On Sun, Jul 14, 2024 at 4:05 AM Takayuki 'January June' Suwa
wrote:
>
> [U]FLOAT.S machine instruction in Xtensa ISA, which converts an integer to
> a hardware single-precision FP register, has the ability to divide the
> result by power of two (0 to 15th).
>
> Similarly, [U]TRUNC.S instruction, w
On Sun, Jul 14, 2024 at 4:05 AM Takayuki 'January June' Suwa
wrote:
>
> No functional changes.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.cc
> (gen_int_relational, gen_float_relational): Replace tempvar-based
> value-swapping codes with std::swap.
> * config/xten
gcc/
* config/xtensa/xtensa.cc (xtensa_option_override_after_change):
New function.
(TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE): Define as
xtensa_option_override_after_change.
(xtensa_option_override): Call
xtensa_option_override_after_change.
---
gcc/con
On Mon, Jul 15, 2024 at 10:21:18AM -0700, Ian Lance Taylor wrote:
> Can you see whether this patch works for FDPIC support? This is based
> on your patch but has various changes. Thanks.
Yes, it is working.
--
Thanks.
-- Max
On Wed, Jul 10, 2024 at 12:49 PM Ian Lance Taylor wrote:
> On Sun, May 26, 2024 at 11:51 PM Max Filippov wrote:
> > diff --git a/libbacktrace/internal.h b/libbacktrace/internal.h
> > index 4fa0af8cb6c9..456911166026 100644
> > --- a/libbacktrace/internal.h
> > ++
On Tue, Jun 18, 2024 at 10:00 PM Takayuki 'January June' Suwa
wrote:
>
> This patch makes avoid inserting a MEMW instruction before a load/store
> nstruction with volatile memory reference if there is already a MEMW
> immediately before it.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.cc
On Tue, Jun 18, 2024 at 7:56 PM Takayuki 'January June' Suwa
wrote:
>
> The previous constant synthesis logic had some issues that were non-fatal
> but worth considering:
>
> - It didn't work with DFmode literals, because those were cast to SImode
>rather SFmode when splitting into two natural
Hi Suwa-san,
On Mon, Jun 17, 2024 at 04:17:15PM +0900, Takayuki 'January June' Suwa wrote:
> The previous constant synthesis logic had some issues that were non-fatal
> but worth considering:
>
> - It didn't work with DFmode literals, because those were cast to SImode
> rather SFmode when split
On Sun, May 26, 2024 at 11:50 PM Max Filippov wrote:
>
> Instead of a single base address FDPIC ELF files use load map: a
> structure with an array of mappings for individual segments. Change
> libbacktrace functions and structures to support that.
Ping?
> libbacktrace/
On Fri, May 31, 2024 at 07:24:48PM +0900, Takayuki 'January June' Suwa wrote:
> No functional changes.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa-protos.h (xtensa_expand_call):
> Add the third argument as boolean.
> (xtensa_expand_epilogue): Remove the first argument.
>
On Fri, May 31, 2024 at 07:23:13PM +0900, Takayuki 'January June' Suwa wrote:
> No functional changes.
>
> gcc/ChangeLog:
>
> * config/xtensa/predicates.md
> (subreg_HQI_lowpart_operator, xtensa_sminmax_operator):
> New operator predicates.
> * config/xtensa/xtensa-protos.
On Thu, May 30, 2024 at 6:33 AM Takayuki 'January June' Suwa
wrote:
>
> In commit ad89d820bf, an "epilogue_done" member was added to the
> machine_function structure, but it is sufficient to use the existing
> "epilogue_completed" global variable.
>
> gcc/ChangeLog:
>
> * config/xtensa/xte
On Thu, May 30, 2024 at 6:33 AM Takayuki 'January June' Suwa
wrote:
>
> Instead of comparing directly, this patch replaces as much as possible with
> macros that determine RTX code such as REG_P(), SUBREG_P() or MEM_P(), etc.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.cc (xtensa_valid_m
On Mon, May 27, 2024 at 12:01 AM Rainer Orth
wrote:
> > This is an RFC series that adds FDPIC ELF target support to
> > libbacktrace.
> >
> > While debugging this I've noticed that there's no unwinding info for the
> > libstdc++ version of libbacktrace, which made backtraces empty for me,
> > both
bc.
Adding -funwind-tables to the libstdc++ version of libbacktrace fixed
that. Which makes me wonder how it works for other architectures?
Max Filippov (2):
libbacktrace: add FDPIC support
libstdc++-v3/src/libbacktrace: add -funwind-tables
libbacktrace/dwarf.c
Instead of a single base address FDPIC ELF files use load map: a
structure with an array of mappings for individual segments. Change
libbacktrace functions and structures to support that.
libbacktrace/
PR libbacktrace/114941
* dwarf.c: Include or if available.
(struct d
libstdc++-v3/
* src/libbacktrace/Makefile.am (AM_CFLAGS, AM_CXXFLAGS): Add
-funwind-tables
* src/libbacktrace/Makefile.in: Regenerate.
---
libstdc++-v3/src/libbacktrace/Makefile.am | 4 ++--
libstdc++-v3/src/libbacktrace/Makefile.in | 4 ++--
2 files changed, 4 insertions(
On Fri, Mar 22, 2024 at 1:15 PM Max Filippov wrote:
>
> libgcc/
> * unwind-arm-common.inc (__gnu_personality_sigframe_fdpic): Cast
> last argument of _Unwind_VRS_Set to void *.
> ---
> libgcc/unwind-arm-common.inc | 2 +-
> 1 file changed, 1 insertion(+),
On Thu, Mar 21, 2024 at 4:36 PM Takayuki 'January June' Suwa
wrote:
>
> int test(int a) {
>return a * 4 + 3;
> }
>
> In the example above, since Xtensa has instructions to add register value
> scaled by 2, 4 or 8 (and corresponding define_insns), we would expect them
> to be used but not,
libgcc/
* unwind-arm-common.inc (__gnu_personality_sigframe_fdpic): Cast
last argument of _Unwind_VRS_Set to void *.
---
libgcc/unwind-arm-common.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/libgcc/unwind-arm-common.inc b/libgcc/unwind-arm-common.inc
inde
After switching to LRA xtensa backend generates the following code for
saving/loading registers:
movi a9, 0x190
add a9, a9, sp
s32i.n a3, a9, 0
instead of the shorter and more efficient
s32i a3, a9, 0x190
E.g. the following code can be used to reproduce it:
i
On Sat, Feb 3, 2024 at 6:19 AM Takayuki 'January June' Suwa
wrote:
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.md (*eqne_zero_masked_bits):
> Add missing ":SI" to the match_operator.
> ---
> gcc/config/xtensa/xtensa.md | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reg
On Sun, Feb 4, 2024 at 2:20 AM Takayuki 'January June' Suwa
wrote:
>
> After LRA transition, HImode constants that don't fit into signed 12 bits
> are no longer subject to constant synthesis:
>
> /* example */
> void test(void) {
> short foo = 32767;
> __asm__ ("" :: "r"(foo));
Hi Suwa-san,
On Sat, Feb 3, 2024 at 6:20 AM Takayuki 'January June' Suwa
wrote:
> After LRA transition, HImode constants that don't fit into signed 12 bits
> are no longer subject to constant synthesis:
with this change I get multiple ICEs during libgomp, libgfortran and
libstdc++ builds, e.g.:
From: Takayuki 'January June' Suwa
gcc/ChangeLog:
* config/xtensa/constraints.md (R, T, U):
Change define_constraint to define_memory_constraint.
* config/xtensa/predicates.md (move_operand): Don't check that a
constant pool operand size is a multiple of UNITS_PER
From: Takayuki 'January June' Suwa
gcc/ChangeLog:
* config/xtensa/constraints.md (R, T, U):
Change define_constraint to define_memory_constraint.
* config/xtensa/predicates.md (move_operand): Don't check that a
constant pool operand size is a multiple of UNITS_PER
Hi Suwa-san,
I've finally processed the new issues introduced by this change.
On Wed, May 10, 2023 at 2:10 AM Max Filippov wrote:
> On Mon, May 8, 2023 at 6:38 AM Takayuki 'January June' Suwa
> wrote:
> >
> > gcc/ChangeLog:
> >
> >
gcc/
* config/xtensa/xtensa.h (TARGET_SALT): Change HW version from
26 (which corresponds to RF-2014.0) to 27 (which
corresponds to RG-2015.0, the release where salt/saltu opcodes
were introduced).
---
gcc/config/xtensa/xtensa.h | 2 +-
1 file changed, 1 ins
gcc/
* config/xtensa/predicates.md (xtensa_cstoresi_operator): Add
unsigned comparisons.
* config/xtensa/xtensa.cc (xtensa_expand_scc): Add code
generation of salt/saltu instructions.
* config/xtensa/xtensa.h (TARGET_SALT): New macro.
* config/xtensa/
On Fri, Sep 8, 2023 at 1:49 AM Takayuki 'January June' Suwa
wrote:
>
> An idiomatic implementation of boolean evaluation of whether a register is
> zero or not in Xtensa is to assign 0 and 1 to the temporary and destination,
> and then issue the MOV[EQ/NE]Z machine instruction
> (See 8.3.2 Instruc
gcc/
* config/xtensa/predicates.md (xtensa_cstoresi_operator): Add
unsigned comparisons.
* config/xtensa/xtensa.cc (xtensa_expand_scc): Add code
generation of salt/saltu instructions.
* config/xtensa/xtensa.h (TARGET_SALT): New macro.
* gcc/config/xte
On Tue, Sep 5, 2023 at 2:29 AM Takayuki 'January June' Suwa
wrote:
>
> This patch optimizes the boolean evaluation for equality to 0 in SImode
> using the MINU (Minimum Value Unsigned) machine instruction available
> when TARGET_MINMAX is configured, for example, (x != 0) to MINU(x, 1)
> and (x ==
On Tue, Sep 5, 2023 at 9:24 PM Takayuki 'January June' Suwa
wrote:
> On 2023/09/06 8:01, Max Filippov wrote:
> > On Tue, Sep 5, 2023 at 2:29 AM Takayuki 'January June' Suwa
> > wrote:
> >> ;; after (prereq. TARGET_MINMAX)
> >> test0:
&
Hi Suwa-san,
On Tue, Sep 5, 2023 at 2:29 AM Takayuki 'January June' Suwa
wrote:
>
> This patch optimizes the boolean evaluation for equality to 0 in SImode
> using the MINU (Minimum Value Unsigned) machine instruction available
> when TARGET_MINMAX is configured, for example, (x != 0) to MINU(x,
On Thu, Jul 20, 2023 at 10:54 AM Alexey Lapshin
wrote:
> Please consider to review another two pathes then.
> This would be nice to have it in upstream
Sure, it's going to take some time though as I need to take a good look,
and maybe I'll come back with some change proposals.
--
Thanks.
-- Max
On Thu, Jul 20, 2023 at 10:45 AM Alexey Lapshin
wrote:
>
> On Thu, 2023-07-20 at 08:25 -0700, Max Filippov wrote:
> > But it defines them with their respective values.
> > Just notice that it adds two leading underscores in front of the names.
>
> Why builtin macros
On Thu, Jul 20, 2023 at 9:10 AM Alexey Lapshin
wrote:
> I see now, thanks for the explanation, I will try to rebuild toolchain
> without this particular patch.
> BTW, what do you thing about placing config from newlib overlay to dynconfig?
That's the right thing to do. Bonus points for keeping b
On Thu, Jul 20, 2023 at 8:12 AM Alexey Lapshin
wrote:
>
> Oops, missed this loop while implementing...
>
> I had a problem with building esp chips multilib until added my changes.
>
> This loop looks like just defines a macro without value.
But it defines them with their respective values.
Just n
On Thu, Jul 20, 2023 at 7:37 AM Alexey Lapshin
wrote:
>
> gcc/
> * config/xtensa/xtensa.h (XCHAL_HAVE_BE, XCHAL_HAVE_DENSITY,
> XCHAL_HAVE_CONST16, XCHAL_HAVE_ABS, XCHAL_HAVE_ADDX,
> XCHAL_HAVE_L32R, XSHAL_USE_ABSOLUTE_LITERALS,
> XSHAL_HAVE_TEXT_SECTION_LITER
On Mon, Jul 3, 2023 at 5:57 PM Takayuki 'January June' Suwa
wrote:
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.cc (machine_function, xtensa_expand_prologue):
> Change to use HARD_REG_BIT and its macros.
> * config/xtensa/xtensa.md
> (peephole2: regmove elimination
On Sat, Jul 1, 2023 at 10:21 AM Takayuki 'January June' Suwa
wrote:
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.md (*eqne_INT_MIN):
> Add missing ":SI" to the match_operator.
> ---
> gcc/config/xtensa/xtensa.md | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Regtested f
On Sat, Jul 1, 2023 at 10:21 AM Takayuki 'January June' Suwa
wrote:
>
> Because both smin and smax requiring TARGET_MINMAX are essential to the
> RTL representation.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.cc (xtensa_match_CLAMPS_imms_p):
> Simplify.
> * config/xtensa
On Sun, Jun 18, 2023 at 12:10 AM Takayuki 'January June' Suwa
wrote:
>
> This patch adds a new 2-instructions constant synthesis pattern:
>
> - A non-negative square value that root can fit into a signed 12-bit:
> => "MOVI(.N) Ax, simm12" + "MULL Ax, Ax, Ax"
>
> Due to the execution cost of t
On Sun, Jun 18, 2023 at 12:10 AM Takayuki 'January June' Suwa
wrote:
>
> It used to always return a constant 4, which is same as the default
> behavior, but doesn't take into account the effects of secondary
> reloads.
>
> Therefore, the implementation of this target hook is removed.
>
> gcc/Chang
On Mon, Jun 5, 2023 at 8:15 AM Max Filippov wrote:
>
> Hi Suwa-san,
>
> On Mon, Jun 5, 2023 at 2:37 AM Takayuki 'January June' Suwa
> wrote:
> >
> > This patch optimizes the boolean evaluation of EQ/NE against zero
> > by adding two insn_and_split patte
Hi Suwa-san,
On Mon, Jun 5, 2023 at 2:37 AM Takayuki 'January June' Suwa
wrote:
>
> This patch optimizes the boolean evaluation of EQ/NE against zero
> by adding two insn_and_split patterns similar to SImode conditional
> store:
>
> "eq_zero":
> op0 = (op1 == 0) ? 1 : 0;
> op0 = c
On Sat, Jun 3, 2023 at 3:52 PM Takayuki 'January June' Suwa
wrote:
>
> This patch optimizes both the boolean evaluation of and the branching of
> EQ/NE against INT_MIN (-2147483648), by taking advantage of the specifi-
> cation the ABS machine instruction on Xtensa returns INT_MIN iff INT_MIN,
> o
Hi Suwa-san,
On Sat, Jun 3, 2023 at 2:55 AM Takayuki 'January June' Suwa
wrote:
>
> This patch optimizes the boolean evaluation of EQ/NE against zero
> by adding two insn_and_split patterns similar to SImode conditional
> store:
>
> "eq_zero":
> op0 = (op1 == 0) ? 1 : 0;
> op0 = c
On Wed, May 31, 2023 at 11:01 PM Takayuki 'January June' Suwa
wrote:
> More optimized than the default RTL generation.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.md (adddi3, subdi3):
> New RTL generation patterns implemented according to the instruc-
> tion idioms descri
On Wed, May 31, 2023 at 11:01 PM Takayuki 'January June' Suwa
wrote:
> More optimized than the default RTL generation.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.md (adddi3, subdi3):
> New RTL generation patterns implemented according to the instruc-
> tion idioms descri
On Tue, May 30, 2023 at 2:27 AM Takayuki 'January June' Suwa
wrote:
>
> The insn "*shlrd_reg" shifts two registers with a funnel shifter by the
> third register to get a single word result:
>
> reg0 = (reg1 SHIFT_OP0 reg3) BIT_JOIN_OP (reg2 SHIFT_OP1 (32 - reg3))
>
> where the funnel left shift
On Tue, May 30, 2023 at 2:50 AM Takayuki 'January June' Suwa
wrote:
>
> Resubmitting the correct one due to a mistake in merging order of fixes.
> ---
> More optimized than the default RTL generation.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.md (adddi3, subdi3):
> New RTL gene
Hi Suwa-san,
On Tue, May 30, 2023 at 2:51 AM Takayuki 'January June' Suwa
wrote:
>
> Resubmitting the correct one due to a mistake in merging order of fixes.
> ---
> This patch introduces more optimized implementations for the 6 cstoresi4
> insn comparison methods (eq/ne/lt/le/gt/ge, however, req
On Thu, May 25, 2023 at 8:13 AM Takayuki 'January June' Suwa
wrote:
>
> In order to reject voodoo estimation logic with lots of magic numbers,
> this patch revises the code to measure the costs of the three memset
> methods based on the actual emission size of the insn sequence
> corresponding to
On Thu, May 25, 2023 at 8:13 AM Takayuki 'January June' Suwa
wrote:
>
> This patch makes try to eliminate using temporary pseudo for
> '(minus:SI (const_int) (reg:SI))' if the addition of negative constant
> value can be emitted in a single machine instruction.
>
> /* example */
> int test
On Thu, May 25, 2023 at 8:13 AM Takayuki 'January June' Suwa
wrote:
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.md (*extzvsi-1bit_ashlsi3):
> Retract excessive line folding, and correct the value of
> the "length" insn attribute related to TARGET_DENSITY.
> (*extz
On Mon, May 22, 2023 at 12:06 AM Takayuki 'January June' Suwa
wrote:
>
> By making use of the 'addsub_operator' added in the last patch.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.md (*addsubx): Rename from '*addx',
> and change to also accept '*subx' pattern.
> (*subx):
On Mon, May 22, 2023 at 10:48 PM Takayuki 'January June' Suwa
wrote:
>
> On 2023/05/23 11:27, Max Filippov wrote:
> > Hi Suwa-san,
>
> Hi!
>
> > This change introduces a bunch of test failures on big endian configuration.
> > I believe that's becau
Hi Suwa-san,
On Mon, May 22, 2023 at 12:06 AM Takayuki 'January June' Suwa
wrote:
>
> This patch decreses one machine instruction from "single bit extraction
> with shifting" operation, and tries to eliminate the conditional
> branch if CST2_POW2 doesn't fit into signed 12 bits with the help
> of
Hi Suwa-san,
On Mon, May 8, 2023 at 6:38 AM Takayuki 'January June' Suwa
wrote:
>
> gcc/ChangeLog:
>
> * config/xtensa/constraints.md (R, T, U):
> Change define_constraint to define_memory_constraint.
> * config/xtensa/xtensa.cc
> (xtensa_lra_p, TARGET_LRA_P): Remo
gcc/
* config/xtensa/xtensa-opts.h: New header.
* config/xtensa/xtensa.h (STRICT_ALIGNMENT): Redefine as
xtensa_strict_align.
* config/xtensa/xtensa.cc (xtensa_option_override): When
-m[no-]strict-align is not specified in the command line set
xtensa_
gcc/
* config/xtensa/xtensa-dynconfig.cc (xtensa_get_config_v4): New
function.
include/
* xtensa-dynconfig.h (xtensa_config_v4): New struct.
(XCHAL_DATA_WIDTH, XCHAL_UNALIGNED_LOAD_EXCEPTION)
(XCHAL_UNALIGNED_STORE_EXCEPTION, XCHAL_UNALIGNED_LOAD_HW)
Hi Suwa-san,
On Tue, Mar 7, 2023 at 10:04 PM Takayuki 'January June' Suwa
wrote:
>
> This patch makes LRA well with some exceptions
> (e.g. MI thunk generation due to pretending reload_completed).
>
> gcc/ChangeLog:
>
> * config/xtensa/constraints.md (R, T, U):
> Change define_con
gcc/
* config/xtensa/linux.h (TARGET_ASM_FILE_END): New macro.
libgcc/
* config/xtensa/crti.S: Add .note.GNU-stack section on linux.
* config/xtensa/crtn.S: Likewise.
* config/xtensa/lib1funcs.S: Likewise.
* config/xtensa/lib2funcs.S: Likewise.
---
gcc/conf
On Sun, Mar 12, 2023 at 5:37 PM Takayuki 'January June' Suwa
wrote:
>
> Because GO_IF_LEGITIMATE_ADDRESS was deprecated a long time ago
> (see commit c6c3dba931548987c78719180e30ebc863404b89).
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.h (REG_OK_STRICT, REG_OK_FOR_INDEX_P,
> REG
gcc/
* config/xtensa/xtensa-dynconfig.cc (xtensa_get_config_v4): New
function.
include/
* xtensa-dynconfig.h (xtensa_config_v4): New struct.
(XCHAL_DATA_WIDTH, XCHAL_UNALIGNED_LOAD_EXCEPTION)
(XCHAL_UNALIGNED_STORE_EXCEPTION, XCHAL_UNALIGNED_LOAD_HW)
gcc/
* config/xtensa/xtensa.h (STRICT_ALIGNMENT): Make it 0 when the
hardware supports both unaligned loads and stores.
---
gcc/config/xtensa/xtensa.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/gcc/config/xtensa/xtensa.h b/gcc/config/xtensa/xtensa.h
index
On Sun, Feb 26, 2023 at 9:27 AM Takayuki 'January June' Suwa
wrote:
>
> This patch introduces the use of CLAMPS instruction when the instruction
> is configured.
>
> /* example */
> int test(int a) {
> if (a < -512)
> return -512;
> if (a > 511)
> return 511;
>
gcc/
* config/xtensa/xtensa-dynconfig.cc (xtensa_get_config_v2)
(xtensa_get_config_v3): New functions.
include/
* xtensa-dynconfig.h (xtensa_config_v3): New struct.
(xtensa_get_config_v3): New declaration.
(XCHAL_HAVE_CLAMPS, XCHAL_HAVE_DEPBITS, XCHAL_HAVE_E
On Sun, Feb 26, 2023 at 9:27 AM Takayuki 'January June' Suwa
wrote:
> This patch introduces the use of CLAMPS instruction when the instruction
> is configured.
Testing.
> (Totally off-topic, but do you know anything about the SALT/SALTU
> instructions?
> I see them in the "Core Architecture Ins
gcc/
PR target/108919
* config/xtensa/xtensa-protos.h
(xtensa_prepare_expand_call): Rename to xtensa_expand_call.
* config/xtensa/xtensa.cc (xtensa_prepare_expand_call): Rename
to xtensa_expand_call.
(xtensa_expand_call): Emit the call and add a clob
Hi Suwa-san,
On Sat, Feb 25, 2023 at 3:33 AM Takayuki 'January June' Suwa
wrote:
> On 2023/02/25 19:01, Max Filippov wrote:
> > diff --git a/gcc/config/xtensa/xtensa.cc b/gcc/config/xtensa/xtensa.cc
> > index e52fba082550..babe7f0ebd68 100644
> > --- a/gcc/config
gcc/
PR target/108919
* config/xtensa/xtensa-protos.h
(xtensa_prepare_expand_call): Rename to xtensa_expand_call.
* config/xtensa/xtensa.cc (xtensa_prepare_expand_call): Rename
to xtensa_expand_call.
(xtensa_expand_call): Emit the call and add a clob
gcc/
* config/xtensa/t-xtensa (xtensa-dynconfig.o): Use $(COMPILE)
and $(POSTCOMPILE) instead of manual dependency listing.
* config/xtensa/xtensa-dynconfig.c: Rename to ...
* config/xtensa/xtensa-dynconfig.cc: ... this.
---
gcc/config/xtensa/t-xtensa
gcc/
* config/xtensa/xtensa-dynconfig.cc (config.h, system.h)
(coretypes.h, diagnostic.h, intl.h): Use "..." instead of <...>
for the gcc-internal headers.
---
gcc/config/xtensa/xtensa-dynconfig.cc | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git
On Thu, Feb 23, 2023 at 1:35 AM Max Filippov wrote:
>
> On Wed, Feb 22, 2023 at 7:42 PM Takayuki 'January June' Suwa
> wrote:
> >
> > In commit b2ef02e8cbbaf95fee98be255f697f47193960ec, the sibling call
> > insn included (use (reg:SI A0_REG)) to fix the
On Thu, Feb 16, 2023 at 11:54 PM Takayuki 'January June' Suwa
wrote:
>
> In the case of the CALL0 ABI, values that must be retained before and
> after function calls are placed in the callee-saved registers (A12
> through A15) and referenced later. However, it is often the case that
> the save an
On Fri, Feb 17, 2023 at 8:43 PM Takayuki 'January June' Suwa
wrote:
>
> Register-register move instructions that can be easily seen as
> unnecessary by the human eye may remain in the compiled result.
> For example:
>
> /* example */
> double test(double a, double b) {
> return __builtin_copysig
Hi Jakub,
On Thu, Feb 23, 2023 at 2:34 AM Jakub Jelinek wrote:
> The translation PR complains that these 4 messages from xtensa-dynconfig.c
> are marked in po/gcc.pot as c-format (which doesn't allow %qs) while they
> should be gcc-internal-format.
>
> The problem is in the manual translation of
In commit b2ef02e8cbbaf95fee98be255f697f47193960ec, the sibling call
insn included (use (reg:SI A0_REG)) to fix the problem, which added
a USE chain unconditionally to the data flow of register A0 during
the sibling call.
As a result, df_regs_ever_live_p (A0_REG) returns true, so even if
register
This reverts commit b2ef02e8cbbaf95fee98be255f697f47193960ec.
---
gcc/config/xtensa/xtensa.cc | 2 ++
gcc/config/xtensa/xtensa.md | 20 +++-
2 files changed, 9 insertions(+), 13 deletions(-)
diff --git a/gcc/config/xtensa/xtensa.cc b/gcc/config/xtensa/xtensa.cc
index 5c1c713e122d
On Wed, Feb 22, 2023 at 7:42 PM Takayuki 'January June' Suwa
wrote:
>
> In commit b2ef02e8cbbaf95fee98be255f697f47193960ec, the sibling call
> insn included (use (reg:SI A0_REG)) to fix the problem, which added
> a USE chain unconditionally to the data flow of register A0 during
> the sibling call
On Wed, Feb 22, 2023 at 7:42 PM Takayuki 'January June' Suwa
wrote:
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.md
> (zero_cost_loop_start, zero_cost_loop_end, loop_end):
> Add missing "SI:" to PLUS RTXes.
> ---
> gcc/config/xtensa/xtensa.md | 12 ++--
> 1 file c
gcc/
PR target/108876
* config/xtensa/xtensa.cc (xtensa_expand_epilogue): Drop emit_use
for A0_REG.
* config/xtensa/xtensa.md (sibcall, sibcall_internal)
(sibcall_value, sibcall_value_internal): Add 'use' expression
for A0_REG.
---
gcc/config/xtensa/
On Fri, Feb 17, 2023 at 8:54 PM Takayuki 'January June' Suwa
wrote:
>
> Leaf function often omits saving its return address to the stack slot,
> and this feature often makes debugging very confusing, especially for
> stack dump analysis.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.cc (xt
Hi Suwa-san,
On Thu, Jan 26, 2023 at 7:17 PM Takayuki 'January June' Suwa
wrote:
>
> In the case of the CALL0 ABI, values that must be retained before and
> after function calls are placed in the callee-saved registers (A12
> through A15) and referenced later. However, it is often the case that
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