> > microblaze Michael Eager
> > -mips portMatthew Fortune
> > +mips portYunQiang Su
>
> Has Matthew agreed to be removed from the maintainer's post? Even if so,
> then he needs to be moved back to the Write After Approval section, as no
> one has deprived him of this right.
>
> Maciej
Robert Suchanek writes:
> This patch adds -mcrc and -mginv options to pass through them
> to the assembler.
>
> Regards,
> Robert
>
> gcc/ChangeLog:
>
> 2018-06-01 Matthew Fortune
>
> * config/mips/mips.h (ASM_SPEC): Pass through -mcrc, -mno-crc,
&g
t; gcc/ChangeLog:
>
> 2018-06-12 Matthew Fortune
> Prachi Godbole
>
> * config/mips/mips-cpus.def: Define P6600.
> * config/mips/mips-tables.opt: Regenerate.
> * config/mips/mips.c (mips_ucbranch_type): New enum.
> (mips_rtx_cost_data): A
Hi,
This patch was developed as part of preparing ever more complex multilib
combinations for the MIPS architecture and aims to solve several problems
in this area. I've attempted to be quite verbose in the description, so
that I can explain how I am using various terms as pretty much everyone
has
Paul Hua writes:
> The gcc.c-torture/execute/scal-to-vec1.c trigger a gcc ICE bug.
>
> It's a mistake in define_expand vec_setv4hi in loongson.md file.
>
> 375 (define_expand "vec_setv4hi"
> 376 [(set (match_operand:V4HI 0 "register_operand" "=f")
> 377 (unspec:V4HI [(match_operand:V4
Robert Suchanek writes:
> The below adds support for -march=p6600. It includes
> a new scheduler plus performance tweaks.
>
> gcc/ChangeLog:
>
> 2018-06-01 Matthew Fortune
> Prachi Godbole
> * config/mips/mips-cpus.def: Define P6600.
> *
Robert Suchanek writes:
> This patch adds i6500 CPU as an alias for i6400.
>
> Regards,
> Robert
>
> gcc/ChangeLog:
>
> 2018-06-01 Matthew Fortune
>
> * config/mips/mips-cpus.def: New MIPS_CPU for i6500.
> * config/mips/mips-tables.opt: Regener
Robert Suchanek writes:
> Update to i6400 scheduler.
>
> Regards,
> Robert
>
> gcc/ChangeLog:
>
> 2018-06-01 Prachi Godbole
>
> * config/mips/i6400.md (i6400_gpmuldiv): Remove cpu_unit.
> (i6400_gpmul): Add cpu_unit.
> (i6400_gpdiv): Likewise.
> (i6400_msa_add_d): Up
Robert Suchanek writes:
> This patch adds -mcrc and -mginv options to pass through them
> to the assembler.
>
> Regards,
> Robert
>
> gcc/ChangeLog:
>
> 2018-06-01 Matthew Fortune
>
> * config/mips/mips.h (ASM_SPEC): Pass through -mcrc, -mno-crc,
&g
Richard Sandiford writes:
> vect_recog_divmod_pattern currently bails out if the target has
> native support for integer division, but I think in practice
> it's always going to be better to open-code it anyway, just as
> we usually open-code scalar divisions by constants.
>
> I think the only cu
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -77,7 +77,7 @@ m68k port Andreas Schwab
m68k-motorola-sysv portPhilippe De Muyter
mcore port Nick Clifton
microblaze Michael Eager
-mips port Matthew Fortune
+mips
Maciej Rozycki writes:
> (we have no support for hard-float n64 MIPS16 code generation), which
> means that the test case will fail, as the regular expression pattern
> expects `lw' and `.word' rather than `ld' and `.dword' respectively to
> appear in assembly code generation. Correct the pattern
Maciej Rozycki writes:
> Given that the SVR4 vs PLT code model consideration is irrelevant for
> this test case rather than rewriting the regular expression to match
> this variant of code just enforce the PLT model by using the `-mplt'
> option. It is safe to use this option unconditionally as i
Hi Paul,
> ChangeLog entries:
>
> gcc/testsuite/ChangeLog
>
> 2018-03-24 Chenghua Xu
>
> * gcc.target/mips/fix-r4000-1.c: Delete "[^\n]" in dg-final.
> * gcc.target/mips/fix-r4000-2.c: Likewise.
> * gcc.target/mips/fix-r4000-3.c: Likewise.
> * gcc.target/mips/fix-r4000-4.c: Li
Hi Paul
> ChangeLog entries:
>
> gcc/testsuite/ChangeLog
>
> 2018-03-24 Chenghua Xu
>
> * gcc.target/mips/umips-stroe16-2.c: Change "length = 2"
> to "l=2" in dg-final.
Looks good. Thanks for the cleanup. OK to commit.
Matthew
Hans-Peter Nilsson writes:
> All patches are together run through the gcc and g++ test-suites
> to check ASAN results for mipsisa32r2el-linux-gnu. As of
> r258635 those results are on par with those for
> arm-linux-gnueabihf, so without delay I present the current
> state. Maybe it's non-intrusi
Jason Merrill writes:
> On Thu, Mar 1, 2018 at 7:02 AM, Matthew Fortune
> wrote:
> > Hi,
> >
> > It seems we have had a bug for some time that causes an ICE and
> prevents the
> > MIPS16 library builds from completing but is likely unrelated to
> MIP
Hi,
It seems we have had a bug for some time that causes an ICE and prevents the
MIPS16 library builds from completing but is likely unrelated to MIPS16.
The problem is when we call target_reinit and library functions get created
as shown in the call stack at the end of this message. The first bui
Hi,
This issue was caught with assert checking enabled but is not a
functional bug as XINT(x, 0) happens to overlay INTVAL(x) anyway.
Committed to trunk.
Thanks,
Matthew
gcc/
* config/mips/mips.c (mips_final_prescan_insn): Fix incorrect
XINT with INTVAL.
(mips_final_post
Tom de Vries writes:
> On 02/26/2018 12:00 PM, Matthew Fortune wrote:
> > Tom de Vries writes:
> >> On 01/08/2018 05:32 PM, Tom de Vries wrote:
> >>> On 12/18/2017 05:57 PM, Vladimir Makarov wrote:
> >>>>
> >>>>
> >>>> On
Tom de Vries writes:
> On 02/26/2018 12:00 PM, Matthew Fortune wrote:
> > Tom de Vries writes:
> >> On 01/08/2018 05:32 PM, Tom de Vries wrote:
> >>> On 12/18/2017 05:57 PM, Vladimir Makarov wrote:
> >>>>
> >>>>
> >>>> On
Tom de Vries writes:
> On 01/08/2018 05:32 PM, Tom de Vries wrote:
> > On 12/18/2017 05:57 PM, Vladimir Makarov wrote:
> >>
> >>
> >> On 12/15/2017 06:25 AM, Tom de Vries wrote:
> >>>
> >>> Proposed Solution:
> >>>
> >>> The patch addresses the problem, by:
> >>> - marking the hard regs that have
Hi Sandra,
> The testcase gcc.target/mips/msa.c gives dozens of FAILs if it's tested
> with a GCC configured to default to -fno-common, because of patterns
> like
>
> /* { dg-final { scan-assembler-times "\t.comm\tv16i8_\\d+,16,16" 3 } }
> */
>
> Seems like the simplest solution is to force -fco
Jim Wilson writes:
> Hand tested to verify that I didn't accidentally break passing -g to
> the assembler.
In case you are waiting on an OK for the MIPS part... this is fine.
Thanks,
Matthew
Simon Atanasyan writes:
> On Mon, Sep 11, 2017 at 03:26:52PM +0000, Matthew Fortune wrote:
> > Simon Atanasyan writes:
> > > Here is the updated patch with chnaged e-mail address and fixed
> > > indentation issues:
> > > -8<
> &g
Simon Atanasyan writes:
> Here is the updated patch with chnaged e-mail address and fixed
> indentation issues:
> -8<
> Currently GCC supports 'long_call', 'far', and 'near' attributes. The
> 'long_call' and 'far' attributes are synonyms. This patch adds support
> for the 'shor
Simon Atanasyan writes:
> Currently GCC supports 'long_call', 'far', and 'near' attributes. The
> 'long_call' and 'far' attributes are synonyms. This patch adds support
> for the 'short_call' attribute as a synonym for `near` to make this list
> complete, consistent with other targets, and compati
Jakub Jelinek writes:
> Bootstrapped/regtested on x86_64-linux and i686-linux, where it improves
> e.g. the code generation for slp-43.c and slp-45.c testcases.
> make cc1 tested in cross-compilers to the remaining targets.
No objections for the MIPS part. I've pointed out this change to Sameera
Maciej Rozycki writes:
> On Fri, 23 Jun 2017, Prachi Godbole wrote:
>
> > Index: gcc/config/mips/mips.md
> > ===
> > --- gcc/config/mips/mips.md (revision 246899)
> > +++ gcc/config/mips/mips.md (working copy)
> > @@ -6578,6 +6581,20
Prachi Godbole writes:
> Please find the updated patch below. I hope I've covered everything.
> I've added the test for inline restriction, could you check if I got all
> the options correct?
I think the test is probably good enough. It is a little too forgiving due
to handling the indirect call
Prachi Godbole writes:
> Changelog:
>
> 2017-04-25 Prachi Godbole
>
> gcc/
> * config/mips/mips.h (machine_function): New variable
> use_hazard_barrier_return_p.
> * config/mips/mips.md (UNSPEC_JRHB): New unspec.
> (mips_hb_return_internal): New insn pattern.
> *
Maciej Rozycki writes:
> Further to my changes made last November here is an update to the MIPS16
> `casesi' pattern making it emit bounds checking as RTL rather than having
> it as hardcoded assembly within the `casesi_internal_mips16_'
> dispatcher. See below for how PR tree-optimization/51513
Hi Paul,
Paul Hua writes:
> cc: Matthew.
>
> ping.
Sorry a little slow on the reply.
> On Thu, Jun 1, 2017 at 3:35 PM, Paul Hua wrote:
> > Hi,
> >
> > There are duplicate testcase in gcc.target/mips dir.
> >
> > div-5.c same as div-9.c.
> > div-6.c same as div-10.c.
> > div-7.c same as div-1
Bernd Edlinger writes:
> This is my new attempt to clean up the different cross compiler
> configurations. It turned out to be a very complicated matter,
> so I thought it would be better to postpone it to the stage1.
>
> In a canadian cross compiler setup we have a different header dir path
> f
Jakub Jelinek writes:
> On Thu, Apr 20, 2017 at 12:49:49PM +0000, Matthew Fortune wrote:
> > Hi Jeff,
> >
> > I missed a load of test failures while on vacation and just noticed
> > that the fix you did for a potentially uninitialized variable warning
> > is overw
hangeLog
index c908048..80d3436 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2017-04-20 Matthew Fortune
+
+ * config/mips/mips.c (mips_expand_vec_perm_const): Re-fix
+ uninitialized variable warning to avoid buffer overrun.
+
2017-04-20 Alexander Monakov
Jeff Law writes:
> All the MIPS compilers will fail to build using the trunk due to a
> couple minor uninitialized memory issues.
>
> First in mips_multi_add we add an uninitialized mips_multi_member object
> to the mips_multi_members vec. It's easy enough to just memset the new
> member.
>
> S
Hi Catherine,
I'm following up on PR target/80057 to update the description of -mvirt.
I agree with Roland that the description is inconsistent and should not
state 'application specific' as none of the other ASE options include
it. Instead I suggest we put the shortened form of (VZ) in like (XPA
Another MSA related fix; this time relating to using -mno-odd-spreg.
This fixes a build-failure with gcc.c-torture/execute/20050604-1.c
when using -mabi=32 -mmsa -mno-odd-spreg.
The fix is to copy the whole vector from the odd-numbered source
register to the even numbered single-precision destinat
This is a fix for a compile failure in gcc.c-torture/compile/pr70240.c
with options -O1 -mmsa.
The expand code for replicated constant vectors with small immediate
values was simply wrong and would never work. This code is not used in the
simple case of initialising a variable with a constant vect
pr52125.c verifies that orphaned %hi relocs are deleted if they feed
an inline asm statement that never emits the %lo part. Orphaned %hi
relocs are only strictly a problem for o32 but are eliminated for
any ABI as long as 32-bit addressing is in use so force -msym32 as well
as require absolute addr
Toma Tabacu writes:
> The pic-3,4.c and pie-3,4.c tests are failing for some configurations of
> mips*-*-linux-*.
>
> This is because PIC is always on for MIPS Linux by default, except when the
> compiler is built with --with-mips-plt, in which case PIC is on by default
> only
> for the n64 ABI,
Toma Tabacu writes:
> The gcc.dg/pic-2.c and gcc.dg/pie-2.c tests are failing for MIPS targets
> because __PIC__ is always set to 1 for MIPS.
>
> This patch makes the testsuite skip those two tests for all MIPS
> targets.
>
> Tested with mips-mti-elf and mips-mti-linux-gnu.
>
> Should I have fi
x27; basic block is fixed almost immediately
anyway making the offending check potentially unnecessary in
the first place.
Thanks,
Matthew
> -Original Message-
> From: Toma Tabacu
> Sent: 07 March 2017 11:44
> To: gcc-patches@gcc.gnu.org
> Cc: Matthew Fortune
The lxc1-sxc1 tests fundamentally require hard-float to test the
relevant instruction usage. This patch adds -mhard-float to force
it on all configurations.
gcc/testsuite/
* gcc.target/mips/lxc1-sxc1-1.c: Use -mhard-float.
* gcc.target/mips/lxc1-sxc1-2.c: Likewise.
Committed to
Rainer Orth writes:
> > g++.dg/lto/pr69589_0.C is currently failing for mips-mti-elf with the
> following error:
> >
> > xg++: error: unrecognized command line option '-rdynamic'
> >
> > However, it passes just fine for mips-mti-linux-gnu.
> > I think that we should skip this test for mips-mti-elf
Prachi Godbole writes:
> 2017-03-09 Prachi Godbole
>
> gcc/testsuite/
> * gcc.target/mips/msa-bclri.c: Skip the test for -O0.
>
>
> Index: testsuite/gcc.target/mips/msa-bclri.c
> ===
> --- testsuite/gcc.target/mips/msa-bcl
Jakub Jelinek writes:
> >
> > ../../gcc/config/mips/mips-msa.md:1219:1: vec_select parallel with 2
> > elements, expected 4
> > ../../gcc/config/mips/mips-msa.md:1219:1: vec_select parallel with 2
> > elements, expected 4
> > ../../gcc/config/mips/mips-msa.md:1219:1: vec_select parallel with 2
> >
Toma Tabacu writes:
> gcc/testsuite/
>
> * gcc.target/mips/inline-memcpy-3.c (dg-options): Add -mabi=32.
OK, thanks. Sorry for the slow reply.
Matthew
Prachi Godbole writes:
> 2017-03-06 Prachi Godbole
>
> gcc/
> * config/mips/mips-msa.md (msa_fmax_a_,
> msa_fmin_a_,
> msa_max_a_, msa_min_a_): Introduce mode interator
> for
> if_then_else.
> (smin3, smax3): Change operand print code from 'B' to
> 'E'.
>
> gcc/testsui
Prachi Godbole writes:
> 2017-03-06 Prachi Godbole
>
> gcc/
> * config/mips/mips-msa.md (msa_dotp__d, msa_dpadd__d,
> msa_dpsub__d): Fix MODE for vec_select.
>
> gcc/testsuite/
> * gcc.target/mips/msa-dotp.c: New tests.
OK, thanks.
Matthew
Prachi Godbole writes:
> 2017-03-06 Prachi Godbole
>
> gcc/
> * config/mips/mips.c (mips_gen_const_int_vector): Change type of
> last
> argument.
> * config/mips/mips-protos.h (mips_gen_const_int_vector): Likewise.
>
> gcc/testsuite/
> * gcc.target/mips/msa-bclri.c: Ne
Toma Tabacu writes:
> pr68273.c currently fails when targeting MIPS64 with the n64 ABI.
> This is because it is checking for some registers in SImode, but, because of
> n64, they will actually be in DImode.
>
> This patch restricts matching for SImode registers to ilp32 targets and adds
> matchin
Moore, Catherine writes:
> > -Original Message-
> > From: Matthew Fortune [mailto:matthew.fort...@imgtec.com]
> > Sent: Friday, February 24, 2017 8:58 AM
> > To: Moore, Catherine
> > Cc: 'gcc-patches@gcc.gnu.org' (gcc-patches@gcc.gnu.org) > pa
Hi Catherine,
Can you review the description for -mload-store-pairs please?
Thanks,
Matthew
gcc/
PR target/79473
* doc/invoke.texi: Document -mload-store-pairs.
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 6e5fa56..f1fc449 100644
--- a/gcc/doc/invoke.texi
+++ b/g
Hi Catherine,
I missed a couple of testsuite changes that are needed to deal with the
fallout of fixing the ABI issues for floating point vectors. I had them
in my tree but forgot to post. The ABI change for V2SF i.e. paired
single is a bug fix as the behaviour was unintended and violates the go
Moore, Catherine writes:
> > As this is an ABI fix, just wait a day or so in case Catherine has
> > any comment otherwise OK to commit.
> >
> I have not further comments on this patch. Please commit.
Hi Sameera,
I've been considering this patch further and have realised that my review
was preo
Eric Botcazou writes:
> > The condition would look like this, What do you think?
> >
> > if (!(GET_MODE_PRECISION (mode) != GET_MODE_PRECISION (innermode)
> > && GET_MODE_SIZE (mode) <= UNITS_PER_WORD
> > && GET_MODE_SIZE (innermode) <= UNITS_PER_WORD
> >
> > I will keep working on this code post GCC 7 as the topic is bugging me
> now
> > :-)
>
> I'm OK to lend a hand, but what's left for GCC 7 to make MIPS happy?
I have just successfully bootstrapped MIPS with just the pending (amended)
patch (3). i.e. with this patch (1) reverted so I did not ne
Eric Botcazou writes:
> > Agreed. I don't think things like WORD_MODE_OPERATIONS should change
> > rtl semantics, just optimisation decisions.
Sorry, I did cover two topics in one email. My point was about whether
simplifying:
(subreg:OUTER (mem:INNER ...))
To:
(mem:OUTER ...)
Should ever be
Richard Sandiford writes:
> Matthew Fortune writes:
> > Eric Botcazou writes:
> >> > Thanks for reporting. I'll take a brief look first but revert if
> >> > the issue isn't something that vaguely makes sense to me.
> >>
> >> You
Eric Botcazou writes:
> > Thanks for reporting. I'll take a brief look first but revert if the
> > issue isn't something that vaguely makes sense to me.
>
> You need to restrict any WORD_REGISTER_OPERATIONS test to subword
> registers.
I've reverted this. I haven't been able to quickly find a ch
Christophe Lyon writes:
> On 21 February 2017 at 11:59, Kyrill Tkachov
> wrote:
> >
> > On 21/02/17 10:54, Christophe Lyon wrote:
> >>
> >> Hi,
> >>
> >> On 20 February 2017 at 13:08, Matthew Fortune
> >> wrote:
> >>>
&g
32 b)
{
return a + b;
}
As this is an ABI fix, just wait a day or so in case Catherine has
any comment otherwise OK to commit.
Thanks,
Matthew
>
> - Thanks and regards,
> Sameera D.
>
> From: Sameera Deshpande
> Sent: 08 Februar
Vladimir Makarov writes:
> On 02/07/2017 09:08 AM, Matthew Fortune wrote:
> > Hi,
> >
> > This patch addresses a problem with LRA splitting hard registers where
> > the mode requires multiple registers. When splitting then each
> > constituent register is split i
Vladimir Makarov writes:
> On 02/07/2017 09:08 AM, Matthew Fortune wrote:
> > Hi,
> >
> > This patch partially reverts r243782 where a return false was added
> > expecting it to be a no-op. Detailed inspection shows this was not
> > true. Despite no bug bein
Matthew Fortune writes:
> This change addresses a comment from Richard Sandiford in:
> https://gcc.gnu.org/ml/gcc-patches/2015-01/msg02165.html
>
> where a previous fix was over eager in converting OP_OUT reloads to
> OP_INOUT.
>
> No testcase here either but I will try a
Vladimir Makarov writes:
> On 02/07/2017 09:08 AM, Matthew Fortune wrote:
> > Hi,
> >
> > This change deals with reloading a subreg(reg) using the inner mode to
> > prevent partial spilling of data like in the case described here:
> > https://gcc.gnu.org/
Hi Eric,
Any thoughts on this?
Thanks,
Matthew
> Sorry for the slow reply, been away for a few days
>
> Eric Botcazou writes:
> > > This patch is a minimal change to prevent (subreg(mem)) from being
> > > simplified to use the outer mode for WORD_REGISTER_OPERATIONS.
> > > There is high pr
Sorry for the slow reply, been away for a few days
Eric Botcazou writes:
> > This patch is a minimal change to prevent (subreg(mem)) from being
> > simplified to use the outer mode for WORD_REGISTER_OPERATIONS. There
> > is high probability of refining and/or re-implementing this for GCC 8
>
Eric Botcazou writes:
> > @Eric: thanks for the offer of sparc testing; please can you let me
> > know if there are any issues?
>
> Sure, but can you post a consolidated patch as an attachment? (btw it's
> SPARC instead of sparc, like MIPS instead of mips I presume).
I've attached the consolidat
Hi,
This patch addresses a problem with LRA splitting hard registers
where the mode requires multiple registers. When splitting then
each constituent register is split individually using the widest
mode for each register but no check is made that such a mode is
actually supported in those registe
Hi,
This patch partially reverts r243782 where a return false was added
expecting it to be a no-op. Detailed inspection shows this was not
true. Despite no bug being identified following the change, removing
the early return is likely to be safer than leaving it in place.
This is supported by t
Hi,
This patch is a minimal change to prevent (subreg(mem)) from being
simplified to use the outer mode for WORD_REGISTER_OPERATIONS. There
is high probability of refining and/or re-implementing this for GCC 8
but such a change would be too invasive. This change at least ensures
correctness but
Hi,
This change addresses a comment from Richard Sandiford in:
https://gcc.gnu.org/ml/gcc-patches/2015-01/msg02165.html
where a previous fix was over eager in converting OP_OUT reloads to
OP_INOUT.
No testcase here either but I will try and exercise this code later
with a targeted test using the
t is not a WORD_REGISTER_OPERATIONS target. If anyone can give
a recipe for bootstrapping ARM on a compile farm machine I will do that
but I have no idea how to get the ARM multiarch stuff to work in Ubuntu.
Thanks,
Matthew
Matthew Fortune (4):
Handle WORD_REGISTER_OPERATIONS when reloading (subreg (reg))
Tighten
Hi,
This change deals with reloading a subreg(reg) using the inner mode
to prevent partial spilling of data like in the case described here:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78660#c8
No test case for now but I am investigating a targeted test using
the RTL frontend for later submissio
Toma Tabacu writes:
> Matthew Fortune writes:
> >
> > That's not what I hoped but is what I was concerned about as I believe
> > it means we have a change of behaviour. It boils down to simply
> > ignoring the argument type of unsigned char. My guess is that a z
Toma Tabacu writes:
> > From: Matthew Fortune
> > > +/* The third argument needs to be in SImode in order to succesfully
> > > match
> > > + the operand from the insn definition. */
> >
> > Please refer to operand here not argument as it
Toma Tabacu writes:
> The builtins for the pshufh, psllh, psllw, psrah, psraw, psrlh, psrlw
> Loongson instructions have the third argument's type set to UQI while
> its corresponding insn operand is in SImode.
>
> This results in the following error when matching insn operands:
>
> ../gcc/gcc/i
Moore, Catherine writes:
> > -Original Message-
> > From: Matthew Fortune [mailto:matthew.fort...@imgtec.com]
> > Sent: Thursday, January 19, 2017 5:30 PM
> > To: Moore, Catherine
> > Cc: 'Aurelien Jarno' ; 'Richard Sandiford'
> >
Matthew Fortune writes:
> I've rewritten/simplified this patch as it provides far too much control
> to end users who will undoubtedly shoot themselves in the foot so to
> speak. The option I intend to support is simply --with-madd4 --without-madd4
> and -mmadd4 -mno-madd4.
suite/gcc.target/mips/madd4-1.c
create mode 100644 gcc/testsuite/gcc.target/mips/madd4-2.c
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e53f9e1..7496071 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,19 @@
+2017-01-19 Matthew Fortune
+ Yunqiang Su
+
+ * confi
Hi Paul,
Your latest version of the patch is now committed. I have been doing some
work on the recursive build failure but the issue is complex and involves
LRA so I went ahead with committing your change independently. It also
turns out that (at least when targeting loongson3a) there are stage2
nused.
This optimization is off by default at all optimization levels.
+@item -mlxc1-sxc1
+@itemx -mno-lxc1-sxc1
+@opindex mlxc1-sxc1
+When applicable, enable (disable) the generation of @code{lwxc1},
+@code{swxc1}, @code{ldxc1}, @code{sdxc1} instructions. Enabled by default.
+
Toma Tabacu writes:
> Matthew Fortune writes:
> >
> > Sounds good. I'd prefer to get the testsuite clean first then improve the
> > code quality as a later step since it is not a regression and we are
> > a few days off stage 4.
> >
> > In terms of
Maciej Rozycki writes:
> On Mon, 16 Jan 2017, Toma Tabacu wrote:
>
> > After searching through the archives, I have found an interesting bit
> > of information about DIV.G/MOD.G in the original submission thread:
> >
> > > > Ruan Beihong 23 July 2008:
> > > >
> > > > I've seen the Loongson 2F man
Moore, Catherine writes:
> > -Original Message-
> > From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> > ow...@gcc.gnu.org] On Behalf Of Matthew Fortune
> > Sent: Monday, January 16, 2017 11:25 AM
> > To: Doug Gilmore ; gcc-
> > patc...@
Doug Gilmore
> I recently bisected PR78176 to problems introduced with r21650.
>
> Given the short time until the release, we would like to provide a
> target flag and build option to avoid the bug until we are able to
> resolve the problem with the commit. Note that as Matt
Kito Cheng writes:
> On Mon, Jan 16, 2017 at 02:42:08PM +0800, Kito Cheng wrote:
> > 2017-01-16 Kito Cheng
> > Kuan-Lin Chen
> >
> > PR target/PR79079
> > * gcc/internal-fn.c (expand_mul_overflow): Use convert_modes
> instead of
> > gen_lowpart.
Thanks for t
Maciej Rozycki writes:
> On Thu, 12 Jan 2017, Toma Tabacu wrote:
>
> > > > Unfortunately, this interferes with the generation of DIV.G and
> > > > MOD.G (the div3 and mod3 patterns) for Loongson
> > > > targets,
> > > which
> > > > causes test failures.
> > >
> > > What test failures? Details p
Maciej Rozycki writes:
> On Thu, 5 Jan 2017, Matthew Fortune wrote:
> > It is true to say that users are discouraged from using 2008-NaN with
> > soft-float for pre-R6 architectures simply to avoid further fragmentation
> > of software for no real gain. However, for R6 then s
Sandra Loosemore writes:
> On 01/10/2017 07:24 AM, Yunqiang Su wrote:
> > Hi, folks, any idea about this patch?
>
> I can only comment on the documentation parts.
I am reviewing the patch but need to determine if the changes are sufficient and
safe to meet the goal. This area is complex in the M
Joseph Myers writes:
> On Wed, 4 Jan 2017, Maciej W. Rozycki wrote:
>
> > AFAIR we deliberately decided not to define a 2008-NaN soft-float
> > ABI, and chose to require all soft-float binaries to use the legacy
> encoding.
>
> Soft-float and 2008-NaN are naturally completely orthogonal and the
Joseph Myers writes:
> The MIPS sfp-machine.h has an _FP_CHOOSENAN implementation which
> emulates hardware semantics of not preserving signaling NaN payloads for
> an operation with two NaN arguments (although that doesn't suffice to
> avoid sNaN payload preservation in any case with just one NaN
Sandra Loosemore writes:
> On 12/21/2016 11:54 AM, Yunqiang Su wrote:
> > By this patch, I add a build-time option ` --with-unfused-madd4=yes/no',
> > and runtime option -m(no-)unfused-madd4,
> > to disable generate madd.fmt instructions.
>
> Your patch also needs a documentation change so that t
Hi Paul,
Apologies for the delay in responding.
> I get the copyright assignment, it's ok for commit.
Thanks for going through copyright assignment, I can see you listed and
also you have commit access now. Is the trunk build failure still
present for you, if it is now resolved then please go ah
Toma Tabacu writes:
> microMIPS is not supported on pre-R2 architectures, but the testsuite allows
> it to be used on pre-R2 architectures, which results in test failures.
>
> This patch makes the testsuite upgrade to R2 if -mmicromips is used in a test.
>
> Tested with mips-mti-elf.
>
> Regard
Toma Tabacu writes:
> In the case of mips16-attributes.c, even though the (-mips16) option ensures
> that -mmicromips will be overriden, there still is a dg-skip-if for
> -mmicromips.
>
> I think that it is not necessary and it actually decreases test coverage,
> because it will cause the testsu
Toma Tabacu writes:
> >
> > It's a shame this is the only way to deal with this but I see aarch64
> > have to resort to the same thing for error checking tests.
> >
>
> I have looked into this some more and I 've found that the solution I
> proposed is incomplete.
>
> The problem is that if no l
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