[PATCH] RISC-V: add TARGET_ZBKB to the condition of bswapsi2, bswapdi2 and rotr3 patterns

From: Sinan Lin tell gcc that zbkb has these two spn to enable some optimizations. e.g. 1) the rrotate_expr could match to rotrm3 during expand; 2) hook up __builtin_bswap64 with `rev8` in zbkb64. --- gcc/config/riscv/bitmanip.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff

[PATCH] RISC-V: avoid splitting small constant in i_extrabit pattern

From: Sinan Lin there is no need to split an xori/ori with an small constant. take the test case `int foo(int idx) { return idx|3; }` as an example, rv64im_zba generates: ori a0,a0,3 ret but, rv64im_zba_zbs generates: ori a0,a0,1 ori a0,a0,2 re

[PATCH] RISC-V: Fix wrong partial subreg check for bsetidisi

From: Lin Sinan The partial subreg check should be for subreg operand(operand 1) instead of the immediate operand(operand 2). This change also fix pr68648.c in zbs. gcc/ChangeLog: * config/riscv/bitmanip.md: Fix wrong index in the check. --- gcc/config/riscv/bitmanip.md | 2 +- 1 file

[PATCH RESEND] riscv: improve the cost model for loading a 64bit constant in rv32.

The motivation of this patch is to correct the wrong estimation of the number of instructions needed for loading a 64bit constant in rv32 in the current cost model(riscv_interger_cost). According to the current implementation, if a constant requires more than 3 instructions(riscv_const_insn and