Re: [PATCH] RISC-V: Put jump table in text for large code model

committed :) On Mon, Apr 14, 2025 at 6:01 PM Kito Cheng wrote: > > This patch will be committed this week if CI passes and not strong > objections since it's bug to large code model, also change is small > > On Mon, Apr 14, 2025 at 6:00 PM Kito Cheng wrote: > > >

Re: [PATCH v2] riscv: Fix incorrect gnu property alignment on rv32

Thanks, committed to trunk :) On Fri, Apr 11, 2025 at 12:27 PM Jesse Huang wrote: > > Codegen is incorrectly emitting a ".p2align 3" that coerces the > alignment of the .note.gnu.property section from 4 to 8 on rv32. > > 2025-04-11 Jesse Huang > > gcc/ChangeLog > > * config/riscv/riscv

Re: [PATCH] RISC-V: Put jump table in text for large code model

This patch will be committed this week if CI passes and not strong objections since it's bug to large code model, also change is small On Mon, Apr 14, 2025 at 6:00 PM Kito Cheng wrote: > > Large code model assume the data or rodata may put far away from > text section. So we ne

Re: RISC-V: revert pr114194 tests on gcc-14 [PR118601]

LGTM, thanks :) Alexandre Oliva 於 2025年4月15日 週二 12:25 寫道： > > And here's another that came up more recently: > > The gcc-14 backport that split the pr114194 testcase for rv32 and rv64 > would only generate the expected rv32 sequence if commit > 6b315907c0353f71169a7555e653d29a981fef67 had also b

Re: RISC-V: adjust testcase for gcc-14 [PR118182]

OK for GCC 14 branch, thanks :) On Tue, Apr 15, 2025 at 12:23 PM Alexandre Oliva wrote: > > On Apr 14, 2025, Jeff Law wrote: > > > No strong opinion. I'd lean towards xfail or twiddling the test since > > that's obviously super-save WRT codegen on the gcc-14 release branch. > > Twiddling it is,

[PATCH] RISC-V: Put jump table in text for large code model

Large code model assume the data or rodata may put far away from text section. So we need to put jump table in text section for large code model. gcc/ChangeLog: * config/riscv/riscv.h (JUMP_TABLES_IN_TEXT_SECTION): Check if large code model. gcc/testsuite/ChangeLog: * g

Re: [PATCH] RISCV :Added MIPS P8700 Subtarget.

Could you break this patch into two pieces: 1) Add new extensions. 2) Add new core (for -mcpu), pipeline model and cost model > diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1326c67563a..d2642390b2a > 100644 > --- a/gcc/ChangeLog > +++ b/gcc/ChangeLog > @@ -1,3 +1,24 @@ > +2025-04-09 Umesh K

Re: [PATCH] riscv: Fix incorrect gnu property alignment on rv32

On Thu, Apr 10, 2025 at 9:12 PM Jesse Huang wrote: > > Codegen is incorrectly emitting a ".p2align 3" that coerces the > alignment of the .note.gnu.property section from 4 to 8 on rv32. > --- > gcc/config/riscv/riscv.cc | 2 +- > gcc/testsuite/gcc.target/riscv/gnu-proper

[committed] RISC-V: Fix the behavior for multilib-generator with --cmodel=large on rv32

Large code model is only supported on RV64, so we don't need to generate the multilibs for RV32 with --cmodel=large. And the compact code model is something we don't supported on upstream (which is accidentally added in the past), so we need to remove it. gcc/ChangeLog: * config/riscv/mul

[committed] RISC-V: Include local riscv_vector.h in testsuite

That could prevent us including stdint.h from glibc, and that will cause problem when the corresponding multilib isn't built. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c: Include local riscv_vector.h. * gcc.target/riscv/rvv/base/abi-ca

Re: [PATCH] riscv: Fix r15-9270 fallout on RISC-V

Hi Jakub: Checked with SVE's implementation and seems right for RVV, so OK for trunk, thanks :) On Wed, Apr 9, 2025 at 9:24 PM Jakub Jelinek wrote: > > Hi! > > On Wed, Apr 09, 2025 at 02:38:01PM +0200, Mark Wielaard wrote: > > Unfortunately this seems to have broken the riscv bootstrap: > > http

Re: [PATCH] [testsuite] [riscv] limit vwaddsub-1.c to rv64

On Tue, Apr 1, 2025 at 12:47 PM Jeff Law wrote: > > > > On 3/31/25 7:03 PM, Alexandre Oliva wrote: > > On Mar 31, 2025, Jeff Law wrote: > >> I don't immediately see anything in this test or its history to > >> indicate it's only supposed to work for rv64. > > > > It's the 64-bit integral argument

Re: [PATCH v2] RISC-V: Tweak testcase for PIE

Push to trunk since the CI is green :) On Tue, Apr 1, 2025 at 3:43 PM Kito Cheng wrote: > > Linux toolchain may configured with --enable-default-pie, and that will > cause lots of regression test failures because the function name will > append with @plt suffix (e.g. `call foo` beco

[PATCH v2] RISC-V: Tweak testcase for PIE

Linux toolchain may configured with --enable-default-pie, and that will cause lots of regression test failures because the function name will append with @plt suffix (e.g. `call foo` become `call foo@plt`), also some code generation will different due to the code model like the address generation

[PATCH] RISC-V: Tweak testcase for PIE

Linux toolchain may configured with --enable-default-pie, and that will cause lots of regression test failures because the function name will append with @plt suffix (e.g. `call foo` become `call foo@plt`). We may consider just drop @plt suffix to prevent that at all, because it's not difference b

Re: [PATCH] RISC-V: testsuite: Fix broken testsuite error of zicbop

Thanks, pushed to trunk :) On Mon, Mar 31, 2025 at 4:54 PM Liao Shihua wrote: > > Fix broken testsuite like > "ERROR: gcc.target/riscv/cmo-zicbop-2.c -Os : 1: too many arguments for " > dg-do 1 compile target { { rv32-*-*}} " > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/cmo-zicb

Re: [PATCH v3] RISC-V: Fix wrong LMUL when only implict zve32f.

Hi Robin: Pushed to trunk, thanks, On Mon, Mar 31, 2025 at 11:23 PM Robin Dapp wrote: > > LGTM (even though I still don't like the spec :D). Yeah...and I also don't like the magic "ceil(AVL / 2) ≤ vl ≤ VLMAX if AVL < (2 * VLMAX)" rule... > We still have an implicit assumption in riscv-vsetvl.

[PATCH v3] RISC-V: Fix wrong LMUL when only implict zve32f.

abi-18.c: Update test. gcc.target/riscv/rvv/base/vsetvl_zve32-1.c: New test. gcc.target/riscv/rvv/base/vsetvl_zve32-2.c: New test. Co-authored-by: Kito Cheng --- gcc/config/riscv/riscv-v.cc | 8 +- .../riscv/riscv-vector-builtins-types.def | 322 +-

Re: [PATCH] RISC-V: Remove the priority in FMV ASM name mangling

Will it only cause issues with this patch https://gcc.gnu.org/pipermail/gcc-patches/2025-March/678918.html or will it cause problems with the current trunk as well? If the latter one, could you provide a case for that? Thanks :) On Tue, Mar 25, 2025 at 7:15 PM Yangyu Chen wrote: > > We don't ne

Re: [PATCH v2] RISC-V: Fix wrong LMUL when only implict zve32f.

Hi Robin Sorry Kito, that we're having so much back and forth here, it's not my > intention to block anything (not that I could anyway). I just want to > make sure I properly understand the rationale (or the spec, rather). > No worries, it's a great chance to clarify the spec together :) Some t

Re: [PATCH v2] RISC-V: Fix wrong LMUL when only implict zve32f.

On Mon, Mar 24, 2025 at 11:35 PM Robin Dapp wrote: > > > This does not only happen on ELEN=32 and VLEN=32, it happened on all > > ELEN=32 arch, and one of our internal configurations hit this... > > Wait, is there something I keep missing? There must be I guess. > > Disregarding the SEW=8 case be

Re: [PATCH v2] RISC-V: Fix wrong LMUL when only implict zve32f.

On Mon, Mar 24, 2025 at 6:53 PM Robin Dapp wrote: > > Hi Kito, > > > So valid range fractional LMUL for SEW=8, 16 32 are: > > > > mf8 = [8, (1/8)*32] = [8, 4] = [], no SEW is valid with mf8 for ELEN = 32 > > mf4 = [8, (1/4)*32] = [8, 8] = only SEW 8 with mf4 is valid > > mf2 = [8, (1/2)*32] = [8,

Re: [PATCH v2] RISC-V: Fix wrong LMUL when only implict zve32f.

Hi Robin: Just got few more clarifications from Andrew about the behavior for the valid* LMUL for ELEN=32, * valid may not be a precise word, anyway, the spec guarantees that it should be implemented. Spec[1] say: --- When LMUL < SEWMIN/ELEN, there is no guarantee an implementation would have

[PATCH v2] driver: Fix multilib_os_dir and multiarch_dir for those target use TARGET_COMPUTE_MULTILIB

This patch fixes the multilib_os_dir and multiarch_dir for those targets that use TARGET_COMPUTE_MULTILIB, since the TARGET_COMPUTE_MULTILIB hook only update/fix the multilib_dir but not the multilib_os_dir and multiarch_dir, so the multilib_os_dir and multiarch_dir are not set correctly for those

Re: [PATCH 1/2] Add TARGET_COMPUTE_MULTILIB_OS hook to override multi-lib-os result.

Hi Jin Ma: I realized multilib os dir is not correctly set as you described, but I think that info should just come from multilib_select rather than creating a new hook to do that, anyway I just wrote a fix...because we hit that issue last week... Hi Jeff: Here is another approach to fix that -

[PATCH] driver: Fix multilib_os_dir and multiarch_dir for those target use TARGET_COMPUTE_MULTILIB

This patch fixes the multilib_os_dir and multiarch_dir for those targets that use TARGET_COMPUTE_MULTILIB, since the TARGET_COMPUTE_MULTILIB hook only update/fix the multilib_dir but not the multilib_os_dir and multiarch_dir, so the multilib_os_dir and multiarch_dir are not set correctly for those

Re: [PATCH v2] RISC-V: Fix a typo in zce to zcf implication

Hi Yuriy: V2 is LGTM, thanks :) On Wed, Feb 26, 2025 at 3:06 AM Yuriy Kolerov wrote: > > Hi Jeff, > > That check is performed in a lambda function: > > {"zce", "zcf", >[] (const riscv_subset_list *subset_list) -> bool >{ > return subset_list->xlen () == 32 && subset_list->lookup (

Re: [PATCH] RISC-V: Fix .cfi_offset directive when push pop in zc

Pushed with minor coding style fix: https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=4dcd3c7749734133f7f59509b1a118f3a13de4ee On Mon, Feb 24, 2025 at 4:00 PM Kito Cheng wrote: > > Thanks, will push after verified on my hand :) > > On Mon, Feb 24, 2025 at 3:20 PM Hsing Yu

Re: [PATCH] RISC-V: Fix .cfi_offset directive when push pop in zc

Thanks, will push after verified on my hand :) On Mon, Feb 24, 2025 at 3:20 PM Hsing Yu Peng wrote: > > Address Fei's comment. > > Thanks > Lino > > Fei Gao 於 2025年2月24日 週一 下午2:20寫道： > > > > The case you hit is s2 set in frame mask but s1 not. So you're trying to > > set s1 bit manually. > > If

Re: [RFC] RISC-V: The optimization ignored the side effects of the rounding mode, resulting in incorrect results.

We already have a use of "(reg:SI FRM_REGNUM)" within the pattern, is it not enough? I believe the answer is not enough so you propose this patch, so could you explain a few more about what happened? (define_insn "@pred_single_widen__scalar" [(set (match_operand:VWEXTF 0 "register_operand"

Re: [PATCH v2] RISC-V: unrecognizable insn ICE in xtheadvector/pr114194.c on 32bit targets

LGTM, that seems right way to fix :) Jin Ma 於 2025年2月11日 週二 21:45 寫道： > This is a follow-up to the patch below to avoid generating unrecognized > vsetivl instructions for XTheadVector. > > https://gcc.gnu.org/pipermail/gcc-patches/2025-January/674185.html > > PR target/118601 > > gcc/Cha

Re: [PATCH] RISC-V: unrecognizable insn ICE in xtheadvector/pr114194.c on 32bit targets

Could you add a few more comments to explain why xtheadvector is not supported? Maybe something like: /* Xtheadvector doesn't support it because of the lack of XXX instrucion. */ On Mon, Feb 10, 2025 at 4:38 PM Jin Ma wrote: > > On Sun, 09 Feb 2025 14:04:00 +0800, Jin Ma wrote: > > PR t

Re: [PATCH] RISC-V: Fix wrong LMUL when only implict zve32f.

cc Robin an Ju-Zhe On Tue, Feb 4, 2025 at 3:16 PM Monk Chiang wrote: > > According to Section 3.4.2, Vector Register Grouping, in the RISC-V > Vector Specification, the rule for LMUL is LMUL >= SEW/ELEN > --- > gcc/config/riscv/riscv-v.cc | 8 +- > gcc/config/riscv/riscv-vect

Re: [PATCH V5 0/2] RISC-V: Add intrinsics support and testcases for SiFive Xsfvcp extension.

LGTM but defer to GCC 16 :) On Tue, Jan 21, 2025 at 11:43 AM wrote: > > From: yulong > > This patch implements the Sifvie vendor extension Xsfvcp[1] > support to gcc. Providing a flexible mechanism to extend application > processors with custom coprocessors and variable-latency arithmetic >

[committed] RISC-V: Add sifive_vector.h

sifive_vector.h is a vendor specfic header, it should include before using sifive vector intrinsic, it's just include riscv_vector.h for now, we will separate the implementation by adding new pragma in future. gcc/ChangeLog: * config.gcc (riscv*): Install sifive_vector.h. * config

Re: [PATCH v3 2/2] RISC-V: Update Xsfvqmacc and Xsfvfnrclip's testcases

committed, thanks :) On Fri, Dec 13, 2024 at 8:39 PM Jiawei wrote: > > From: Liao Shihua > > Update Sifive Xsfvqmacc and Xsfvfnrclip extension's testcases. > > version log: > Update synchronize LMUL settings with return type. > > gcc/ChangeLog: > > * config/riscv/vector.md: New a

Re: [PATCH v3 1/2] RISC-V: Update Xsfvfnrclip implementation.

committed, thanks :) On Fri, Dec 13, 2024 at 8:39 PM Jiawei wrote: > > Update implementation of Xsfvfnrclip, using return type as iterator. > > gcc/ChangeLog: > > * config/riscv/genrvv-type-indexer.cc (expand_floattype): New func. > (main): New type. > * config/riscv/riscv

Re: [PATCH v5 1/4] RISC-V: Add Zicfiss ISA extension.

(_Unwind_Frames_Extra): Define. > (_Unwind_Frames_Increment): Define. > > gcc/testsuite/ChangeLog: > * gcc/testsuite/gcc.target/riscv/ssp-1.c: New test. > * gcc/testsuite/gcc.target/riscv/ssp-2.c: New test. > > Co-Developed-by: Greg McGary , >

Re: [PATCH v3 1/4] RISC-V: Add Zicfiss ISA extension.

OK with one minor comment On Wed, Jan 15, 2025 at 3:57 PM Monk C > --- /dev/null > +++ b/libgcc/config/riscv/shadow-stack-unwind.h > @@ -0,0 +1,74 @@ > +/* _Unwind_Frames_Extra with shadow stack. > + Copyright (C) 2016-2024 Free Software Foundation, Inc. 2025 rather than 2016-2024.

Re: [PATCH v3 3/4] RISC-V: Add .note.gnu.property for ZICFILP and ZICFISS ISA extension

OK with one minor comment: > diff --git a/gcc/config/riscv/linux.h b/gcc/config/riscv/linux.h > index 9060c940a44..c1cfa9bf28a 100644 > --- a/gcc/config/riscv/linux.h > +++ b/gcc/config/riscv/linux.h > @@ -61,6 +61,8 @@ along with GCC; see the file COPYING3. If not see > -dynamic-linker "

Re: [PATCH v2 2/4] RISC-V: Add Zicfilp ISA extension.

OK with few minor comments > This patch only support landing pad value is 1. Should be 0? > --- /dev/null > +++ b/gcc/config/riscv/riscv-zicfilp.cc > @@ -0,0 +1,169 @@ > +/* Branch Target Identification for RISCV architecture. > + Copyright (C) 2019-2024 Free Software Foundation, Inc. 2025 >

Re: [PATCH v4] RISC-V: Fix code gen for reduction with length 0 [PR118182]

committed to trunk On Mon, Jan 6, 2025 at 6:06 PM Kito Cheng wrote: > > `.MASK_LEN_FOLD_LEFT_PLUS`(or `mask_len_fold_left_plus_m`) is expecting the > return value will be the start value even if the length is 0. > > However current code gen in RISC-V backend is not meet that se

Re: [PATCH] RISC-V: fix thinko in riscv_register_move_cost ()

Thanks, that's apparently my stupid mistake...:P On Tue, Jan 14, 2025 at 12:26 AM Jeff Law wrote: > > > > On 1/11/25 4:45 PM, Vineet Gupta wrote: > > This seeming benign mistake caused a massive SPEC2017 Cactu regression > > (2.1 trillion insn to 2.5 trillion) wiping out all the gains from my > >

Re: [PATCH V4 0/2] RISC-V: Add intrinsics support and testcases for SiFive Xsfvcp extension.

Could you rebase and send the patch set again? I can't apply the patch set: [kitoc@hsinchu18 gcc]$ git am /tmp/git-pw8sm7zbop/RISC-V-Add-intrinsics-support-and-testcases-for-SiFive-Xsfvcp-extension..patch Applying: RISC-V: Add intrinsics support for SiFive Xsfvcp extensions. error: patch failed: g

Re: [PATCH] riscv: add mising masking in lrsc expander (PR118137)

LGTM Patrick O'Neill 於 2025年1月8日 週三 00:12 寫道： > > On 1/7/25 07:37, Andreas Schwab wrote: > > gcc: > > PR target/118137 > > * config/riscv/sync.md ("lrsc_atomic_exchange"): Apply mask > > to shifted value. > > > > gcc/testsuite: > > PR target/118137 > > * gcc.dg/atom

[PATCH v4] RISC-V: Fix code gen for reduction with length 0 [PR118182]

`.MASK_LEN_FOLD_LEFT_PLUS`(or `mask_len_fold_left_plus_m`) is expecting the return value will be the start value even if the length is 0. However current code gen in RISC-V backend is not meet that semantic, it will result a random garbage value if length is 0. Let example by current code gen for

Re: [PATCH v3] RISC-V: Fix code gen for reduction with length 0 [PR118182]

I have a few more thoughts during the vacation: we don't really need those fixes (work around for VL=0) *IF* we know the VL is constant or VLMAX, and that the situation for out-loop reduction, the only thing we need to fix is the in-loop reduction, that should be the only case will affected. On Fr

Re: [PATCH] RISC-V: Move fortran testcase to gfortran.target

Committed to trunk :) On Mon, Dec 23, 2024 at 9:28 PM Kito Cheng wrote: > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/fortran/pr111395.f90: Move this file to... > * gfortran.target/riscv/rvv/pr111395.f90: ...here. > * gcc.target/riscv/rvv/fo

Re: [PATCH v2] RISC-V: Fix code gen for reduction with length 0 [PR118182]

sorry for my stupid mistake, forgot v2, it's just same as v1 and see v3 On Mon, Dec 23, 2024 at 11:15 PM Kito Cheng wrote: > > --- > gcc/config/riscv/autovec-opt.md | 16 ++-- > gcc/config/riscv/autovec.md | 30 +++ > gcc/config/riscv/riscv-v.cc

[PATCH v3] RISC-V: Fix code gen for reduction with length 0 [PR118182]

`.MASK_LEN_FOLD_LEFT_PLUS`(or `mask_len_fold_left_plus_m`) is expecting the return value will be the start value even if the length is 0. However current code gen in RISC-V backend is not meet that semantic, it will result a random garbage value if length is 0. Let example by current code gen for

[PATCH v2] RISC-V: Fix code gen for reduction with length 0 [PR118182]

--- gcc/config/riscv/autovec-opt.md | 16 ++-- gcc/config/riscv/autovec.md | 30 +++ gcc/config/riscv/riscv-v.cc | 4 +- gcc/config/riscv/vector-iterators.md | 46 +++ gcc/config/riscv/vector.md | 118 +++ 5 files changed, 1

Re: [PATCH] RISC-V: Fix code gen for reduction with length 0 [PR118182]

Oh and I realized I send wrong version which didn't contain the changelog, test case and the description, let me send the v2 first On Mon, Dec 23, 2024 at 11:05 PM Kito Cheng wrote: > > On Mon, Dec 23, 2024 at 10:35 PM Robin Dapp wrote: > > > > > +;; Integer Reducti

Re: [PATCH] RISC-V: Fix code gen for reduction with length 0 [PR118182]

On Mon, Dec 23, 2024 at 10:35 PM Robin Dapp wrote: > > > +;; Integer Reduction (vred(sum|maxu|max|minu|min|and|or|xor).vs), but for > > auto vectorizer > > +(define_insn "@pred_av_" > > + [(set (match_operand: 0 "register_operand" "=vr") > > + (unspec: > > + [(unspec: > >

[PATCH] RISC-V: Fix code gen for reduction with length 0 [PR118182]

--- gcc/config/riscv/autovec-opt.md | 16 ++-- gcc/config/riscv/autovec.md | 30 +++ gcc/config/riscv/riscv-v.cc | 4 +- gcc/config/riscv/vector-iterators.md | 46 +++ gcc/config/riscv/vector.md | 118 +++ 5 files changed, 1

[PATCH] RISC-V: Move fortran testcase to gfortran.target

gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/fortran/pr111395.f90: Move this file to... * gfortran.target/riscv/rvv/pr111395.f90: ...here. * gcc.target/riscv/rvv/fortran/pr111566.f90: Move this file to... * gfortran.target/riscv/rvv/pr111566.f90: ...here.

Re: [RFC PATCH v2] RISC-V:Fix th.vsetvli generates from vext_x_v with wrong operand

On Mon, Dec 23, 2024 at 2:52 PM wrote: > > From: Yunze Zhu > > Fix a bug th.vsetvli generates from vext_x_v with an imm operand, > which reports illegal operand. This patch fix this by replacing > imm operand with reg operand in th.vsetvli. > > gcc/ChangeLog: > > * config/riscv/riscv-vset

Re: [PATCH] RISC-V: List valid -mtune options only once

LGTM Christoph Müllner 於 2024年12月20日 週五 04:13 寫道： > This patch ensures that the list of valid -mtune options > does not contain entries more than once. > The -mtune option accepts CPU identifiers as well as > tuning identifiers and there are cases where a CPU and > its tuning have the same ident

Re: [PATCH 2/2] RISC-V: Add intrinsic testcases for SiFive Xsfvcp extensions.

Could you reduce the test files? just one test for each instruction is fine, you don't need to put all tests into gcc source tree. e.g. only pick test_sf_vc_v_xvw_u8mf4 and test_sf_vc_v_xvw_se_u16m4 for sf.vc.v.xvw

Re: [PATCH 1/2] RISC-V: Add intrinsics support for SiFive Xsfvcp extensions.

> diff --git a/gcc/config/riscv/genrvv-type-indexer.cc > b/gcc/config/riscv/genrvv-type-indexer.cc > index a2974269adc..e3b845d156e 100644 > --- a/gcc/config/riscv/genrvv-type-indexer.cc > +++ b/gcc/config/riscv/genrvv-type-indexer.cc > @@ -303,6 +303,8 @@ main (int argc, const char **argv) >

Re: [PATCH 0/5] New Asm Constraints and Modifiers - RVC, Raw Encodings, Pairs

On Sun, Dec 15, 2024 at 1:31 AM Jeff Law wrote: > > > > On 12/9/24 1:56 AM, Kito Cheng wrote: > > This patch set implements the proposal from riscv-c-api-doc[1]. > > It adds two constraints and one modifier with the goal of improving the user > > experience for `.ins

Re: [PATCH] RISC-V: Support for zilsd and zclsd extensions.

On Mon, Dec 16, 2024 at 10:58 PM Dongyan Chen wrote: > > This patch support zilsd and zclsd[1] extensions. > To enable GCC to recognize and process zilsd and zclsd extension correctly at > compile time. > > [1] https://github.com/riscv/riscv-zilsd > > gcc/ChangeLog: > > * common/config/ri

[PATCH v2 5/5] RISC-V: Add new constraint R for register even-odd pairs

Although this constraint is not currently used for any instructions, it is very useful for custom instructions. Additionally, some new standard extensions (not yet upstream), such as `Zilsd` and `Zclsd`, are potential users of this constraint. Therefore, I believe there is sufficient justification

[PATCH v2 4/5] RISC-V: Implment N modifier for printing the register number rather than the register name

The modifier `N`, to print the raw encoding of a register. This is used when using `.insn , `, where the user wants to pass a value to the instruction in a known register, but where the instruction doesn't follow the existing instruction formats, so the assembly parser is not expecting a register n

[PATCH v2 3/5] RISC-V: Rename internal operand modifier N to n

Here is a purposal that using N for printing register encoding number, so let rename the existing internal operand modifier `N` to `n`. gcc/ChangeLog: * config/riscv/corev.md (*cv_branch): Update modifier. (*branch): Ditto. * config/riscv/riscv.cc (riscv_print_operand): Up

[PATCH v2 2/5] RISC-V: Add cr and cf constraint

gcc/ChangeLog: * config/riscv/constraints.md (cr): New. (cf): New. * config/riscv/riscv.h (reg_class): Add RVC_GR_REGS and RVC_FP_REGS. (REG_CLASS_NAMES): Ditto. (REG_CLASS_CONTENTS): Ditto. * doc/md.texi: Document cr and cf constraint.

[PATCH v2 1/5] RISC-V: Rename constraint c0* to k0*

Rename those constraint since we want define other constraint start with `c`, those constraints are internal and undocumented, so it's fine to rename. gcc/ChangeLog: * config/riscv/constraints.md (c01): Rename to... (k01): ...this. (c02): Rename to... (k02): ...thi

[PATCH v2 0/5] New Asm Constraints and Modifiers - RVC, Raw Encodings, Pairs

] https://github.com/riscv-non-isa/riscv-c-api-doc/pull/92 Changes in v2: - Adjsut riscv_regno_to_class, riscv_secondary_memory_needed and riscv_register_move_cost for new register class, also I've make sure the cost model isn't change. Kito Cheng (5): RISC-V: Rename constraint

Re: [PATCH V2] RISC-V: Update Xsfvqmacc and Xsfvfnrclip extension's testcases.

> diff --git > a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vfnrclip_x_f_qf.c > b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vfnrclip_x_f_qf.c > index 813f7860f645..3b46505e8f99 100644 > --- a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vfnrclip_x_f_qf.c > +++ b/gcc/testsuite/gcc.ta

Re: [PATCH 0/3] testsuite: RISC-V: Improve support for RV32E

Oh i just saw other part before i saw cover letter, anyway， LGTM for this patch set, thanks :) Dimitar Dimitrov 於 2024年12月10日 週二 00:16 寫道： > Many test cases implicitly require some form of I ABI variant for > RISC-V to be the default. Hence they fail when ILP32E is configured as > the default A

Re: [PATCH 5/5] RISC-V: Add new constraint R for register even-odd pairs

Apparently I forgot to attach the testcase, will put in v2 or put it when committing to the trunk. On Mon, Dec 9, 2024 at 5:06 PM Kito Cheng wrote: > > Although this constraint is not currently used for any instructions, it is > very > useful for custom instructions. Additional

[PATCH 5/5] RISC-V: Add new constraint R for register even-odd pairs

Although this constraint is not currently used for any instructions, it is very useful for custom instructions. Additionally, some new standard extensions (not yet upstream), such as `Zilsd` and `Zclsd`, are potential users of this constraint. Therefore, I believe there is sufficient justification

[PATCH 4/5] RISC-V: Implment N modifier for printing the register number rather than the register name

The modifier `N`, to print the raw encoding of a register. This is used when using `.insn , `, where the user wants to pass a value to the instruction in a known register, but where the instruction doesn't follow the existing instruction formats, so the assembly parser is not expecting a register n

[PATCH 2/5] RISC-V: Add cr and cf constraint

gcc/ChangeLog: * config/riscv/constraints.md (cr): New. (cf): New. * config/riscv/riscv.h (reg_class): Add RVC_GR_REGS and RVC_FP_REGS. (REG_CLASS_NAMES): Ditto. (REG_CLASS_CONTENTS): Ditto. * doc/md.texi: Document cr and cf constraint. gcc/

[PATCH 3/5] RISC-V Rename internal operand modifier N to n

Here is a purposal that using N for printing register encoding number, so let rename the existing internal operand modifier `N` to `n`. gcc/ChangeLog: * config/riscv/corev.md (*cv_branch): Update modifier. (*branch): Ditto. * config/riscv/riscv.cc (riscv_print_operand): Up

[PATCH 1/5] RISC-V: Rename constraint c0* to k0*

Rename those constraint since we want define other constraint start with `c`, those constraints are internal and undocumented, so it's fine to rename. gcc/ChangeLog: * config/riscv/constraints.md (c01): Rename to... (k01): ...this. (c02): Rename to... (k02): ...thi

[PATCH 0/5] New Asm Constraints and Modifiers - RVC, Raw Encodings, Pairs

] https://github.com/riscv-non-isa/riscv-c-api-doc/pull/92 Kito Cheng (5): RISC-V: Rename constraint c0* to k0* RISC-V: Add cr and cf constraint RISC-V Rename internal operand modifier N to n RISC-V: Implment N modifier for printing the register number rather than the register name RISC

Re: [PATCH v1 1/6] RISC-V: Refine unsigned vector SAT_ADD testcase dump check to tree optimized

This patch series is LGTM :) On Sun, Dec 8, 2024 at 8:01 PM wrote: > > From: Pan Li > > The sat alu related testcase check the rtl dump for the standard name > like .SAT_ADD exist or not. But the rtl pass expand is somehow > impressionable by the middle-end change or debug information. Like >

Re: [PATCH v1] RISC-V: Fix incorrect optimization options passing to partial

ok On Mon, Dec 9, 2024 at 2:13 PM wrote: > > From: Pan Li > > Like the strided load/store, the testcases of vector partial > are designed to pick up different sorts of optimization options but > actually these option are ignored according to the Execution log of > the gcc.log. > > This patch wou

Re: [committed] RISC-V: Add const to function_shape::get_name [NFC]

Thanks for notifying me that, I just reverted that first and will investigate next week :) On Sat, Dec 7, 2024 at 3:30 AM Mark Wielaard wrote: > > Hi Kito, > > On Thu, Dec 05, 2024 at 03:12:03PM +0800, Kito Cheng wrote: > > function_shape::get_name is the funciton for building

Re: [PATCH v3] RISC-V: Add --with-cmodel configure option

committee to trunk On Thu, Dec 5, 2024 at 2:59 PM Kito Cheng wrote: > > From: Hau Hsu > > Sometimes we want to use default cmodel other than medlow. Add a GCC > configure option for that. > > gcc/ChangeLog: > > * config.gcc (riscv*-*-*): Add support for --with

[committed] RISC-V: Add const to function_shape::get_name [NFC]

function_shape::get_name is the funciton for building intrinsic function name, the result should not be changed by others once it built. So add const to the return type to make sure no one change that by accident. gcc/ChangeLog: * config/riscv/riscv-vector-builtins-shapes.cc (vset

[PATCH v3] RISC-V: Add --with-cmodel configure option

(TARGET_DEFAULT_CMODEL): Remove. * doc/install.texi: Document --with-cmodel configure option. * doc/invoke.texi (-mcmodel): Mention --with-cmodel configure option. Co-authored-by: Kito Cheng --- v3: I've confirmed the v2 of this patch will break all other target's build, and I've

Re: [PATCH v1] RISC-V: Add assert for insn operand out of range access [PR117878][NFC]

LGTM On Wed, Dec 4, 2024 at 4:31 PM wrote: > > From: Pan Li > > According to the the initial analysis of PR117878, the ice comes from > the out-of-range operand access for recog_data.operand[]. Thus, add > one assert here to expose this explicitly. > > PR target/117878 > > gcc/ChangeLog

Re: [PATCH v2] RISC-V: Add --with-cmodel configure option

Let you know I am working on that and will send the v3 patch soon, also I have tested that on aarch64 from cfram. On Mon, Aug 26, 2024 at 12:40 AM Jeff Law wrote: > > > > On 8/4/24 8:24 PM, Hau Hsu wrote: > > Oh the Palmer's patch is here > > [PATCH] RISC-V: Add --with-cmodel configure-time argum

Re: [PATCH v1] RISC-V: Fix incorrect optimization options passing to reduc and ternop

lgtm On Tue, Dec 3, 2024 at 2:13 PM wrote: > > From: Pan Li > > Like the strided load/store, the testcases of vector reduce and ternop > are designed to pick up different sorts of optimization options but > actually these option are ignored according to the Execution log of > the gcc.log. > > Th

Re: [PATCH v1] RISC-V: Fix incorrect optimization options passing to cond and builtin

LGTM 於 2024年12月2日 週一 22:25 寫道： > From: Pan Li > > Like the strided load/store, the testcases of vector cond and builtin are > designed to pick up different sorts of optimization options but actually > these option are ignored according to the Execution log of gcc.log. > This patch would like to

Re: [PATCH 0/2] RISC-V: Add intrinsics support and testcases for SiFive Xsfvfnrclipxfqf extension.

LGTM, committed to trunk :) On Mon, Dec 2, 2024 at 9:33 AM wrote: > > From: yulong > > This patch implements the Sifvie vendor extension Xsfvfnrclipxfqf[1] > support to gcc. Providing support for FP32-to-int8 Ranged Clip > instrctions. > > [1] https://www.sifive.com/document-file/fp32-to-int8-

Re: [PATCH] riscv: Avoid narrowing warning

LGTM, thanks :) On Mon, Dec 2, 2024 at 6:00 PM Andreas Schwab wrote: > > * config/riscv/riscv.cc (fli_value_hf, fli_value_sf) > (fli_value_df): Use integer constants. Constify. > (riscv_float_const_rtx_index_for_fli): Add const. > --- > gcc/config/riscv/riscv.cc | 64 +++

Re: [PATCH 1/2] RISC-V: Add intrinsics support for SiFive Xsfvqmaccqoq/dod extensions.

Oh, I saw the second patch is just adding testcase, I think all comments are minor, so no need v2, I will address those minor change and commit after verified on my hand :) On Thu, Nov 28, 2024 at 2:52 PM Kito Cheng wrote: > > I incline to just keep sifive-vector, it although actually

Re: [PATCH 1/2] RISC-V: Add intrinsics support for SiFive Xsfvqmaccqoq/dod extensions.

ssume we just need one more version :) On Thu, Nov 28, 2024 at 10:39 AM wrote: > > From: yulong > > This commit adds intrinsics support for Xsfvqmaccqoq/dod. > > Co-Authored by: Kito Cheng > Co-Authored by: Monk Chiang Drop me and Monk, we aren't really involved in t

Re: [RFC][PATCH] RISC-V: Support TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN

Do you mind creating a PR to https://github.com/riscv/riscv-elf-psabi-doc/pull/ to start the discussion? I believe this should be documented somewhere since it should be consistent between LLVM and GCC. On Mon, Nov 4, 2024 at 2:26 PM Zhijin Zeng wrote: > > I can't find the vector function name ma

Re: [PATCH 4/4] RISC-V: Add -fcf-protection=[full|branch|return] to enable zicfiss, zicfilp.

I guess this should also adjust the testcase as well? On Fri, Nov 15, 2024 at 6:55 PM Monk Chiang wrote: > > gcc/ChangeLog: > * gcc/config/riscv/riscv.cc > (is_zicfilp_p): New function. > (is_zicfiss_p): New function. > * gcc/config/riscv/riscv-zicfilp.cc: Upd

Re: [PATCH 2/2] RISC-V: Use dynamic shadow offset

committed :) On Wed, Nov 20, 2024 at 3:26 AM Jeff Law wrote: > > > > On 11/14/24 9:14 PM, Kito Cheng wrote: > > Switch to dynamic offset so that we can support Sv39, Sv48, and Sv57 at > > the same time without building multiple libasan versions! > > > > [

Re: [PATCH 1/2] asan: Support dynamic shadow offset

Committed with changelog update and minor tweak (move RISC-V bits to second patch) On Wed, Nov 20, 2024 at 4:18 AM Jeff Law wrote: > > > > On 11/14/24 9:14 PM, Kito Cheng wrote: > > AddressSanitizer has supported dynamic shadow offsets since 2016[1], but > > GCC has

Re: [PATCH v3] RISC-V: Minimal support for svvptc extension.

LGTM, will commit to trunk once I pass the local test :) On Fri, Nov 22, 2024 at 1:15 PM Dongyan Chen wrote: > > This patch support svvptc extension[1]. > To enable GCC to recognize and process svvptc extension correctly at compile > time. > > [1] https://github.com/riscv/riscv-svvptc > > gcc/Ch

Re: [PATCH v2] RISC-V: Minimal support for svvptc extension.

Hi Dongyan: Thanks for your patch, it seems good but just a few minor comments :) > @@ -1721,6 +1722,9 @@ static const riscv_ext_flag_table_t > riscv_ext_flag_table[] = >RISCV_EXT_FLAG_ENTRY ("svinval", x_riscv_sv_subext, MASK_SVINVAL), >RISCV_EXT_FLAG_ENTRY ("svnapot", x_riscv_sv_subext

Re: [PATCH V1] RISC-V: Add the mini support for SiFive extensions.

Thanks, committed to trunk :) On Wed, Nov 20, 2024 at 2:09 AM Jeff Law wrote: > > > > On 11/17/24 2:55 AM, shiyul...@iscas.ac.cn wrote: > > From: yulong > > > > This patch add the mini support for xsfvqmaccqoq, xsfvqmaccdod and > > xsfvfnrclipxfqf extensions. > > > > gcc/ChangeLog: > > > >

[PATCH 2/2] RISC-V: Use dynamic shadow offset

Switch to dynamic offset so that we can support Sv39, Sv48, and Sv57 at the same time without building multiple libasan versions! [1] https://github.com/llvm/llvm-project/commit/da0c8b275564f814a53a5c19497669ae2d99538d gcc/ChangeLog: * config/riscv/riscv.cc (riscv_asan_shadow_offset): U

[PATCH 1/2] asan: Support dynamic shadow offset

AddressSanitizer has supported dynamic shadow offsets since 2016[1], but GCC hasn't implemented this yet because targets using dynamic shadow offsets, such as Fuchsia and iOS, are mostly unsupported in GCC. However, RISC-V 64 switched to dynamic shadow offsets this year[2] because virtual memory s

Re: [PATCH v1] RISC-V: Rearrange the test files for scalar SAT_ADD [NFC]

r patch for this. > > Pan > > -Original Message- > From: Kito Cheng > Sent: Thursday, November 14, 2024 3:22 PM > To: 钟居哲 > Cc: Li, Pan2 ; gcc-patches ; > jeffreyalaw ; Robin Dapp > Subject: Re: [PATCH v1] RISC-V: Rearrange the test files for scalar SAT_ADD &

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