> 1. Change the name of the option from:
>
> -fdiagnostic-try-to-explain-harder
> To
> -fdiagnostic-explain-harder
I can think of a lot of connotations for this name, but alas, they are
unfortunate, off-topic, or both.
Some more neutral ideas:
-fdiagnostics-verbose
-fdiagnostic-details
Or maybe
On Thu, 30 Nov 2023 at 17:53, Jeff Law wrote:
> > * ext-dce.c: Fixes for carry handling.
> >
> > * ext-dce.c (safe_for_live_propagation): Handle MINUS.
> >(ext_dce_process_uses): Break out carry handling into ..
> >(carry_backpropagate): This new function.
> >Bet
I originally computed mmask in carry_backpropagate from XEXP (x, 0),
but abandoned that when I realized we also get called for RTX_OBJ
things. I forgot to adjust the SIGN_EXTEND code, though. Fixed
in the attached revised patch. Also made sure to not make inputs
of LSHIFTRT / ASHIFTRT live if t
On Wed, 29 Nov 2023 at 20:05, Joern Rennecke
wrote:
> > I suspect it'd be more useful to add handling of LSHIFTRT and ASHIFTRT
> > . Some ports do
> > a lot of static shifting.
>
> > +case SS_ASHIFT:
> > +case US_ASHIFT:
> > +
On Wed, 29 Nov 2023 at 19:57, Joern Rennecke
wrote:
>
> Attached is what I have for carry_backpropagate .
>
> The utility of special handling for SS_ASHIFT / US_ASHIFT seems
> somewhat marginal.
>
> I suspect it'd be more useful to add handling of LSHIFTRT and ASHIFTRT
5ef9c
Author: Joern Rennecke
Date: Wed Nov 29 18:46:06 2023 +
* ext-dce.c: Fixes for carry handling.
* ext-dce.c (safe_for_live_propagation): Handle MINUS.
(ext_dce_process_uses): Break out carry handling into ..
(carry_backpropagate): This new function.
B
Why did you leave out MINUS from safe_for_live_propagation ?
On Tue, 28 Nov 2023 at 13:36, Joern Rennecke
wrote:
> For the saturating truncation operations, we have the high-to-low
propagation,
> but no low-to-high propagation, so that would be something separate to model.
P.S.:
For unsigned saturating truncation, the propagation from higher to
On Mon, 27 Nov 2023 at 20:18, Jeff Law wrote:
>
>
>
> On 11/27/23 13:03, Richard Sandiford wrote:
> > Joern Rennecke writes:
> >> On 11/20/23 11:26, Richard Sandiford wrote:
> >>>> + /* ?!? What is the point of this adjustment to DST_MASK?
On Mon, 27 Nov 2023 at 20:03, Richard Sandiford
wrote:
>
> Joern Rennecke writes:
> > On 11/20/23 11:26, Richard Sandiford wrote:
> >>> + /* ?!? What is the point of this adjustment to DST_MASK? */
> >>> + if (code == PLUS || code == MINUS
> &
You are applying PATTERN to an INSN_LIST.
diff --git a/gcc/ext-dce.cc b/gcc/ext-dce.cc
index 52032b50951..4523654538c 100644
--- a/gcc/ext-dce.cc
+++ b/gcc/ext-dce.cc
@@ -122,10 +122,9 @@ safe_for_live_propagation (rtx_code code)
optimziation phase during use handling will be. */
static voi
On 11/20/23 11:26, Richard Sandiford wrote:
>> + /* ?!? What is the point of this adjustment to DST_MASK? */
>> + if (code == PLUS || code == MINUS
>> + || code == MULT || code == ASHIFT)
>> + dst_mask
>> + = dst_mask ? ((2ULL << floor_log2 (dst_mask)) - 1) : 0;
>
> Yeah, sympathise w
On 11/20/23 11:26, Richard Sandiford wrote:
>> +
>> + mask = GET_MODE_MASK (GET_MODE (SUBREG_REG (x))) << bit;
>> + if (!mask)
>> + mask = -0x1ULL;
>
> Not sure I follow this. What does the -0x1ULL constant indicate?
> Also, isn't it the mask of the outer register that i
sh-elf
Add support for XCVhwlp extension in CV32E40P
2023-11-18 Joern Rennecke
gcc/
* common/config/riscv/riscv-common.cc (riscv_ext_version_table):
Add xcvhwlp.
(riscv_ext_flag_table): Likewise.
* config.gcc (riscv*): Add corev.o to extra_objs.
* co
aram=riscv-autovec-preference=scalable
riscv-sim/-march=rv64imac/-mabi=lp64
2023-11-08 Joern Rennecke
gcc/testsuite/
* lib/scanasm.exp (scan-assembler-times): Disregard LTO sections.
(scan-assembler-dem, scan-assembler-dem-not): Likewise.
(dg-scan): Likewise, if nam
On Wed, 11 Oct 2023 at 05:48, Joern Rennecke
wrote:
> So I propose we look at the first character of the regexp, and if it's neither
> ^ nor \ (neither caret nor backslash), we consider the regexp un-anchored,
> and prepend ^[^"]* , so it won't allow a match after a doubl
On Sat, 30 Sept 2023 at 22:12, Joern Rennecke
wrote:
> Also, we might have different directives for not scanning in LTO sections -
> or just ignoring .ascii . Or maybe the other way round - you have to do
> something special if you want to scan inside strings, and by default we
>
On Wed, 4 Oct 2023 at 18:38, Patrick O'Neill wrote:
>
> Hi Joern,
>
> I'm seeing new failures introduced by this patch
> (9464e72bcc9123b619215af8cfef491772a3ebd9).
>
> On rv64gcv:
> FAIL: gcc.dg/pr90263.c scan-assembler memcpy
My testing didn't flag this because I used elf targets. The
expected
Attached is the committed version.
commit 9464e72bcc9123b619215af8cfef491772a3ebd9
Author: Joern Rennecke
Date: Mon Oct 2 03:16:09 2023 +0100
cpymem for RISC-V with v extension
gcc/
* config/riscv/riscv-protos.h (riscv_vector::expand_block_move):
Declare.
* config/riscv/ri
Committed as obvious (RE doesn't compile without patch, and I know
what I meant when I wrote it).
commit 5f3da480e7541a9c29d655dccb2463fc5f3cf2c4
Author: Joern Rennecke
Date: Sun Oct 1 22:46:43 2023 +0100
Fix typo in add_options_for_riscv_v, add_options_for_risc
On Fri, 29 Sept 2023 at 14:54, Jeff Law wrote:
> So I recommend we go forward with Joern's approach (so consider that an
> ACK for the trunk). Joern can you post a follow-up manual twiddle so
> that other ports can follow your example and avoid this problem?
The manual... so not in the genera
ation of the alignment test for using scalars values
spanning multiple
addressable units.
Make riscv_vector::legitimize_move adjust SRC in the caller.
2023-09-29 Joern Rennecke
Juzhe-Zhong
PR target/111566
gcc/
* config/riscv/riscv-protos.h (riscv_vector::legit
On Wed, 27 Sept 2023 at 18:22, Jeff Law wrote:
> It would help to describe how these patterns were under specified so
> that folks don't continue to make the same mistake as new tests get added.
dg-final scan-assembler, scan-assembler-not, and scan-assembler-times
use a tcl regular expression (o
obvious.
commit d326bb6d7588425d013791299272f913fb23e56d
Author: Joern Rennecke
Date: Wed Sep 27 10:05:13 2023 +0100
Harden scan patterns with a bit of scripting:
$ egrep -r 'scan-assembler(|-not|-times) "[[:alnum:].]{1,7}"' riscv
$ egrep -rl 'sc
On Tue, 26 Sept 2023 at 14:18, Jeff Law wrote:
> But the Coremark code is what it is. This isn't a whole lot
> different than the work in the 90s which rewrote loops and compromised
> some of the spec benchmarks, or the eqntott hack to simplify that one
> key loop in eqntott.
I think the state
On Sun, 24 Sept 2023 at 12:41, Alexander Monakov wrote:
>
>
> On Sun, 24 Sep 2023, Joern Rennecke wrote:
>
> > It is a stated goal of coremark to test performance for CRC.
>
> I would expect a good CRC benchmark to print CRC throughput in
> bytes per cycle or megabytes
Mariam Harutyunyan:
+++ b/gcc/ChangeLog
@@ -1,3 +1,45 @@
+2023-08-03 Mariam Arutunian
+
It is common courtesy to include all authors in the list of authors
for the ChangeLog; also,
this may help people in the future understand the history of the code better.
While must of your patch is new, it
In the patch call we talked about sign extsnsion elimination, so I dug
up this patch set that I did a while ago. It is still lacking some
documentation and testing in a more recent base version;
I only adjusted the common.opt part context for the patch to apply.
Author: Joern Rennecke
Date
rength reduction of the opaque pattern version for -O3,
though. Would people also like to see that expanded into RTL? Or
should I just drop in the opaque pattern for that? Or not at all,
because everyone uses Superscalar Out-Of-Order execution?
commit 1f4b7a8e6798acab1f79de38e85d9d080a76eb4a
Autho
On Fri, 4 Aug 2023 at 21:52, Jeff Law wrote:
> > diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> > index b4884a30872..e61110fa3ad 100644
> > --- a/gcc/config/riscv/riscv-v.cc
> > +++ b/gcc/config/riscv/riscv-v.cc
> > @@ -49,6 +49,7 @@
> > #include "tm-constrs.h"
> > #
could still construe a multi-word option
that uses a string starting with -march as a pathname or similar, but I suppose
you'd deserve whatever you get then. I don't see a bobby tables scenario
here.)
I also found one comment pasto.
I have attached the amended patch - not tested yet.
ou can use check_effective_target_riscv_v_ok to
check if that's ok, and then
add_options_for_riscv_v to add the appropriate -march option.
Examples how this can be used can be found
athttps://github.com/embecosm/rvv-gcc/tree/rvv-12/gcc/testsuite
2023-04-17 Joern Rennecke
gcc/testsuite/
* lib/targ
p64d
riscv-sim/-march=rv64imafdcv_zicsr_zifencei_zfh_zba_zbb_zbs_zve32f_zve32x_zve64d_zve64f_zve64x_zvl128b_zvl32b_zvl64b/-mabi=lp64d
riscv-sim/-march=rv64imafdcv_zicsr_zifencei_zfh_zve32f_zve32x_zve64d_zve64f_zve64x_zvl128b_zvl32b_zvl64b/-mabi=lp64d
2023-07-12 Ju-Zhe Zhong
Committed as obvious.
commit 6bab2772dbc42ce7a1b29b03ae84e6e434e23c4e
Author: Joern Rennecke
Date: Tue Jul 18 04:28:55 2023 +0100
Tighten regexps in gcc.target/riscv/_Float16-zhinx-1.c .
The original "mv" regexp would match
.ascii "\254\254\375\002e2N6\013\
On Thu, 18 May 2023 at 16:37, Joern Rennecke wrote
in https://gcc.gnu.org/pipermail/gcc-patches/2023-May/618928.html :
>
> This breaks building libstdc++-v3 for
> -march=rv32imafdcv_zicsr_zifencei_zba_zbb_zbc_zbs_zve32f_zve32x_zve64d_zve64f_zve64x_zvl128b_zvl32b_zvl64b
> -mabi=ilp32f
On Wed, Jun 1, 2022 at 02:28:45 GMT 2022, zhongjuzhe
wrote:
> gcc/testsuite/ChangeLog:
>
>* gcc.target/riscv/rvv/intrinsic/vlex_2.c: New test.
These intrinsic test cases look like they have been machine generated. And if
they aren't, they probably should (have) be(en). I've been working
> and there needs to be code to actually expand the builtin using optabs.
> And something needs to be done to make match.pd work on the output.
Never mind that bit, that was just due to a function argument type mismatch
on the last argument of the crc built-in functions.
On Wed, 16 Mar 2022 at 08:15, Richard Biener wrote:
> The canonical place to transform loops into builtins would be loop
> distribution.
> Another place would be final value replacement since you basically replace
> the reduction result with a call to the builtin, but I think
> loop-distribution
On 15/03/2022, Richard Biener wrote:
> Why's this a new pass? Every walk over all insns costs time. The pass
> lacks any comments as to what CFG / stmt structure is matched. From
> a quick look it seems like it first(?) statically matches a stmt sequence
> without considering intermediate stmt
On 15/03/2022, Richard Biener wrote:
> Why's this a new pass? Every walk over all insns costs time.
If should typically scan considerably less than all the insns.
> The pass
> lacks any comments as to what CFG / stmt structure is matched.
I've put a file in:
config/riscv/tree-crc-doc.txt
wo
This misses some documentation and testing, but it appears to work
well with 64 bit RISC-V.
-fext-dce is best used with aggressive unrolling and/or inlining. It deletes
zero/sign extensiions where the part of the register that the
zero/sign extension
pertains to is dead.
This is not about multi-
On Tue, 15 Mar 2022 at 02:17, Oleg Endo wrote:
> > In my own CRC library I've got ~30 'commonly used' CRC types, based on
> the following generic definition:
> > This being a library makes it relatively easy to tune and customize for
> various systems.
...
> How would that work together with you
Oops, that was meant to go to the list too.
On Tue, 15 Mar 2022 at 01:04, Andrew Pinski wrote:
>
> On Mon, Mar 14, 2022 at 5:33 PM Joern Rennecke
> wrote:
> >
> > Most microprocessors have efficient ways to perform CRC operations, be
> > that with lookup table
n the
tree, we'll get more
contributions of suitable named patterns for various ports.
bootstrapped on x86_64-pc-linux-gnu .
2022-03-14 Jon Beniston
Joern Rennecke
* Makefile.in (OBJS): Add tree-crc.o .
* builtin-types.def (BT_FN_UINT16_UINT16_UINT8_CONS
ction didn't actually
return early (doing
things with an array of N elements where N might be zero... but it
isn't for the actual data).
Does someone have a benchmark / computing load where the early return
is beneficial? Or conversely, harmful?
2022-03-14 Joern Rennecke
* com
I find that when compiling some files, lra goes into an infinite loop
reloading constant
addresses. This patch allows them to just be recognized as matching addresses
immediately, which also saves a bit of space for a few other files.
Bootstrapped and regression tested on x86_64-pc-linux-gnu.
gcc
On Mon, 17 May 2021 at 11:59, Richard Biener wrote:
> The plan for reload is to axe it similar to CC0 support. Sooner than later,
> but
> give it's still used exclusively by a lot of target means it might
> take some time.
> So for you it's always just -fretry-compilation -m[no-]lra? Given -m
On Mon, 17 May 2021 at 08:36, Richard Biener wrote:
>
> On Sun, May 16, 2021 at 8:53 PM Joern Rennecke
> wrote:
> >
> > For architectures with likely spilled register classes, neither
> > register allocator is guaranteed
> > to succeed when using optimization.
of the error message and the recap of the number
of alternatives of operand 0.
So I propose the attached patch now.
Bootstrapped on x86_64-pc-linux-gnu.
2021-05-17 Joern Rennecke
Make "wrong number of alternatives" message more specific, and
remove assumption
64-pc-linux-gnu.
FWIW, we also have patches for cpplib / lexer / parser char and string
handling to make 8 -> 16 bit char cross-compiling work, but they can't
be ported forward easily because the parser has changed since gcc9.
2021-04-16 Joern Rennecke
* c-fami
retry, which is
implemented in the compiler driver.
Bootstrapped on x86_64-pc-linux-gnu.
2021-05-16 Joern Rennecke
* common.opt: New option -fretry-compilation=.
* gcc.c (execute): Implement -fretry-compilation.
* doc/invoke.texi: Document -fretry-compilation.
diff --git
Bootstrapped regtested and on x86_64-pc-linux-gnu.
2021-02-22 Joern Rennecke
lra fix to reduce fatal spill failures.
* lra-constraints.c (split_reg): No longer static.
* lra-int.h (split_reg): Declare.
* lra-assigns.c (lra_split_hard_reg_for): Add strategy
MATCH_SCRATCH in alter_predicate_for_insn.
This makes most sense together with the previous patch for MATCH_DUP support,
although the latter can also be used stand-alone, so have posted and
tested these
patches separately.
Bootstrapped on x86_64-pc-linux-gnu.
2020-12-12 Joern Rennecke
Fix
hat's
not only wrong, but can also
be impossible when the pattern should apply to multiple patterns with
different operand numbers.
The attached patch fixes this.
Bootstrapped on x86_64-pc-linux-gnu.
2020-12-12 Joern Rennecke
Fix match_dup bug of define_cond_exec.
* ge
e attached patch fixes this.
Bootstrapped on x86_64-pc-linux-gnu.
2020-12-12 Joern Rennecke
Fix match_dup bug of define_cond_exec.
* gensupport.c (alter_predicate_for_insn): Handle MATCH_DUP.
diff --git a/gcc/gensupport.c b/gcc/gensupport.c
index e1ca06dbc1e..92275358078 100644
e too many. By making genoutput tell you what the
argument counts are, this gets a little bit easier.
Bootstrapped on x86_64-pc-linux-gnu.
2021-01-13 Joern Rennecke
Make "wrong number of alternatives" message a bit more specific.
diff --git a/gcc/genoutput.c b/gcc/genoutput
Bootstrapped on x86_64-pc-linux-gnu.
2020-12-10 Joern Rennecke
Fix bug in the define_subst handling that made match_scratch unusable for
multi-alternative patterns.
diff --git a/gcc/gensupport.c b/gcc/gensupport.c
index e1ca06dbc1e..4022c661adb 100644
--- a/gcc/gensupport.c
+++ b/gcc
On Fri, 5 Apr 2019 at 11:07, Richard Sandiford
wrote:
> > 2019-04-04 Joern Rennecke
> >
> > * sched-deps.c (sched_macro_fuse_insns): Check return value of
> > targetm.fixed_condition_code_regs.
>
> OK, thanks.
Thanks for the review.
Is that OK
TARGET_FIXED_CONDITION_CODE_REGS
has the default value as defined in target.def (hook_bool_uintp_uintp_false).
The attached patch fixes this by checking the return value of
targetm.fixed_condition_code_regs. Bootstrapped & regtested on
x86_64-pc-linux-gnu .
2019-04-04 Joern Rennecke
* sched-de
I forgot the 'x' number base specifier in r216034.
Committed as obvious.
2014-11-09 Joern Rennecke
* config/avr/predicates.md (low_io_address_operand): Fix typo.
Index: config/avr/predicates.md
===
--- config/avr/pre
r.
By setting CPLUSPLUS_CPP_SPEC to "%(cpp)", we let the cc1plus
preprocessor look up the actual value of the preprocessor specs.
OK to apply?
2014-11-09 Joern Rennecke
* /config/avr/avr.h (CPLUSPLUS_CPP_SPEC): Define.
diff --git a/gcc/config/avr/avr.h b/gcc/config/avr/avr.
On 4 November 2014 14:24, James Greenhalgh wrote:
> On Tue, Nov 04, 2014 at 12:07:56PM +0000, Joern Rennecke wrote:
>> On 31 October 2014 15:10, James Greenhalgh wrote:
>>
>> > While I am there, arc defines a macro CAN_MOVE_BY_PIECES, which is
>> > unused, so cl
On 31 October 2014 15:10, James Greenhalgh wrote:
> While I am there, arc defines a macro CAN_MOVE_BY_PIECES, which is
> unused, so clean that up too.
That's not a clean-up. This pertains to PR 39350.
Which, incidentally, this hookization completely ignores, entrenching
the conflation of
move e
On 3 November 2014 14:33, Sivanupandi, Pitchumani
wrote:
> Hi,
>
> Unrecognized option error is issued by avr-gcc for devices with AVR_ISA_RMW.
> This is because of an incorrect spec string device spec generation.
>
> Below patch corrects the incorrect spec string in gen-avr-mmcu-specs.c.
> If OK,
On 25 October 2014 10:58, Richard Sandiford wrote:
> This is part of a series to remove uses of for_each_rtx from the ports.
>
> Tested by making sure there were no code changes for gcc.dg, gcc.c-torture
> and g++.dg for arc-elf. OK to install?
>
> Thanks,
> Richard
>
>
> gcc/
> * config/
On 25 October 2014 10:56, Richard Sandiford wrote:
> This is part of a series to remove uses of for_each_rtx from the ports.
>
> Tested by making sure there were no code changes for gcc.dg, gcc.c-torture
> and g++.dg for arc-elf. OK to install?
>
> Thanks,
> Richard
>
>
> gcc/
> * config/
On 25 October 2014 10:53, Richard Sandiford wrote:
...
> Tested by making sure there were no code changes for gcc.dg, gcc.c-torture
> and g++.dg for arc-elf. OK to install?
>
> Thanks,
> Richard
>
>
> gcc/
> * config/arc/arc.c: Include rtl-iter.h.
> (arc_rewrite_small_data_1): De
On 25 October 2014 10:54, Richard Sandiford wrote:
> This is part of a series to remove uses of for_each_rtx from the ports.
>
> Tested by making sure there were no code changes for gcc.dg, gcc.c-torture
> and g++.dg for arc-elf. OK to install?
OK.
On 21 October 2014 17:29, Jonathan Wakely wrote:
>> +typedef typeof (((tm*)0)->tm_sec) __tm_small_int;
>
>
> I think this should probably use __typeof__ to work with
> -Wpedantic-errors
Ok, makes sense, and it's a straightforward change.
>
>> +#else /* For 100% mangling compatibility, use int d
A couple of tests fail because an unqualified size_t is used.
2014-09-15 Joern Rennecke
* libstdc++-v3/testsuite/util/io/prog_bar.cc: Qualify size_t.
* libstdc++-v3/testsuite/util/io/prog_bar.hpp: Likewise.
* libstdc++-v3/testsuite/util/io/verified_cmd_line_input.hpp
We got a couple of tests that assume -frtti; this is the default for
most targets, but not for avr.
libstdc++-v3:
2013-09-24 Joern Rennecke
* testsuite/18_support/type_info/hash_code.cc (dg-options): Add -frtti.
* testsuite/20_util/shared_ptr/cons/unique_ptr_deleter_ref_2.cc
The gdb version check ends up trying to invoke gdb on the target -
not so nice if your target is too small to accomodate gdb in the first place.
I've added a check similar to the one in gdb-test to punt on non-native
targets.
libstdc++-v3:
2013-09-17 Joern Rennecke
* testsuite/li
libstdc++-v3:
2013-06-14 Joern Rennecke
* include/bits/locale_facets_nonio.h (__tm_small_int): typedef/define.
(_M_extract_num): Templatize base type of __member argument.
(_M_extract_name): Change type of __member argument to __tm_small_int&.
* include/
libstdc++-v3:
2013-06-14 Joern Rennecke
* configure.ac [avr-*-*]: Don't use AC_LIBTOOL_DLOPEN.
* crossconfig.m4: Add avr-*-* settings.
* configure: Regenerate.
Index: configure.ac
===
--- configu
gcc:
2014-09-23 Joern Rennecke
* config/avr/avr.h (LIBSTDCXX): Don't define.
* config/avr/avr.c (TARGET_UNWIND_WORD_MODE): Define.
(avr_unwind_word_mode): New function.
* config/avr/avr.c (avr_asm_function_rodata_section):
When merging something
On 21 October 2014 16:35, Joern Rennecke wrote:
> Make can't 'build' check-c++ without rules for check-target-libgomp-c++ /
> check-target-libitm-c++
>
> This patch makes sure that there's at least a dummy rule available.
Sorry - forgot to attach the patch - h
Make can't 'build' check-c++ without rules for check-target-libgomp-c++ /
check-target-libitm-c++
This patch makes sure that there's at least a dummy rule available.
On 13 October 2014 20:43, Jeff Law wrote:
...
> I think you want "smode" in the mode_for_size call rather than "mode", right
> (both instances)?
No, nregs is the number of hard registers of regno in "mode". Hence
we must use the
size of "mode".
How to choose the mode class is not so clear-cut.
an
think of arguments for or against, but got no
concrete examples for either.
2014-10-11 Joern Rennecke
Jeff Law
* caller-save.c (replace_reg_with_saved_mem): If saved_mode covers
multiple hard registers, use word_mode.
diff --git a/gcc/caller-save.c b/gcc/caller-s
l/gcc-patches/2014-10/msg00420.html ,
as avr-libc won't build otherwise.
2014-10-08 Joern Rennecke
* config/avr/avr.opt (mmcu=): Change to have a string value.
(mn-flash=, mskip-bug, march=, mrmw): New options.
(HeaderInclude): New.
(mmcu=): Remove Var / In
On 8 October 2014 12:02, Richard Biener wrote:
...
> - if (POINTER_TYPE_P (TREE_TYPE (exp)))
> - as = TYPE_ADDR_SPACE (TREE_TYPE (TREE_TYPE (exp)));
> - else
> - as = ADDR_SPACE_GENERIC;
> -
> + as = TYPE_ADDR_SPACE (TREE_TYPE (TREE_TYPE (TREE_OPERAND (exp, 0;
>
Trying to build avr2 strftime of avr-libc ICEs as we are trying to
convert a PSImode address to HImode. There is no reason to
do this conversion in the first place - it is a case of failing to recognize
the proper address space.
The attached patch fixes this.
Bootstrapped on i686-pc-linux-gnu.
On 7 October 2014 18:38, Jeff Law wrote:
> On 10/06/14 20:57, Joern Rennecke wrote:
>>
>> On 6 October 2014 19:58, Jeff Law wrote:
>>>
>>> What makes word_mode special here? ie, why is special casing for
>>> word_mode
>>> the right thing to do?
On 6 October 2014 19:58, Jeff Law wrote:
> What makes word_mode special here? ie, why is special casing for word_mode
> the right thing to do?
The patch does not special-case word mode. The if condition tests if
smode would
cover multiple hard registers.
If that would be the case, smode is repl
Investigating an ICE while trying to compile libgcc2.c:__udivmoddi4 for
a new avr variant with different register set/allocation order, I found
replace_reg_with_saved_mem falling over its own nonsense. The instruction:
(debug_insn 97 96 98 2 (var_location:SI __x2 (mult:SI (lshiftrt:SI
(reg/v:SI 1
I've changed the heading to "ARC" and put the item in its
proper alpha-sorted position to make it easier to find.
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Description: Binary data
As ARC maintainer, I have applied the appended patch to changes.html.
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Description: Binary data
On 2 June 2014 13:34, Christian Bruel wrote:
> Hello,
>
> Any feedback for this ? I'd like to commit only when OK for Epiphany.
>> Joern, is this new target macro interface OK with you ?
Yes, this interface should allow me to do switches between rounding
and truncating
floating-point modes with
On 13 May 2014 22:41, Oleg Endo wrote:
> Right. I was thinking to add FPSCR.SZ mode switching to SH, in order to
> do float vector moves. For that SZ and PR need to be switched both at
> the same time (only SH4A has both, fpchg and fschg). So basically I'd
> add another mode entity, which woul
On 12 May 2014 23:39, Oleg Endo wrote:
> This is the same as changing/setting the FP modes (PR, SZ) on SH while
> preserving the other FPSCR bits, or did I miss something?
It's more like if you have to control multiple bits at once to get a
specific mode.
Say you have to turn SZ off and PR on.
On 12 May 2014 13:51, Joern Rennecke wrote:
> On 12 May 2014 13:16, Christian Bruel wrote:
>
>> Just for my curiosity, which other targets have multi-way toggling
>> support ?
>
> The epiphany has, sort of: you read a control register, AND and/or OR
> some mask(s) t
On 12 May 2014 13:16, Christian Bruel wrote:
> Just for my curiosity, which other targets have multi-way toggling
> support ?
The epiphany has, sort of: you read a control register, AND and/or OR
some mask(s) to the value,
and write it back.
If we knew the previous mode, we might elide and AND o
On 12 May 2014 10:06, Christian Bruel wrote:
> Just saw the Jeff's approval for the RTL part. Sorry for the crossed answers
>
> remains the target maintainers. Joern, Kaz ?
>
> Many thanks.
>
> Christian
>
> On 05/12/2014 10:44 AM, Christian Bruel wrote:
>> Hello,
>>
>> I'd still wish to ping for
On 2 April 2014 17:34, Joern Rennecke wrote:
> Hmm, the sanity check in new_seginfo caused a boostrap failure
> building libjava on x86.
> There was a block with CODE_LABEL as basic block head, otherwise empty.
I've added the testcase - and a bit more detail on this issue - in
Hmm, the sanity check in new_seginfo caused a boostrap failure
building libjava on x86.
There was a block with CODE_LABEL as basic block head, otherwise empty.
3. add a comment above the trick in optimize_mode_switching saying that it
> is both required to implement the FIFO insertion and valid because we know
> that the basic block was initially empty.
Done.
> It's not clear to me whether this is a regression or not, so you'll also
On 26 March 2014 12:35, Joern Rennecke wrote:
> bootstrapped on i686-pc-linux-gnu, regtest in progress.
Passed now.
On 26 March 2014 08:15, Eric Botcazou wrote:
>> As described in the PR, this patch fixes a wrong-code bug by making the
>> order of emitted mode switching instructions more consistet & predictable.
>
> I don't understand this change (but I'm not a specialist of mode switching):
> currently the mod
As described in the PR, this patch fixes a wrong-code bug by making the order of
emitted mode switching instructions more consistet & predictable.
Bootstrapped / regtested on i686-pc-linux-gnu.
tmp
Description: Binary data
I've been looking how to make the precompiled header mechanism allow
me to use the
ARC -misize option (which outputs additional information about gcc's
idea of instruction
addresses for the purpose of branch shortening, to help debugging the
latter) in a
compilation involving precompiled headers.
I
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