[PATCH,committed] [MAINTAINERS] Update email address

Hi, Updating my email address in the MAINTAINERS file. Thanks, Naveen Index: ChangeLog === --- ChangeLog (revision 263324) +++ ChangeLog (working copy) @@ -1,3 +1,7 @@ +2018-08-06 Naveen H.S + + * MAINTAINERS: Update my email addr

Re: [PING] [PATCH] [AArch64] Add addr_type attribute

Hi, Please consider this as a personal reminder to review the patch at following link and let me know your comments on the same. https://gcc.gnu.org/ml/gcc-patches/2017-07/msg01634.html Thanks, Naveen

Re: [PING] [PATCH] [AArch64] vec_pack_trunc_ should split after register allocator

Hi,   Please consider this as a personal reminder to review the patch at following link and let me know your comments on the same.   https://gcc.gnu.org/ml/gcc-patches/2017-07/msg01529.html Thanks, Naveen

[PING 5] [PATCH][AArch64] Add neon_pairwise_add & neon_pairwise_add_q types

Hi,  Please consider this as a personal reminder to review the patch at following link and let me know your comments on the same.  https://gcc.gnu.org/ml/gcc-patches/2017-03/msg00505.html Thanks, Naveen    

Re: [PING 4] [PATCH][AArch64] Add neon_pairwise_add & neon_pairwise_add_q types

Hi,  Please consider this as a personal reminder to review the patch at following link and let me know your comments on the same.  https://gcc.gnu.org/ml/gcc-patches/2017-03/msg00505.html Thanks, Naveen    

Re: [PATCH][AArch64] Add addr_type attribute

Hi James, Thanks for the review and comments on the patch. >> What am I missing - you add a new function which is never called? >> Should this have been in series with a scheduling model change? Sorry. You are right. This patch is one in series for scheduling and addition of attributes to improv

Re: [PATCH][AArch64] vec_pack_trunc_ should split after register allocator

Hi, >> I haven't been clear in what I was asking for Sorry. We understood right with the first comment but the second part confused us a bit :). >> Could you switch this back to an insn_and_split as it was in the previous >> patch, and just drop the && reload_completed ? Done. Bootstrapped and

Re: [PATCH][AArch64] vec_pack_trunc_ should split after register allocator

Hi, >> I think we can split this whenever we like, and >> that there isn't any benefit in keeping the pair together? Thanks for the review and your views. The patch is modified as per your suggestion. Please review the patch and let me know if its okay? Bootstrapped and Regression done on AArc

Re: [PING} [PATCH] Transform (m1 > m2) * d into m1> m2 ? d : 0

Hi,   Please consider this as a personal reminder to review the patch at following link and let me know your comments on the same.   https://gcc.gnu.org/ml/gcc-patches/2017-07/msg00178.html Thanks, Naveen

Re: [PING 5] [PATCH] [AArch64] vec_pack_trunc_ should split after register allocator

Hi,   Please consider this as a personal reminder to review the patch at following link and let me know your comments on the same.  https://gcc.gnu.org/ml/gcc-patches/2017-04/msg01334.html Thanks, Naveen    

Re: [PATCH] [AArch64] Fix PR71112

Hi Ramana, >> PR71112 is still open - should this be backported to GCC-6 ? Ported the patch to gcc-6-branch and committed as:- https://gcc.gnu.org/viewcvs/gcc?view=revision&revision=250014 Bootstrapped and Regression Tested gcc-6-branch for AArch64 on aarch64-thunder-linux. Thanks, Naveen

Re: [PATCH] Transform (m1 > m2) * d into m1> m2 ? d : 0

Hi, Thanks for the review and comments on the patch. >> The proposed patch handled both the same.  This means the pattern >> shouldn't use range-info but instead match a more complex The patch handles as per the discussion by matching the pattern in match.pd. Bootstrapped and Regression tested

Re: [PING 4] [PATCH] [AArch64] vec_pack_trunc_ should split after register allocator

Hi,  Please consider this as a personal reminder to review the patch at following link and let me know your comments on the same.  https://gcc.gnu.org/ml/gcc-patches/2017-04/msg01334.html Thanks, Naveen    

[PATCH] Transform (m1 > m2) * d into m1> m2 ? d : 0

Hi,  The code (m1 > m2) * d code should be optimized as m1> m2 ? d : 0. The patch optimizes it inside tree-vrp.c when simplifying with the range inside simplify_stmt_using_ranges. If a multiply is found and either side has a range [0,1], then transform it. Ex:- d * c where d has a range of [0,1]

Re: [PING][PATCH] Move the check for any_condjump_p from sched-deps to target macros

Hi Jeff, Thanks for the review and your approval for final patch. Sorry, It was a long weekend and hence could not revert to your comments earlier. >> You need a ChangeLog entry, but I think that's it. Can you >> please repost with a ChangeLog entry for final approval? Please find the final pat

Re: [PATCH][AArch64] Add crypto_pmull attribute

Hi Ramana, Thanks for the review and approval. >> Please update the ARM backend with the new attribute too >> (define_insn "crypto_vmullp64" Its already been updated in the patch posted at:- https://gcc.gnu.org/ml/gcc-patches/2017-03/msg00504.html >> Ok with that change and checking that you ca

Re: [PATCH][AArch64] Add crypto_pmull attribute

Hi James, Thanks for the approval. >> From an AArch64 perspective, this is OK - but please wait for an ARM >> approval before you commit it. Can anyone from ARM comment on the patch so that it can be committed upstream if no issues. https://gcc.gnu.org/ml/gcc-patches/2017-03/msg00504.html Than

Re: [PATCH, AArch64] Add x86 intrinsic headers to GCC AArch64 taget

Hi Joesph, Thanks for your review and valuable comments on this issue. Please find attached the patch that merges x86-intrinsics for AArch64 and PPC architectures. >> it would seem to me to be a bad idea to duplicate the >> implementation for more and more architectures. Merged the implementati

Re: [PING 3] [PATCH] [AArch64] vec_pack_trunc_ should split after register allocator

Hi,  Please consider this as a personal reminder to review the patch at following link and let me know your comments on the same.  https://gcc.gnu.org/ml/gcc-patches/2017-04/msg01334.html Thanks, Naveen    

Re: [PING 3] [PATCH] [AArch64] Implement ALU_BRANCH fusion

Hi Wilco, >> That looks good to me now. Thanks for the review and your okay for the patch. Please consider this as a personal reminder to review the patch at following link and let me know if its okay to commit? https://gcc.gnu.org/ml/gcc-patches/2017-04/msg01333.html Thanks, Naveen

Re: [PING 3][PATCH] Move the check for any_condjump_p from sched-deps to target macros

Hi Wilco, >> That looks good to me now. Thanks for the review and your okay for the patch. Please consider this as a personal reminder to review the patch at following link and let me know if its okay to commit? https://gcc.gnu.org/ml/gcc-patches/2017-05/msg00839.html Thanks, Naveen

Re: [PATCH] [AArch64] PR target/71663 Improve Vector Initializtion

Hi James, >> Could you make the testcase a bit more comprehensive? Modified the testcase considering all the possible cases. Split up the test based on different scenarios. Please review the patch and let us know if its okay? Thanks, Naveendiff --git a/gcc/config/aarch64/aarch64.c b/gcc/config

Re: [PATCH] [AArch64] PR target/71663 Improve Vector Initializtion

Hi James, Thanks for your review and useful comments. >> If you could try to keep one reply chain for each patch series Will keep that in mind for sure :-) >> Very minor, but what is wrong with: >> int matches[16][2] = {0}; Done. >> nummatches is unused. Removed. >> This search algorithm is to

[PATCH, AArch64] Add x86 intrinsic headers to GCC AArch64 taget

Hi, Please find attached the patch that adds first set of X86 instrinsic headers to AArch64 target. The implementation is based on similar work targeted at PPC64LE. https://gcc.gnu.org/ml/gcc-patches/2017-05/msg00550.html We are using the corresponding DejaGnu tests similar to Powerpc from gcc/t

Re: [PING 2] [PATCH] [AArch64] Implement ALU_BRANCH fusion

Hi,  Please consider this as a personal reminder to review the patch at following link and let me know your comments on the same.  https://gcc.gnu.org/ml/gcc-patches/2017-04/msg01333.html Thanks, Naveen   

Re: [PING 2] [PATCH] [AArch64] vec_pack_trunc_ should split after register allocator

Hi,  Please consider this as a personal reminder to review the patch at following link and let me know your comments on the same.  https://gcc.gnu.org/ml/gcc-patches/2017-04/msg01334.html Thanks, Naveen

Re: [PING 2] [PATCH] [AArch64] PR target/71663 Improve Vector Initializtion

Hi,  Please consider this as a personal reminder to review the patch at following link and let me know your comments on the same.  https://gcc.gnu.org/ml/gcc-patches/2017-04/msg01260.html Thanks, Naveen

Re: [PING 3] [PATCH][AArch64] Add neon_pairwise_add & neon_pairwise_add_q types

Hi,  Please consider this as a personal reminder to review the patch at following link and let me know your comments on the same.  https://gcc.gnu.org/ml/gcc-patches/2017-03/msg00505.html Thanks, Naveen    

Re: [PING 3][PATCH][AArch64] Add crypto_pmull attribute

Hi,   Please consider this as a personal reminder to review the patch at following link and let me know your comments on the same.   https://gcc.gnu.org/ml/gcc-patches/2017-03/msg00504.html Thanks, Naveen    

Re: [PING 3][PATCH] [AArch64] Implement automod load and store for Thunderx2t99

Hi,   Please consider this as a personal reminder to review the patch at following link and let me know your comments on the same.   https://gcc.gnu.org/ml/gcc-patches/2017-03/msg00226.html Thanks, Naveen    

Re: [PING 3][PATCH][AArch64] Add addr_type attribute

Hi,  Please consider this as a personal reminder to review the patch at following link and let me know your comments on the same.  https://gcc.gnu.org/ml/gcc-patches/2017-03/msg00222.html Thanks, Naveen    

Re: [PING 2][PATCH] Move the check for any_condjump_p from sched-deps to target macros

Hi, Please consider this as a personal reminder to review the patch at following link and let me know your comments on the same. https://gcc.gnu.org/ml/gcc-patches/2017-05/msg00839.html Thanks, Naveen    

Re: [PING] [PATCH] [AArch64] vec_pack_trunc_ should split after register allocator

Hi, Please consider this as a personal reminder to review the patch at following link and let me know your comments on the same. https://gcc.gnu.org/ml/gcc-patches/2017-04/msg01334.html Thanks, Naveen

Re: [PING] [PATCH] [AArch64] Implement ALU_BRANCH fusion

Hi, Please consider this as a personal reminder to review the patch at following link and let me know your comments on the same. https://gcc.gnu.org/ml/gcc-patches/2017-04/msg01333.html Thanks, Naveen   

Re: [PING] [PATCH] [AArch64] PR target/71663 Improve Vector Initializtion

Hi, Please consider this as a personal reminder to review the patch at following link and let me know your comments on the same. https://gcc.gnu.org/ml/gcc-patches/2017-04/msg01260.html Thanks, Naveen

Re: [PING2] [PATCH][AArch64] Add neon_pairwise_add & neon_pairwise_add_q types

Hi,  Please consider this as a personal reminder to review the patch at following link and let me know your comments on the same.  https://gcc.gnu.org/ml/gcc-patches/2017-03/msg00505.html Thanks, Naveen    

Re: [PING2][PATCH][AArch64] Add crypto_pmull attribute

Hi,   Please consider this as a personal reminder to review the patch at following link and let me know your comments on the same.   https://gcc.gnu.org/ml/gcc-patches/2017-03/msg00504.html Thanks, Naveen    

Re: [PING2][PATCH] [AArch64] Implement automod load and store for Thunderx2t99

Hi,   Please consider this as a personal reminder to review the patch at following link and let me know your comments on the same.   https://gcc.gnu.org/ml/gcc-patches/2017-03/msg00226.html Thanks, Naveen

Re: [PING2][PATCH][AArch64] Add addr_type attribute

Hi,  Please consider this as a personal reminder to review the patch at following link and let me know your comments on the same.  https://gcc.gnu.org/ml/gcc-patches/2017-03/msg00222.html Thanks, Naveen    

Re: [PING2][PATCH][AArch64] Add addr_type attribute

Hi,  Please consider this as a personal reminder to review the patch at following link and let me know your comments on the same.  https://gcc.gnu.org/ml/gcc-patches/2017-03/msg00222.html Thanks, Naveen    

Re: [PING2][PATCH][AArch64] Add addr_type attribute

Hi,  Please consider this as a personal reminder to review the patch at following link and let me know your comments on the same.  https://gcc.gnu.org/ml/gcc-patches/2017-03/msg00222.html Thanks, Naveen    

Re: [PING2][PATCH][AArch64] Add addr_type attribute

Hi,  Please consider this as a personal reminder to review the patch at following link and let me know your comments on the same.  https://gcc.gnu.org/ml/gcc-patches/2017-03/msg00222.html Thanks, Naveen    

Re: [PING][PATCH] Move the check for any_condjump_p from sched-deps to target macros

Hi, >> Doesn't this avoid calling the target hook in cases where it used to >> call it before? Yes. Thanks for pointing it out. >> Consider a conditional jump inside a parallel that is not a single set. Please find attached the modified patch that handles the case mentioned. Please review the

[PATCH][AArch64] vec_pack_trunc_ should split after register allocator

Hi, The instruction "vec_pack_trunc_" should be split after register allocator for scheduling reasons. Currently the instruction is marked as type multiple which means it will scheduled as single issued. However, nothing can be scheduled with either xtn/xtn2 which is a problem in some cases. The

Re: [PING][PATCH][AArch64] Implement ALU_BRANCH fusion

Hi Wilco, >> You should only return true if there is a match, not if there is >> not a match. Done. Bootstrapped and Regression tested on AArch64 and X86_64. Please review the patch and let us know if its okay? Thanks, Naveen    diff --git a/gcc/config/aarch64/aarch64-fusion-pairs.d

Re: [PING][PATCH] Move the check for any_condjump_p from sched-deps to target macros

Hi Wilco, >> I suggest you check the logic and follow the existing patterns in >> aarch_macro_fusion_pair_p. Done. Bootstrapped and Regression tested on AArch64 and X86_64. Please review the patch and let us know if its okay? Thanks, Naveen diff --git a/gcc/config/aarch64/aarch64.c b/gcc/c

Re: [PING][PATCH][AArch64] Implement ALU_BRANCH fusion

Hi Wilco, >> Same comment for this part, we want to return true if we match: Thanks for pointing out about the confusion. >> Note writing these complex conditions using positive logic makes them much >> more readable - if you have to negate use !(X && Y && Z) rather than >> !X || !Y || !Z. Modi

Re: [PING][PATCH] Move the check for any_condjump_p from sched-deps to target macros

Hi Wilco, Thanks for reviewing the patch. >> The return false seems incorrect - it means a core can either have >> FUSE_CMP_BRANCH or FUSE_ALU_BRANCH but not both. Thanks for pointing out about the confusion. Modified the code as required. Bootstrapped and Regression tested on AArch64 and X86_6

Re: [PATCH] [AArch64] PR target/71663 Improve Vector Initializtion

Hi Kyrill, Thanks for the review and your comments. >> It would be useful if you expanded a bit on the approach used to >> generate the improved codegen The patch creates a duplicate of most common element and tries to optimize the insertion using dup for the element followed by insertions. Cur

Re: [PING][PATCH][AArch64] Implement ALU_BRANCH fusion

Hi, Please consider this as a personal reminder to review the patch at following link and let me know your comments on the same. https://gcc.gnu.org/ml/gcc-patches/2017-03/msg01369.html Thanks, Naveen

[PING][PATCH] Move the check for any_condjump_p from sched-deps to target macros

Hi, Please consider this as a personal reminder to review the patch at following link and let me know your comments on the same. https://gcc.gnu.org/ml/gcc-patches/2017-03/msg01368.html Thanks, Naveen

[PING}[PATCH][AArch64] Add neon_pairwise_add & neon_pairwise_add_q types

Hi, Please consider this as a personal reminder to review the patch at following link and let me know your comments on the same. https://gcc.gnu.org/ml/gcc-patches/2017-03/msg00505.html Thanks, Naveen

[PING][PATCH][AArch64] Add crypto_pmull attribute

Hi,   Please consider this as a personal reminder to review the patch at following link and let me know your comments on the same.   https://gcc.gnu.org/ml/gcc-patches/2017-03/msg00504.html Thanks, Naveen

[PING][PATCH] [AArch64] Implement automod load and store for Thunderx2t99

Hi,   Please consider this as a personal reminder to review the patch at following link and let me know your comments on the same.   https://gcc.gnu.org/ml/gcc-patches/2017-03/msg00226.html Thanks, Naveen

[PING][PATCH][AArch64] Add addr_type attribute

Hi, Please consider this as a personal reminder to review the patch at following link and let me know your comments on the same. https://gcc.gnu.org/ml/gcc-patches/2017-03/msg00222.html Thanks, Naveen

[PING] [PATCH] [AArch64] PR target/71663 Improve Vector Initializtion

Hi, Please consider this as a personal reminder to review the patch at following link and let me know your comments on the same. https://gcc.gnu.org/ml/gcc-patches/2016-12/msg00718.html Thanks, Naveen

Re: [PATCH][AArch64] Implement ALU_BRANCH fusion

Hi, Thanks for the review and suggestions. > I think the patch isn't quite complete yet. You will also need changes in > generic code. Currently sched_macro_fuse_insns() does: Modified the sched_macro_fuse_insns() as required. > Basically the idea is to push the check for CC usage into target m

[PATCH] Move the check for any_condjump_p from sched-deps to target macros

Hi, Please find attached the patch that moves the check for CC usage in any_condjump_p from sched-deps to target macros. Currently the check is used only by i386 and AArch64. The general condition checks for the fusion candidates to use/modify CC1 register. However, the fusion of ALU and Branch i

Re: [PATCH][AArch64] Implement ALU_BRANCH fusion

Hi Kyrill, >> I suggest you reword the whole comment and not talk about particular CPUs >> but rather about the kinds of instructions you want to fuse Modified as per the comments. Had modified the earlier version of patch which had the vulcan reservation before James comments. Please find attac

Re: [PATCH][AArch64] Implement ALU_BRANCH fusion

Hi James, >> My reason for asking is that the instruction fusion implemented in LLVM >> ( lib/Target/AArch64/AArch64MacroFusion.cpp::shouldScheduleAdjacent ) Sorry. There seems to be some confusion in the branch instructions. The branch should be conditional for ALU_BRANCH fusion. Please find at

Re: [PATCH][AArch64] Add neon_pairwise_add & neon_pairwise_add_q types

Hi James, > The whitespace in various places in this patch is inconsistent with the > whitespace around the modified line. For example: Fixed the whitespace. >> So this patch isn't OK without fixes for the models >> in cortex-a53.md and exynos-m1.md Thanks for pointing out the missing cores in

Re: [PATCH][AArch64] Add crypto_pmull attribute

Hi James, >> You need to do this for all cores which might be affected by this change, >> i.e. all those which model neon_mul_d_long. Thanks for pointing out the missing cores in patch. Added the support as per your comments. Please find attached the modified patch and let us know if its okay fo

Re: [PATCH][AArch64] Implement ALU_BRANCH fusion

Hi James, Thanks for the review and your comments. >> I'd need more detail on what types of instruction pairs you >> are trying to fuse. The documentation mentions it as follows:- Single uop ALU instruction may fuse with adjacent branch instruction in the same bundle >> This comment looks inc

[PATCH][AArch64] Fix type for 1-element load

Hi, Please find attached the patch that fixes type for 1-element load in AArch64. Bootstrapped and Regression tested on aarch64-thunder-linux. Please review the patch and let us know if its okay for Stage-1? Thanks, Naveen 2017-03-06 Julian Brown Naveen H.S * config/aa

[PATCH][AArch64] Add neon_pairwise_add & neon_pairwise_add_q types

Hi, Please find attached the patch that adds "neon_pairwise_add" & "neon_pairwise_add_qcrypto_pmull" for AArch64. The patch doesn't change spec but improve other benchmarks. Bootstrapped and Regression tested on aarch64-thunder-linux. Please review the patch and let us know if its okay for Stag

[PATCH] [AArch64] Implement automod load and store for Thunderx2t99

Hi, Please find attached the patch that implements automod load and store for Thunderx2t99. The patch doesn't change spec but improve other benchmarks. Bootstrapped and Regression tested on aarch64-thunder-linux. Please review the patch and let us know if its okay for Stage-1? Thanks, Naveen 20

[PATCH][AArch64] Add aes and sha reservations for Thunderx2t99

Hi, Please find attached the patch that adds aes and sha reservations for Thunderx2t99. Bootstrapped and Regression tested on aarch64-thunder-linux. Please review the patch and let us know if its okay for Stage-1? Thanks, Naveen 2017-03-06  Julian Brown      Naveen H.S   * con

[PATCH][AArch64] Implement ALU_BRANCH fusion

Hi, Please find attached the patch that implements alu_branch fusion for AArch64. The patch doesn't change spec but improve other benchmarks. Bootstrapped and Regression tested on aarch64-thunder-linux. Please review the patch and let us know if its okay for Stage-1? Thanks, Naveen 2017-03-06

[PATCH][AArch64] Add crypto_pmull attribute

Hi, Please find attached the patch that adds "crypto_pmull" for AArch64. Bootstrapped and Regression tested on aarch64-thunder-linux. Please review the patch and let us know if its okay for Stage-1? Thanks, Naveen 2017-03-06 Julian Brown Naveen H.S * config/aarch64/aa

[PATCH][AArch64] Add crc reservations for Thunderx2t99

Hi, Please find attached the patch that adds crc reservations for Thunderx2t99. Bootstrapped and Regression tested on aarch64-thunder-linux. Please review the patch and let us know if its okay for Stage-1? Thanks, Naveen 2017-03-06 Julian Brown Naveen H.S * config/aarc

[PATCH][AArch64] Add addr_type attribute

Hi, Please find attached the patch that adds "addr_type" attribute for AArch64. The patch doesn't change spec but improve other benchmarks. Bootstrapped and Regression tested on aarch64-thunder-linux. Please review the patch and let us know if its okay for Stage-1? Thanks, Naveen 2017-03-06

Re: [PATCH] [AArch64] PR target/71663 Improve Vector Initializtion

Hi, Please consider this as a personal reminder to review the patch at following link and let me know your comments on the same. https://gcc.gnu.org/ml/gcc-patches/2016-12/msg00718.html Thanks, Naveen

Re: [PATCH] [AArch64] Implement popcount pattern

Hi Andrew, Thanks for clearing the confusion. > I don't understand this comment and how it relates to your updated patch foo, foo1 and foo2 generates calls to "popcountdi2" which should have been "popcountsi2" for foo1. When Kyrill commented on using the popcountsi2; I was confused :). Hence, t

Re: [PATCH/AARCH64] Add scheduler for Thunderx2t99

Hi James, Thanks for reviewing the patch and comments. >> I wonder whether the current modeling of: >> (define_insn_reservation "thunderx2t99_asimd_load4_elts" 6 >> Actually benefits the schedule in a meaningful way, or if it just increases Done. Removed the scheduler modeling for thunderx2t99_a

Re: [PATCH] [AArch64] Enable AES and cmp_branch fusion for Thunderx2t99

Hi Kyrill, Thanks for the review and comments. >> but there are a couple of issues with the ChangeLog 2017-02-02 Naveen H.S * config/aarch64/aarch64.c (thunderx2t99_tunings): Enable AES and cmp_branch fusion. Thanks, Naveen

Re: [PATCH] [AArch64] Implement popcount pattern

Hi James and Kyrill, Thanks for the review and comments on the patch. >> On ILP32 systems this would still use the SImode patterns, >> so I suggest you use __builtin_popcountll and >> an unsigned long long return type to ensure you always exercise the 64-bit >> code. Sorry for not commenting o

[PATCH] [AArch64] Enable AES and cmp_branch fusion for Thunderx2t99

Hi, Please find attached the patch that adds AES and CMP_BRANCH fusion for Thunderx2t99. Bootstrapped and Regression tested on aarch64-thunderx2t99. Please review the patch and let us know if its okay? 2017-1-25 Naveen H.S gcc * config/aarch64/aarch64.c (thunderx2t99_tunings):

[PATCH/AARCH64] Add scheduler for Thunderx2t99

Hi James, The scheduling patch for vulcan was posted at the following link:- https://gcc.gnu.org/ml/gcc-patches/2016-07/msg01205.html We are working on the patch and addressed the comments for thunderx2t99. >> I tried lowering the repeat expressions as so: Done. >>split off the AdvSIMD/FP model

[PATCH] [Match & Simplify] Optimize some minmax patterns

Hi, Please find attached the patch that optimizes some patterns in maxmin on same variabes with constants. Bootstrapped and Regression tested on x86_64 & aarch64-thunder-linux. Please review the patch and let us know if its okay? 2016-12-15 Andrew Pinski Naveen H.S gcc

Re: [PATCH] [AArch64] Implement popcount pattern

Hi Kyrill, Thanks for reviewing the patch and your useful comments. >> looks good to me if it has gone through the normal required >> bootstrap and testing, but I can't approve. Bootstrapped and Regression Tested on aarch64-thunderx-linux. >> The rest of the MD file uses the term AdvSIMD. Also,

[PATCH] [AArch64] Implement popcount pattern

Hi, Please find attached the patch that implements the support for popcount patterns in AArch64. The implementation improves OVS-DPDK on ThunderX by 3%. It would have a similar effect on other AArch64 targets. Please review the patch and let us know if its okay? 2016-12-12 Andrew Pinski gcc

Re: [PATCH] [AArch64] PR target/71663 Improve Vector Initializtion

Hi, Sorry. Missed out the testcase in patch submission. Added the missing testcase along with the ChangeLog. Please review the same and let us know if thats okay? 2016-12-09  Andrew PInski  gcc     * config/aarch64/aarch64.c (aarch64_expand_vector_init):     Improve vector initializatio

[PATCH] [AArch64] PR target/71663 Improve Vector Initializtion

Hi, The AArch64 vector initialization sequence can be optimized to generate better code. The attached patch handles for the case where the vector contains only variables. It checks for the common elements in the vector and inserts the values in optimized way. Bootstrapped and Regression tested on

Re: [PATCH] [AArch64] Fix PR78382

Hi James, Thanks for the review and suggestions regarding the testcase. >> Why limit the ABI and endianness here Extra options have been dropped and the testcase will check across all variants and endianness. Please find attached the modified patch as per the comments and let me know if its oka

Re: [PATCH] [AArch64] Fix PR71112

Hi James, Thanks for the review and suggestions regarding the testcase. >> Why limit the ABI and endianness here, and if you do plan to do that Extra options have been dropped and the testcase will check across all variants and endianness. Please find attached the modified patch as per the comm

[PING][PATCH] [AArch64] Fix PR71112

Hi, Please consider this as a personal reminder to review the patch at following link and let me know your comments on the same. https://gcc.gnu.org/ml/gcc-patches/2016-11/msg02305.html Thanks, Naveen

[PING][PATCH] [AArch64] Fix PR78382

Hi, Please consider this as a personal reminder to review the patch at following link and let me know your comments on the same. https://gcc.gnu.org/ml/gcc-patches/2016-11/msg02078.html Thanks, Naveen

[PING] [PATCH] [AArch64] Fix PR71727

Hi, Please consider this as a personal reminder to review the patch at following link and let me know your comments on the same. https://gcc.gnu.org/ml/gcc-patches/2016-11/msg00697.html Thanks, Naveen

Re: [PING] [PATCH] Fix PR31096

Hi Jeff, >> I believe Richi asked for a small change after which you can consider >> the patch approved: Yeah. Thanks for all the comments and reviews. Patch committed after the modification as:- https://gcc.gnu.org/ml/gcc-cvs/2016-11/msg01019.html Thanks, Naveen

[PING] [PATCH] Fix PR71727

Hi, Please consider this as a personal reminder to review the patch at following link and let me know your comments on the same. https://gcc.gnu.org/ml/gcc-patches/2016-11/msg00697.html Thanks, Naveen

[PATCH] [AArch64] Fix PR71112

Hi, Please find attached the patch that fixes PR71112. The current implementation that handles SYMBOL_SMALL_GOT_28K in aarch64_load_symref_appropriately access the high part of RTX for Big-Endian mode which results in ICE for ILP32. The attached patch modifies it by accessing the lower part for

[PING] [PATCH] Fix PR31096

Hi, Please consider this as a personal reminder to review the patch at following link and let me know your comments on the same. https://gcc.gnu.org/ml/gcc-patches/2016-11/msg01049.html Thanks, Naveen

[PATCH] [AArch64] Fix PR77635

Hi, Please find attached the patch that fixes PR77635. Some load pair testcase fails when gcc is configured "--with-cpu=thunderx" as -mcpu=generic is missed out in them. The attached patch modifies the testcases to use -mcpu=generic. Please review the patch and let me know if its okay? 2016-11-

[PATCH] [AArch64] Fix PR77634

Hi, Please find attached the patch that fixes PR77634. Some testcase does not use -fno-vect-cost-model and hence fails when gcc is configured "--with-cpu=thunderx". The attached patch modifies the testcases to use -fno-vect-cost-model. Please review the patch and let me know if its okay? 2016

Re: [PATCH] [AArch64] Fix PR78382

Hi Kugan, >> Why don't you use the mode of dest as done in other similar places. Like: Thanks for the pointer. Modified the patch as per your suggestion. Please find attached the modified patch and let me know your comments. Bootstrapped and regression tested on Thunderx. Thanks, Naveen d

Re: [PATCH] [AArch64] Fix PR78382

Hi Kyrill, Thanks for the comment. Bootstrapped successfully on AArch64 (thunder) system. And also regression tested on AArch64(thunder) with no regressions. Thanks, Naveen

[PATCH] [AArch64] Fix PR78382

Hi, Please find attached the patch that fixes PR78382. The "SYMBOL_SMALL_TLSGD" was not handled for ILP32. Hence it generates error when compiled for ILP32. The attached patch adds the support and handles it properly as expected for ILP32. Please review the patch and let me know if its okay?

Re: [PATCH] Fix PR31096

Hi, Sorry for a very late reply as the mail was missed or overlooked. >> could now move the test tree_expr_nonzero_p next to >> tree_expr_nonnegative_p (it is redundant for the last case). Done. >> Often just a comment can really help here. Comments updated as per the suggestion >> when

Re: [PATCH] [AArch64] Fix PR71727

Hi Kyrill, Thanks for the review and suggestions. >> It's a good idea to CC the AArch64 maintainers and reviewers >> on aarch64 patches, or at least Thanks for CCing the maintainers. Added [AArch64] in the subject line. >> New functions need a function comment describing their arguments and the

[PATCH] Fix PR71727

Hi, Please find attached the patch that fixes PR71727. Please review the patch and let me know if its okay? Regression tested on Aarch64 with no regressions. Thanks, Naveen 2016-11-08 Naveen H.S * config/aarch64/aarch64.c (aarch64_builtin_support_vector_misalignment): New.

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