Am 25.04.25 um 16:37 schrieb Vladimir Makarov:
On 4/19/25 3:29 PM, Denis Chertykov wrote:
Bugfix for PR118591
[...]
It is difficult for me to understand AVR code but I think the reason for
the bug is in something else. And the fix should be different.
Hi Vladimir,
let me try to explain t
This patch adds fdiml to libgcc/config/avr/libf7
AVR: target/120442 - Support f7_fdim / fdiml in LibF7.
PR target/120442
Add Support for fdiml.
libgcc/config/avr/libf7/
* libf7-common.mk (LIBF_C_PARTS, m_ddd): Add fdim.
* libf7.h (f7_fdim): New proto.
* li
f7_exp's exponent was limited to |a| < 512, but exponents to to
1024 * ln2 = 709 may occur.
Applied as obvious.
Johann
--
AVR: target/120441 - Fix f7_exp for |x| ≥ 512.
f7_exp limited exponents to 512, but 1023 * ln2 ≈ 709,
hence 1024 is a correct limit.
libgcc/config/avr/libf7/
PR t
libgcc's __xload_1...4 is clobbering Z (and also R21 is some cases),
but avr.md had clobbers of respective GPRs only up to reload.
Outcome was that code reading from the same __memx address twice
could be wrong. This patch adds respective clobbers.
Applied as obvious.
Johann
--
AVR: target/11
When MUL is not available, then the __umulhisi3 and __mulhisi3
functions can use __mulhisi3_helper. This improves code size,
stack footprint and runtime on AVRrc. Applied as obvious.
Johann
--
AVRrc: Tweak __[u]mulhisi3.
When MUL is not available, then the __umulhisi3 and __mulhisi3
functio
With a few changes, 8-bit and 16-bit fixed-point operations
can be made work on the reduced core. Added as obvious.
Johann
--
AVRrc: Support 8-bit and 16-bit fixed-point arith in libgcc.
With some minor changes, 8-bit and 16-bit fixed-point operations
can be supported on the reduced core.
lib
__umulhisi3 had a code size optimization of 6 bytes that costs
a call. This patch uses linear code on all devices with MUL
irrespective of program memory size.
Johann
--
AVR: Speed up __umulhisi3 for small devices with MUL.
__umulhisi3 had an "rcall 1f" to save 6 bytes, which is an un
Applied the patch below.
Johann
--
AVR: Clarify some optimization options.
gcc/
* doc/invoke.texi (AVR Optimization Options)
<-maccumulate-args>: Refer to -fdefer-pop.
<-muse-nonzero-bits>: Re-formulate what the option does.
diff --git a/gcc/doc/invoke.texi b/gcc/doc/i
Support for the AVR-SD devices (which are 1-liners) has been backported
to v13 and v14.
Johann
--
gcc-13, gcc-14: AVR: Mention more new devices.
diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html
index 4860c500..e589e0d6 100644
--- a/htdocs/gcc-13/changes.html
+++ b/htdoc
Added the following 6 AVR-SD devices.
Johann
--
AVR: Add AVR-SD devices.
gcc/
* config/avr/avr-mcus.def: Add AVR32SD20, AVR32SD28, AVR32SD32,
AVR64SD28, AVR64SD32, AVR64SD48.
* doc/avr-mmcu.texi: Rebuild.diff --git a/gcc/config/avr/avr-mcus.def b/gcc/config/avr/avr-mcus
AVR: Use "avr-peep2-after-fuse-move" for the 2nd run of peephole2.
This patch uses a name for the dump file that makes it clear where
in the pass chain the 2nd run of peephole2 is located.
gcc/
* config/avr/avr.c (avr_option_override): Use
"avr-peep2-after-fuse-move" as dump name
The condition to exclude some object files for AVRrc reduced core
did not work properly since it was too strict.
LibF7 didn't exclude its objects at all.
This patch uses $(findstring avrtiny,$(MULTIDIR)) in the condition.
No new regressions. Ok to apply?
Johann
--
AVR: libgcc: Properly exclu
There are occasions where knowledge about nonzero bits makes some
optimizations possible. For example,
Rd |= Rn << Off
can be implemented as
SBRC Rn, 0
ORI Rd, 1 << Off
when Rn in { 0, 1 }, i.e. nonzero_bits (Rn) == 1. This patch adds some
patterns that exploit nonzero_bits() in so
functions
in .initN and .finiN.commit e0e33695a97576cd8cc23da5d5162e4fa595e7ba
Author: Georg-Johann Lay
Date: Fri Mar 21 14:29:13 2025 +0100
AVR: Add attribute "used" for code in .initN and .initN sections.
Code in .initN and .initN sections is never called since these
sections are special and
Applied this patch as obvious.
Johann
--
AVR: target/119355 - Fix ICE in pass avr-fuse-move / -mfuse-move.
This ICE only occurred when the compiler is built with, say
CXXFLAGS='-Wp,-D_GLIBCXX_ASSERTIONS'. The problem was that
a value from an illegal REGNO was read. The value was not
used in
Am 16.03.25 um 02:26 schrieb Gerald Pfeifer:
On Thu, 13 Feb 2025, Georg-Johann Lay wrote:
Applied the following avr news to gcc-15:
Thanks!
+ Support has been added for the new option
+https://gcc.gnu.org/onlinedocs/gcc/AVR-Options.html#index-mno-call-main";
+ >-mno-c
This patch adds a new section "AVR Optimization Options"
in the texi documentation.
Ok for trunk?
Johann
--
AVR: Add texi @subsubsection "AVR Optimization Options".
gcc/
* doc/invoke.texi (AVR Optimization Options): New @subsubsection
for pure optimization options.
diff --git
This adds one more ISR test to the ave testsuite.
Johann
--
AVR: Add new ISR test gcc.target/avr/torture/isr-04-regs.c.
gcc/testsuite/
* gcc.target/avr/torture/isr-04-regs.c: New test.
* gcc.target/avr/isr-test.h: Don't set GPRs to values
that are 0 mod 0x11.AVR: Ad
Added this addendum to PR118764 / "compact vector table".
Johann
--
AVR: ad target/118764 - Let -mcvt set built-in macro __AVR_CVT__
gcc/
PR target/118764
* config/avr/avr-c.cc (avr_cpu_cpp_builtins)
[TARGET_CVT]: Define __AVR_CVT__.
* doc/invoke.texi (AVR Built
This patch executes avr_builtin_supported_p at a later time and in
avr_resolve_overloaded_builtin. This allows for better diagnostics
and avoids lto1 hiccups when a built-in decl is NULL_TREE.
Ok for trunk?
Johann
--
AVR: Diagnose unsupported built-ins in avr_resolve_overloaded_builtin.
This
When REG_UNUSED notes indicate that some result bytes are not
used by the following code, then there's no need to asm out them.
The patch uses such notes for the asm out of AND, IOR, XOR, PLUS, MINUS.
Passes without regressions. Ok for trunk?
Johann
--
AVR: Don't asm output operations for un
This patch fixes an ICE on trunk, so I don't plan to backport.
Ok for trunk?
Johann
--
AVR: target/118878 - Don't ICE on result from paradoxical reg's alloc.
After register allocation, paradoxical subregs may become something
like r20:SI += r22:SI which doesn't make much sense as assembly c
Applied the following avr news to gcc-15:
diff --git a/htdocs/gcc-15/changes.html b/htdocs/gcc-15/changes.html
index 7638d3d5..41425257 100644
--- a/htdocs/gcc-15/changes.html
+++ b/htdocs/gcc-15/changes.html
@@ -500,6 +500,10 @@ asm (".text; %cc0: mov %cc2, %%r0; .previous;"
>-msplit-lds
s not compatible with hardware interrupts.
@@ -24535,7 +24553,19 @@ Allow to use truncation instead of rounding
towards zero for fractional fixed-po
@opindex nodevicelib
@item -nodevicelib
-Don't link against AVR-LibC's device specific library
Am 09.02.25 um 11:26 schrieb Georg-Johann Lay:
Am 09.02.25 um 17:30 schrieb Jeff Law:
On 2/9/25 1:10 AM, Georg-Johann Lay wrote:
The .ira dump has several paradoxical subregs like:
(insn 22 21 60 4 (set (reg/v:SI 51 [ val32 ])
(subreg:SI (reg:HI 53 [ t$val ]) 0)) "pr116389-red.c":14:14
146 {*movsi_split}
(insn 27 26
On devices with very limited resources, it may be desirable to run
main in a more efficient way than provided by the startup code
XCALL main
XJMP exit
from section .init9. In AVR-LibC v2.3, that code has been moved to
libmcu.a, hence symbol __call_main can be satisfied so that the
respec
CCing Denis
Am 08.02.25 um 23:51 schrieb Jeff Law:
On 2/8/25 1:52 PM, Georg-Johann Lay wrote:
Am 08.02.25 um 18:23 schrieb Jeff Law:
On 2/8/25 3:04 AM, Georg-Johann Lay wrote:
That test case from https://gcc.gnu.org/bugzilla/show_bug.cgi?
id=116389#c7
still ICEs with that change in http
Fixed typos in extend.texi.
Applied as as obvious.
Johann
--
ad target/118764: Fix a typo in doc/extend.texi.
gcc/
PR target/118764
* doc/invoke.texi (AVR Options): Fix typos.
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index c33eb4425de..0aef2abf05b
Am 08.02.25 um 18:23 schrieb Jeff Law:
On 2/8/25 3:04 AM, Georg-Johann Lay wrote:
That test case from
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116389#c7
still ICEs with that change in http://gcc.gnu.org/r15-7428
pr116389-red.c: In function 'func':
pr116389-red.c:20:1: e
Am 07.02.25 um 22:28 schrieb Jeff Law:
On 2/7/25 11:01 AM, Georg-Johann Lay wrote:
Am 07.02.25 um 17:12 schrieb Jeff Law:
On 2/3/25 2:09 AM, Richard Sandiford wrote:
Jeff Law writes:
So pulling on this thread leads me into the code that sets up
ALLOCNO_WMODE in create_insn_allocnos
Applied this one.
Johann
--
diff --git a/htdocs/gcc-15/changes.html b/htdocs/gcc-15/changes.html
index 362f345c..6a41ac97 100644
--- a/htdocs/gcc-15/changes.html
+++ b/htdocs/gcc-15/changes.html
@@ -376,6 +376,12 @@ asm (".text; %cc0: mov %cc2, %%r0; .previous;"
Code generation for the 32-bi
Am 07.02.25 um 17:12 schrieb Jeff Law:
On 2/3/25 2:09 AM, Richard Sandiford wrote:
Jeff Law writes:
So pulling on this thread leads me into the code that sets up
ALLOCNO_WMODE in create_insn_allocnos:
if ((a = ira_curr_regno_allocno_map[regno]) == NULL)
{
Some AVR devices support a Compact Vector Table.
The support is provided by means of a startup code file
crt-cvt.o from AVR-LibC that can be linked instead
of the traditional crt.o.
This patch adds a new command line option -mcvt that links
that CVT startup code (or issues an error when the devi
This patch implements a more robust parsing of the
AVR_MCU lines in genmultlib.awk.
The generated t-multilib-avr is the same.
Ok for trunk?
Johann
AVR: genmultilib.awk - Use more robust parsing of spaces.
gcc/
* config/avr/genmultilib.awk: Parse the AVR_MCU lines in
a more rob
For easier review, I broke that patch into two parts:
One for the strlen built-ins, and one to handle built-ins
that are only available in C.
Delta is the same.
Johann
Am 30.01.25 um 11:42 schrieb Georg-Johann Lay:
AVR: Provide built-ins for strlen where the string lives in some AS.
This
AVR: Provide built-ins for strlen where the string lives in some AS.
This patch adds built-in functions __builtin_avr_strlen_flash,
__builtin_avr_strlen_flashx and __builtin_avr_strlen_memx.
Purpose is that higher-level functions can use __builtin_constant_p
on strlen without raising a diagnostic
Am 27.01.25 um 16:19 schrieb Richard Sandiford:
Georg-Johann Lay writes:
Am 24.01.25 um 08:18 schrieb Richard Biener:
On Thu, Jan 23, 2025 at 4:53 PM Georg-Johann Lay wrote:
Am 23.01.25 um 14:58 schrieb Richard Biener:
On Thu, Jan 23, 2025 at 2:23 PM Georg-Johann Lay wrote:
Hi, this is
Am 24.01.25 um 12:59 schrieb Georg-Johann Lay:
Am 24.01.25 um 08:18 schrieb Richard Biener:
On Thu, Jan 23, 2025 at 4:53 PM Georg-Johann Lay wrote:
Am 23.01.25 um 14:58 schrieb Richard Biener:
On Thu, Jan 23, 2025 at 2:23 PM Georg-Johann Lay wrote:
Hi, this is Ping #2 for a patch from
Am 24.01.25 um 08:18 schrieb Richard Biener:
On Thu, Jan 23, 2025 at 4:53 PM Georg-Johann Lay wrote:
Am 23.01.25 um 14:58 schrieb Richard Biener:
On Thu, Jan 23, 2025 at 2:23 PM Georg-Johann Lay wrote:
Hi, this is Ping #2 for a patch from 2024.
It adds a new target hook that allows to
Am 23.01.25 um 14:58 schrieb Richard Biener:
On Thu, Jan 23, 2025 at 2:23 PM Georg-Johann Lay wrote:
Hi, this is Ping #2 for a patch from 2024.
It adds a new target hook that allows to output
assembly code for a VAR_DECL in a custom way.
The default action is an obvious no-op,
i.e
Am 23.01.25 um 14:58 schrieb Richard Biener:
On Thu, Jan 23, 2025 at 2:23 PM Georg-Johann Lay wrote:
Hi, this is Ping #2 for a patch from 2024.
It adds a new target hook that allows to output
assembly code for a VAR_DECL in a custom way.
The default action is an obvious no-op,
i.e
Hi, this is Ping #2 for a patch from 2024.
It adds a new target hook that allows to output
assembly code for a VAR_DECL in a custom way.
The default action is an obvious no-op,
i.e. assemble_variable() behaves like before.
This hook is needed in the avr backend to properly implement
some varia
Ping for https://gcc.gnu.org/pipermail/gcc-patches/2025-January/673336.html
Am 11.01.25 um 14:09 schrieb Georg-Johann Lay:
The patch below is for trunk.
Andrew Pinski says he has a patch to fix it, bit that won't materialize
before v16.
AVR: PR118012 - Try to work around sick code
As it turns out, logical 32-bit shifts with an offset of 25..30 can
be performed in 7 instructions or less. This beats the 7 instruc-
tions required for the default code of a shift loop.
Plus, with zero overhead, these cases can be 3-operand.
This is only relevant for -Oz because with -Os, 3op s
Added 2 tests for PR118591.
Johann
--
AVR: Add test cases for PR118591.
gcc/testsuite/
PR rtl-optimization/118591
* gcc.target/avr/torture/pr118591-1.c: New test.
* gcc.target/avr/torture/pr118591-2.c: New test.
diff --git a/gcc/testsuite/gcc.target/avr/torture/pr11859
Am 18.01.25 um 19:30 schrieb Dimitar Dimitrov:
This test fails on AVR.
Debugging the test on x86 host, I noticed that u in function s sometimes
has value 16128. The "t <= 3 * u" expression in the same function
results in signed integer overflow for targets with sizeof(int)=16.
Fix by requiring
u16 << 5 and u16 << 6 can be tweaked by using MUL instructions.
Benefit is a better speed ratio with -Os and smaller size with -O2.
No new regressions.
Ok for trunk?
Johann
..
AVR: Tweak some 16-bit shifts by using MUL.
u16 << 5 and u16 << 6 can be tweaked by using MUL instructions.
Benefit
Seems in the "extended asm" there is a typo:
"constraints have been for defining" gives me a syntax error.
The patch also improves punctuation.
Johann
--
diff --git a/htdocs/gcc-15/changes.html b/htdocs/gcc-15/changes.html
index a9778659..f38745a4 100644
--- a/htdocs/gcc-15/changes.html
+++ b/
Applied the patch below that adds more v15 avr news.
Johann
--
diff --git a/htdocs/gcc-15/changes.html b/htdocs/gcc-15/changes.html
index 82a86488..16d20554 100644
--- a/htdocs/gcc-15/changes.html
+++ b/htdocs/gcc-15/changes.html
@@ -362,6 +362,28 @@ asm (".text; %cc0: mov %cc2, %%r0; .previous
Most of the avr built-in functions can be attributed "const".
Ok for trunk?
Johann
--
AVR: Add "const" attribute to avr built-in functions if possible.
gcc/
* config/avr/avr-c.cc (DEF_BUILTIN): Add ATTRS argument to macro
definition.
* config/avr/avr.cc: Same.
This patch uses the INT_N interface to define __int24.
Ok for trunk?
Johann
--
AVR: Use INT_N to built-in define __int24.
This patch uses the INT_N interface to define __int24 in avr-modes.def.
Since the testsuite uses -Wpedantic and __int24 is a C/C++ extension,
uses of __int24 and __uint24
Ping for trunk
https://gcc.gnu.org/pipermail/gcc-patches/2024-December/672050.html
Notice that the patch is bootstrapped and reg-tested and I may
commit-after-approval, so no further work from admins is needed.
The avr part has already been approved 2024-12-20.
The default action is an obvious
Am 12.01.25 um 13:54 schrieb Denis Chertykov:
вс, 12 янв. 2025 г. в 15:38, Georg-Johann Lay :
Am 11.01.25 um 19:15 schrieb Denis Chertykov:
The fix for PR117868.
[...]
PR rtl-optimization/117868
gcc/
* lra-spills.cc (assign_stack_slot_num_and_sort_pseudos): Reuse slots
only
Am 11.01.25 um 19:15 schrieb Denis Chertykov:
The fix for PR117868.
[...]
PR rtl-optimization/117868
gcc/
* lra-spills.cc (assign_stack_slot_num_and_sort_pseudos): Reuse slots
only without allocated memory or only with equal or smaller registers
with equal or smaller alignmen
The patch below is for trunk.
Andrew Pinski says he has a patch to fix it, bit that won't materialize
before v16.
AVR: PR118012 - Try to work around sick code from match.pd.
This patch tries to work around PR118012 which may use a
full fledged multiplication instead of a simple bit test.
This i
This is a ping for
https://gcc.gnu.org/pipermail/gcc-patches/2024-December/671216.html
Johann
This patch adds a new target hook that allows to chose
a non-generic named address-space for compiler generated
lookup tables.
The purpose is that there are cases (on avr namely) where
the generic ad
The "io", "io_low", and "address" attributes require to asm output
the definition of respective symbols in a manner that was not supported
until the introduction of the new target hook TARGET_ASM_VARIABLE.
The previous implementation of these attributes abused tls_common_section
which is a noswit
This patch adds a new target hook that allows the backend to asm output
a variable definition in its own way. This hook is needed because
varasm.cc imposes a very restrictive layout for all variable definitions
which will be basically ELF style (on ELF targets as least). To date,
there is no way
* rampz_rtx et al. were missing MEM_VOLATILE_P. This is needed because
avr_emit_cpymemhi is setting RAMPZ explicitly with an own insn.
* avr_out_cpymem was missing a final RAMPZ = 0 on EBI devices.
This only affects the __flash1 ... __flash5 spaces since the other ASes
use different routines,
ace_t
+avr_addr_space_for_artificial_rodata (tree /*type*/,
+ artificial_rodata /*kind*/)
+{
+ return avr_rodata_in_flash_p ()
+? ADDR_SPACE_GENERIC
+: avropt_n_flash > 1 ? ADDR_SPACE_MEMX : ADDR_SPACE_FLASH;
+}
+
Johann
Am 09.12.24 um 15:13 schrieb Georg-Johann Lay:
This patc
This patch adds __flashx as a new named address space that allocates
objects in .progmemx.data. The handling is mostly the same or similar
to that of 24-bit space __memx, except that the output routines are
simpler and more efficient. Loads are emit inline when ELPMX or
LPMX is available. The a
This patch adds a new target hook that allows to chose
a non-generic named address-space for compiler generated
lookup tables.
The purpose is that there are cases (on avr namely) where
the generic address space is sub-optimal because it must
put .rodata in RAM. With this hook it is possible to
c
Am 07.12.24 um 22:25 schrieb Stefan Schulze Frielinghaus:
On Sat, Dec 07, 2024 at 08:49:20AM +0100, Georg-Johann Lay wrote:
Is there a PR for this feature? (Just to make sure that I don't
miss progress on this I could CC to the PR).
No. However, I can CC you in case of further
Am 07.12.24 um 02:03 schrieb Oleg Endo:
On Fri, 2024-12-06 at 16:51 +0100, Georg-Johann Lay wrote:
The CRC tables ARE put into .rodata, not into .data.
The correct question is: Why is avr putting .rodata into RAM?
Suppose the following C code:
char read_c (const char *p)
{
return p[1
...the patch
Am 07.12.24 um 14:36 schrieb Georg-Johann Lay:
This patch implements an alarm should we ever run out of
section flags bits.
Ok for trunk?
Johann
--
AVR: Assert minimal required bit width of section_common::flags.
gcc/
* config/avr/avr.cc (avr_ctz): New constexpr function
This patch implements an alarm should we ever run out of
section flags bits.
Ok for trunk?
Johann
--
AVR: Assert minimal required bit width of section_common::flags.
gcc/
* config/avr/avr.cc (avr_ctz): New constexpr function.
(section_common::flags): Assert minimal bit width.
Is there a PR for this feature? (Just to make sure that I don't
miss progress on this I could CC to the PR).
Johann
Am 10.09.24 um 16:20 schrieb Stefan Schulze Frielinghaus:
This series introduces hard register constraints. The first patch
enables hard register constraints for asm statements
Am 06.12.24 um 15:50 schrieb Oleg Endo:
On Fri, 2024-12-06 at 06:32 -0700, Jeff Law wrote:
On 12/6/24 5:23 AM, Sam James wrote:
Georg-Johann Lay writes:
This patch disables CRC lookup tables which consume quite some RAM.
Given that -foptimize-crc is new, it may be useful to CC the pass
Am 06.12.24 um 14:53 schrieb Richard Biener:
On Fri, Dec 6, 2024 at 2:17 PM Georg-Johann Lay wrote:
Am 06.12.24 um 13:23 schrieb Sam James:
Georg-Johann Lay writes:
This patch disables CRC lookup tables which consume quite some RAM.
Given that -foptimize-crc is new, it may be useful to
Am 06.12.24 um 13:23 schrieb Sam James:
Georg-Johann Lay writes:
This patch disables CRC lookup tables which consume quite some RAM.
Given that -foptimize-crc is new, it may be useful to CC the pass
authors in case they have input.
CCing Mariam Arutunian
Ok for trunk?
Johann
The
This patch disables CRC lookup tables which consume quite some RAM.
Ok for trunk?
Johann
--
AVR: Disable generation of CRC lookup tables.
With -foptimize-crc, large lookup tables may be generated which
are places in .rodata (RAM). This patch disables such tables.
gcc/
* common/confi
This is an addendum to the -msplit-ldst patch.
When -msplit-ldst is on, it may be possible to propagate __zero_reg__
to the sources of the new stores. For example, without this patch,
unsigned long lx;
void store_lsr17 (void)
{
lx >>= 17;
}
compiles to:
store_lsr17:
lds r26,lx+2
Applied the following patch that fixed an ICE when
-fdump-rtl-avr-fuse-move is on, because when 2 insn have been
combined into a single one, then m_insn is undefined.
To date, m_insn is only used in dumps.
Applied as obvious.
Johann
--
AVR: ad target/84211 - Fix dumping INSN_UID for null insn.
In nonlocal_goto sets, change hard_frame_pointer_rtx only after
emit_stack_restore() restored SP. This is needed because SP
my be stored in some frame location.
The only change to test results is that gcc.c-torture/execute/pr64242.c
is passing now.
Ok to apply?
Johann
--
AVR: target/64242 -
This patch splits multi-byte loads and stores into single-byte
ones provided:
- New option -msplit-ldst is on (e.g. -O2 and higher), and
- The memory is non-volatile, and
- The address space is generic, and
- The split addresses are natively supported by the hardware.
Passes without regressi
This patch reworks patterns that add / subtract an (inverted) MSB.
It handles more cases by using mode iterators.
Ok for trunk?
Johann
--
AVR: Rework patterns that add / subtract an (inverted) MSB.
gcc/
* config/avr/avr-protos.h (avr_out_add_msb): New proto.
* config/avr/avr.c
Applied the patch below which also splits logic shifts
with an offset of bitsize - 1 into byte operations.
Johann
--
AVR: ad target/117726 - Also split logic shifts of bitsize - 1.
When -msplit-bit-shift is on, also split logic shifts of bitsize(mode) - 1.
gcc/
PR target/117726
Am 03.12.24 um 15:36 schrieb Jeff Law:
On 12/3/24 3:57 AM, Georg-Johann Lay wrote:
This patch skips some tests that don't work on avr.
Ok for trunk?
Johann
--
AVR: Skip some test cases that don't work for it.
gcc/testsuite/
* gcc.c-torture/execute/ieee/cdivchkd.x
Some diagnostics are issues late, e.g. in avr_print_operand().
This patch uses the insn's location as a proxy for the operand
location. Without the patch, the location is usually input_location,
which points to the closing } of the function body.
Ok for trunk?
Johan
--
AVR: Improve location o
This patch fixes some unrelated tests that were failing.
In most cases, bad tests are slipping in because they
are preprocessed like:
size_t -> long unsigned int -> breaks when size_t is smaller etc.
Other reason is that they assume int is > 16 bits.
Unfortunately, in many cases it's not known
This patch skips some tests that don't work on avr.
Ok for trunk?
Johann
--
AVR: Skip some test cases that don't work for it.
gcc/testsuite/
* gcc.c-torture/execute/ieee/cdivchkd.x: New file.
* gcc.c-torture/execute/ieee/cdivchkf.x: New file.
* gcc.dg/flex-array-counte
Logic 8-bit shifts with an offset of 6 can be improved by
supporting them as 3-operand operations.
Ok for trunk?
Johann
--
AVR: Tweak uin8_t << 6 and uint8_t >> 6 shifts.
Logic 8-bit shifts with an offset of 6 can be improved by
supporting them as 3-operand operations.
PR target/1177
Am 01.12.24 um 19:15 schrieb Dimitar Dimitrov:
On Sun, Dec 01, 2024 at 12:32:55PM +0100, Georg-Johann Lay wrote:
Am 01.12.24 um 05:45 schrieb Maciej W. Rozycki:
On Sat, 30 Nov 2024, Georg-Johann Lay wrote:
The gcc.c-torture/execute/memcpy-a[1248].c tests consumed more time
than the whole rest
Am 01.12.24 um 05:45 schrieb Maciej W. Rozycki:
On Sat, 30 Nov 2024, Georg-Johann Lay wrote:
The gcc.c-torture/execute/memcpy-a[1248].c tests consumed more time
than the whole rest of the test suite, just to come up with
a "memory full" even at -Os. Skipped thusly.
As a matter o
When splitting multi-byte REG-REG moves in try_split_any(),
it's not clear whether propagating constants will turn
out as profitable. When MOVW is available, split into
REG-REG moves instead of a possible REG-CONST.
Johann
--
AVR: ad target/84211 - Split MOVW into MOVs in try_split_any.
This patch fixed some unrelated coding rule nits.
Johann
--
AVR: Fix some coding rule nits and typos.
gcc/
* config/avr/avr-c.cc: Fix some coding rule nits and typos.
* config/avr/avr-passes.cc: Same
* config/avr/avr.h: Same.
* config/avr/avr.cc: Same.
(
but should use Pmode.
PR target/117681
gcc/
* config/avr/avr.cc (TARGET_UNWIND_WORD_MODE): Define to...
(avr_unwind_word_mode): ...this new static function.commit 9e48a5e1dc054959d1dfc2f757d5dcfbdb18e1c3
Author: Georg-Johann Lay
Date: Fri Nov 29 18:26:17 2024 +0100
AVR
This patch splits 2-byte and 3-byte shifts after reload into
a 3-operand byte shift and a residual 2-operand shift.
The "2op" shift insn alternatives are not needed and removed because
all shift insn already have a "r,0,n" alternative that does the job.
Ok for trunk?
Johann
--
AVR: target/11
Applied as obvious.
Johann
--
AVR: target/117744 - Fix asm for partial clobber of address reg,
gcc/
PR target/117744
* config/avr/avr.cc (out_movqi_r_mr): Fix code when a load
only partially clobbers an address register due to
changing the address register tempo
avr-common.cc used spaces for indentation instead of TABs.
Applied as obvious.
Johann
--
AVR: Tabify avr-common.cc according to coding rules.
gcc/
* common/config/avr/avr-common.cc: Tabify.AVR: Tabify avr-common.cc according to coding rules.
gcc/
* common/config/avr/avr-common
This patch is similar to https://gcc.gnu.org/r15-5569 (tweak ashift:SI)
but for
ashiftrt and lshiftrt codes. It splits constant shift offsets > 16
into a 3-operand byte shift and a 2-operand residual bit shift.
Moreover, some of the constraint alternatives have been promoted
to 3-operand alte
This is a no-op refactoring that uses a prefix of avropt_
(formerly: avr_) for variables defined qua Var() directives
in avr.opt. This makes it easier to spot values that come directly
from avr.opt in the rest of the backend.
Ok for trunk?
Johann
--
AVR: Use Var(avropt_xxx) for option variabl
This patch improves the 4-byte ASHIFT insns.
1) It adds a "r,r,C15" alternative for improved long << 15.
2) It adds 3-operand alternatives (depending on options) and
splits them after peephole2 / before avr-fuse-move into
a 3-operand byte shift and a 2-operand residual bit shift.
For better
Am 18.11.24 um 09:03 schrieb Georg-Johann Lay:
Am 16.11.24 um 13:19 schrieb Gerald Pfeifer:
On Mon, 2 Sep 2024, Georg-Johann Lay wrote:
Atmel is no more the AVR manufacturer. This patch removes the
manufacturer from the file headers.
We also have
AVR
Manufacturer: Atmel
href
Now that the C default is C23, we can use bool in avr.h
(which is still used in libgcc via tm.h).
bool is a keyword in C23, so no stdbool.h is required in libgcc.
No regressions. Ok for trunk?
Johan
--
AVR: Use more bool.
Now that the C default is C23, we can use bool in avr.h
(which is still
This patch calculates more accurate shift costs, but makes
the costs for larger offsets no more expensive than the costs
for an unrolled shift.
Ok for trunk?
Johann
--
AVR: target/54378 - Reconsider the default shift costs.
This patch calculates more accurate shift costs, but makes
the costs
/pr116488.c: Require int32plus.
* gcc.dg/torture/pr116915.c: Require int32plus.commit 780720f04b0b83261d6073b92f3b02e8fbef41b9
Author: Georg-Johann Lay
Date: Tue Nov 19 19:32:24 2024 +0100
testsuite/52641 - Skip test cases that are not 16-bit clean.
gcc/testsuite
Am 19.11.24 um 14:48 schrieb Georg-Johann Lay:
Am 19.11.24 um 13:31 schrieb Andreas Schwab:
../../gcc/config/avr/avr-passes.cc: In member function ‘void
{anonymous}::memento_t::apply_insn1(rtx_insn*, bool)’:
../../gcc/config/avr/avr-passes.cc:2119:9: error: no match for
‘operator&=’ (ope
Am 19.11.24 um 13:31 schrieb Andreas Schwab:
../../gcc/config/avr/avr-passes.cc: In member function ‘void
{anonymous}::memento_t::apply_insn1(rtx_insn*, bool)’:
../../gcc/config/avr/avr-passes.cc:2119:9: error: no match for ‘operator&=’
(operand types are ‘{anonymous}::gprmask_t’ {aka ‘unsigned
This patch adds 3-operand alternatives to the shift insns for
offsets that are one less than the bit-size of the mode.
For example, ashrhi3 can support "r,r,C15" without overhead.
Apart from that, the asm out functions for the shifts now use
avr_asm_len to print assembly and to track the isnsns' l
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