de would
produce redundant vector instructions.
Tested on risc-v 64 and risc-v 32, no regressions.
PS. In the vector instruction example there are two add instructions
working on the stack pointer register. I'm not quite sure about the
purpose of these instructions.
2024-31-11 Dusan Stojkovi
I accidentally forgot to include RISC-V in the title of the patch.
Please ignore this patch since I have sent a fixed one.
https://gcc.gnu.org/pipermail/gcc-patches/2024-October/664305.html
Sorry for the inconvenience.
From: Dusan Stojkovic
Sent: Wednesday
; situation change with that applied?
Repeated the testing for sifive-7-series as well as rocket. The same tests are
still effected positively: vsetvlmax-9, vsetvlmax-10, vsetvlmax-11, vsetvlmax-15
on sifive-7-series.
2024-10-2 Dusan Stojkovic
PR target/113035
gcc/ChangeLog:
; situation change with that applied?
Repeated the testing for sifive-7-series as well as rocket. The same tests are
still effected positively: vsetvlmax-9, vsetvlmax-10, vsetvlmax-11, vsetvlmax-15
on sifive-7-series.
2024-10-2 Dusan Stojkovic
PR target/113035
gcc/ChangeLog:
; situation change with that applied?
Repeated the testing for sifive-7-series as well as rocket. The same tests
are still effected positively: vsetvlmax-9, vsetvlmax-10, vsetvlmax-11,
vsetvlmax-15
on sifive-7-series.
2024-10-2 Dusan Stojkovic
PR target/113035
gcc/ChangeLog:
[a-x0-9]+,\\s*zero,\\s*e32,\\s*m1,\\s*t[au],\\s*m[au] 1
tests in previously mentioned files are now passing.
2024-09-10 Dusan Stojkovic
PR target/113035 - RISC-V: regression testsuite errors -mtune=sifive-7-series
PR target/113035
gcc\ChangeLog:
* config/riscv/riscv-vset
