[PATCH] RISC-V: Add testcase for unsigned scalar SAT_ADD form 8 and form 9

e__((noinline)) \ sat_u_add_##T##_fmt_9(T x, T y) \ { \ return x > (T)(x + y) ? -1 : (x + y); \ } Passed the rv64gc regression test. Signed-off-by: Ciyan Pan gcc/testsuite/ChangeLog: * gcc.target/ris

[PATCH] RISC-V: Add testcase for unsigned scalar SAT_ADD form 8 and form 9

e__((noinline)) \ sat_u_add_##T##_fmt_9(T x, T y) \ { \ return x > (T)(x + y) ? -1 : (x + y); \ } Passed the rv64gc regression test. Signed-off-by: Ciyan Pan gcc/testsuite/ChangeLog: * gcc.target/ris

[PATCH] RISC-V: Add testcase for unsigned scalar SAT_ADD form 8 and form 9

ine)) \ sat_u_add_##T##_fmt_9(T x, T y) \ {\ return x > (T)(x + y) ? -1 : (x + y); \ } Passed the rv64gc regression test. Signed-off-by: Ciyan Pan gcc/testsuite/ChangeLog: * gcc.target/riscv/sat/sat_arith.h: Un

[PATCH] RISC-V: Add testcases for unsigned vector SAT_SUB form 11 and form 12

flow ? ret : 0; \ } \ } Passed the rv64gcv regression test. Signed-off-by: Ciyan Pan gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h: Add unsigned vector SAT_SUB form11 and form12. * gcc.target/riscv/rvv/autovec/sat/vec_sat_data.h: Use ussub in

[PATCH] RISC-V: Add testcases for unsigned vector SAT_SUB form 11 and form 12

flow ? ret : 0; \ } \ } Passed the rv64gcv regression test. Signed-off-by: Ciyan Pan gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h: Add unsigned vector SAT_SUB form11 and form12. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u16.c: New test.

[PATCH] RISC-V: Adjust testdata for unsigned vector SAT_SUB

From: panciyan This patch adjust test data for unsigned vector SAT_SUB to vec_sat_data.h Passed the rv64gcv regression test. Signed-off-by: Ciyan Pan gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h: Add vec_sat_u_sub_fmt wrap define. * gcc.target

[PATCH] RISC-V: Add testcases for unsigned vector SAT_SUB form 11 and form 12

flow ? ret : 0; \ } \ } Passed the rv64gcv regression test. Signed-off-by: Ciyan Pan gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h: Add unsigned vector SAT_SUB form11 and form12. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u16.c: New test.

[PATCH v2 2/2] RISC-V: Add testcases for signed scalar SAT_ADD IMM form 2

); \ return ((x ^ sum) < 0 && (x ^ IMM) >= 0) ? \ (-(T)(x < 0) ^ MAX) : sum; \ } Passed the rv64gcv regression test. Signed-off-by: Ciyan Pan gcc/testsuite/ChangeLog: * gcc.target/riscv/sat/sat_ar

[PATCH 1/2] Match: Support for signed scalar SAT_ADD IMM form 2

The below test suites are passed for this patch: 1. The rv64gcv fully regression tests. 2. The x86 bootstrap tests. 3. The x86 fully regression tests. Signed-off-by: Ciyan Pan gcc/ChangeLog: * match.pd: --- gcc/match.pd | 13 - 1 file changed, 12 insertions(+), 1 deleti

[PATCH 2/2] RISC-V: Add testcases for signed scalar SAT_ADD IMM form 2

); \ return ((x ^ sum) < 0 && (x ^ IMM) >= 0) ? \ (-(T)(x < 0) ^ MAX) : sum; \ } Passed the rv64gcv regression test. Signed-off-by: Ciyan Pan gcc/testsuite/ChangeLog: * gcc.target/risc

[PATCH] Match:Support for signed scalar SAT_ADD IMM form 2

The below test suites are passed for this patch: 1. The rv64gcv fully regression tests. 2. The x86 bootstrap tests. 3. The x86 fully regression tests. Signed-off-by: Ciyan Pan gcc/ChangeLog: * match.pd: gcc/testsuite/ChangeLog: * gcc.target/riscv/sat/sat_arith.h: