Re: [PATCH] PR rtl-optimization/64081: Enable RTL loop unrolling for duplicated exit blocks and back edges.

Hi, Here is a quick status update. (Which comes a bit late due to bisection efforts) This patch still causes bootrstrap failure on AIX when applied on top of r219827. I tried to bisect first commit eliminating AIX problem - it may be useful anyway - but my current results seem misleading. Therefor

Re: [PATCH] PR rtl-optimization/64081: Enable RTL loop unrolling for duplicated exit blocks and back edges.

On Sat, Feb 06, 2016 at 12:42:49PM -0700, Jeff Law wrote: > On 02/06/2016 12:08 PM, David Edelsohn wrote: > > >>Normally I'd say that if it was approved before, then it's still good to go > >>since there haven't been major conceptual changes in this code since the > >>patch was originally written

[PATCH] PR rtl-optimization/64081: Enable RTL loop unrolling for duplicated exit blocks and back edges.

Hi! Some kind of this patch was submitted about a year ago by Igor Zamyatin. It's an attempt to fix PR rtl-optimization/64081 by enabling RTL loop unrolling for duplicated exit blocks and back edges. At the time it caused AIX bootstrap failure, but now it's OK according to David's testing. I've a

Re: [PATCH, i386, AVX512] PR target/67895: Fix position of embedded rounding/SAE mode in AVX512 vrangep* and vcvt?si2s* instructions.

I've bootstrapped and regtested it against GCC v5 on x86_64-gnu-linux. OK for 5-branch? -- Thanks, Alexander On Fri, Oct 09, 2015 at 05:24:56PM +0300, Kirill Yukhin wrote: > Hello, > On 08 Oct 20:31, Alexander Fomin wrote: > > Hi All, > > > > This patch addres

Re: [PATCH, i386, AVX512] PR target/69228: Restrict default masks for prefetch gathers/scatters instructions.

Now bootstrapped and regtested against GCC v5. OK for 5-branch thus? Regards, Alexander On Wed, Jan 13, 2016 at 03:41:26PM +0300, Kirill Yukhin wrote: > Hello Sasha, > On 12 Jan 14:57, Alexander Fomin wrote: > > This patch addresses PR target/69228. Expanding non-mask builtins >

Re: [PATCH, i386, AVX512] PR target/67895: Fix position of embedded rounding/SAE mode in AVX512 vrangep* and vcvt?si2s* instructions.

Hi, Still not backported into 5-branch. Could you please handle it? Thanks, Alexander On Fri, Oct 09, 2015 at 05:24:56PM +0300, Kirill Yukhin wrote: > Hello, > On 08 Oct 20:31, Alexander Fomin wrote: > > Hi All, > > > > This patch addresses PR target/67895. For

Re: [PATCH, i386, AVX512] PR target/69228: Restrict default masks for prefetch gathers/scatters instructions.

Checked into main trunk. Could you please backport it to 5-branch? Regards, Alexander On Wed, Jan 13, 2016 at 03:41:26PM +0300, Kirill Yukhin wrote: > Hello Sasha, > On 12 Jan 14:57, Alexander Fomin wrote: > > This patch addresses PR target/69228. Expanding non-mask builtins >

[PATCH, i386, AVX512] PR target/69228: Restrict default masks for prefetch gathers/scatters instructions.

This patch addresses PR target/69228. Expanding non-mask builtins for prefetch gather/scatter insns results in using default mask. Although Intel ISA Extensions Programming Reference statement about EVEX.aaa field in prefetch gather/scatter insns encoding is a bit opaque, no default mask is allowed

[PATCH][COMMITTED] PR target/67895: Fix embedded rounding/SAE specifier position for some AVX512 instructions.

Committed to trunk in r228660. Thanks, Alexander --- gcc/ PR target/67895 * config/i386/sse.md (define_insn "sse_cvtsi2ss"): Adjust embedded rounding/SAE specifier position. (define_insn "sse_cvtsi2ssq"): Likewise. (define_insn "cvtusi232"): Likewise.

[COMMITTED] Add myself to MAINTAINERS (Write After Approval)

trunk/ChangeLog (working copy) @@ -1,3 +1,7 @@ +2015-10-09 Alexander Fomin + + * MAINTAINERS (Write After Approval): Add myself. + 2015-10-02 Florian Weimer * MAINTAINERS: Update email address. Index: MAINTAINERS ===

[PATCH, i386, AVX512] PR target/67895: Fix position of embedded rounding/SAE mode in AVX512 vrangep* and vcvt?si2s* instructions.

Hi All, This patch addresses PR target/67895. For some AVX512 instructions we've used to emit embedded rounding/SAE specifier in a wrong place. The patch fixes its position for vrange* and vcvt?si2s* instructions. I've also updated regular expressions for corresponding assembly in i386 testsuite,

Re: [PATCH, i386, AVX512] PR target/67849: Avoid upper-bank registers when splitting vec_extract_lo instruction.

On Tue, Oct 06, 2015 at 03:23:39PM +0300, Kirill Yukhin wrote: > Hi, > On 05 Oct 18:01, Uros Bizjak wrote: > > On Mon, Oct 5, 2015 at 5:54 PM, Alexander Fomin > > wrote: > > > This patch addresses PR target/67849. Given a machine that does not > > > support A

[PATCH, i386, AVX512] PR target/67849: Avoid upper-bank registers when splitting vec_extract_lo instruction.

This patch addresses PR target/67849. Given a machine that does not support AVX512VL, following "else" branch for vec_exract_lo insn may result in a split using YMMs from upper-bank, hence invalid assembly. Tuning define_insn pattern and define_split constraints eliminates this problem. Please tak

Re: [PATCH] PR target/67480: AVX512 bitwise logic insns pattern is incorrect

Hi, On Tue, Sep 08, 2015 at 11:41:50AM +0300, Kirill Yukhin wrote: > Hi, > On 07 Sep 19:07, Alexander Fomin wrote: > > + tmp = TARGET_AVX512VL ? "p" : "p"; > Suppose masking is applied and 1st alternative chosen... > > + ops = "%s\t{%%

[PATCH] PR target/67480: AVX512 bitwise logic insns pattern is incorrect

This patch adresses PR target/67480. As there are no bitwise logic instructions for BYTE/WORD in AVX512, we should split corresponding pattern into two different patterns, namely: (a) any bitwise logic, for SI/DI modes, masking is supported; (b) any bitwise logic, for QI/HI modes, maski