[PATH 6/6] RISC-V: Add pass to delete redundancy vsetvl insn

gcc/ChangeLog: * config.gcc (extra_objs): Include vector pass. * config/riscv/t-riscv : Likewise. * config/riscv/riscv-pass.c : New. * config/riscv/riscv.opt (-mdelete-vsetvl): Likewise. --- gcc/config.gcc| 2 +- gcc/config/riscv/riscv-pass.c | 19

[PATH 3/6] RISC-V: Add vector VLEN and SEW

gcc/ChangeLog: * config/riscv/riscv-c.c (__riscv_vector): Define. * config/riscv/riscv-opts.h (riscv_vlen): New. * config/riscv/riscv-v.h (TARGET_VECTOR_VLEN): Define. (UNITS_PER_VR_REG): Likewise. (RISCV_VSEW_T): Likewise. * config/riscv/riscv.opt (

[PATH 2/6] RISC-V: Add vector register

gcc/ChangeLog: * config/riscv/riscv-v.h: New. * config/riscv/riscv.h (FIRST_PSEUDO_REGISTER): Add vector register. (FIRST_PSEUDO_REGISTER): Likewise. (CALL_USED_REGISTERS): Likewise. (reg_class): Likewise. (REG_CLASS_NAMES): Likewise. (REG_CL

[PATH 1/6] RISC-V: Add vector mask

- The first version for vector extension and verified on rv64imafdcv linux target with qemu. gcc/ChangeLog: * common/config/riscv/riscv-common.c: Parse vector extension. * config/riscv/riscv.opt (TARGET_VECTOR): New. --- gcc/common/config/riscv/riscv-common.c | 4 gcc/confi