Grml, this is turning into a rabbit hole.
The initial plan was to "just" support the widening shift optab for riscv.
This patch here was supposed to be the first step. The next patch adds support
for n-n (SLP style) widening ops.
But I'm realizing now that we should actually have all the checki
Hi,
Based on the approach mentioned by Andrew, below is a patch to fix PR122126.
Bootstrapped and regtested on powerpc64le and x86 with no regressions. Kindly
review.
Thanks and regards,
Avinash Jayakar
The function gimple_expand_vec_set_expr in the isel pass, converted
VIEW_CONVERT_EXPR to VEC_
> -Original Message-
> From: Tejas Belagod
> Sent: 04 November 2025 12:28
> To: [email protected]
> Cc: Tejas Belagod ; Tamar Christina
> ; [email protected]; [email protected]
> Subject: [PATCH v4 3/3] AArch64: Update test to reflect new message
>
> Update test error message as sv
> -Original Message-
> From: Tejas Belagod
> Sent: 04 November 2025 12:28
> To: [email protected]
> Cc: Tejas Belagod ; Tamar Christina
> ; [email protected]; [email protected]
> Subject: [PATCH v4 2/3] AArch64: Update existing test with svbool_t
> operations
>
> Update existing compi
> -Original Message-
> From: Tejas Belagod
> Sent: 04 November 2025 12:28
> To: [email protected]
> Cc: Tejas Belagod ; Tamar Christina
> ; [email protected]; [email protected]
> Subject: [PATCH v4 1/3] AArch64: Support C/C++ operations on svbool_t
>
> Support a subset of C/C++ operat
From: Pan Li
There are 3 kinds of widen_mul during the unsigned SAT_MUL pattern, aka
* widen_mul directly, like _3 w* _4
* convert and the widen_mul, like (uint64_t)_3 *w (uint64_t)_4
* convert and then mul, like (uint64_t)_3 * (uint64_t)_4
All of them will be referenced during different forms o
On Wed, Nov 5, 2025 at 6:54 AM Andrew MacLeod wrote:
>
> On 11/5/25 04:55, Richard Biener wrote:
> > This clarifies the constraints of the immediate use iterators,
> > documenting how exactly stmts and their immediate uses might be
> > altered during it.
> >
> > I have bootstrapped and tested the
Let's consider this code fragment (from xalan):
bool isValidAncestorType(int type) {
if (type == 0 || type == 6 || type == 4) {
return true;
}
return false;
}
Right now it generates something like this for RISC-V with Zicond enabled:
li a5,6
bgtu
Since libgrust/rustc-lib/stdarch is a library copied from rustc, we
should include the directory in ignored_prefixes.
contrib/ChangeLog:
* gcc-changelog/git_commit.py (ignored_prefixes): Add
'libgrust/rustc-lib/stdarch/'.
Signed-off-by: Owen Avery
---
contrib/gcc-changelog/git_
This patch adds support for the BigObj COFF object file format to libiberty's
simple-object-coff.c. BigObj extends regular COFF to support a 32-bit section
count.
BigObj differs from COFF in a few ways:
* A different header structure
* 32-bit section counts instead of 16-bit
* 32-bit symbol secti
On 11/5/25 11:42 PM, Peter0x44 wrote:
Nov 5, 2025 11:40:46 PM Jonathan Yong <[email protected]>:
On 10/31/25 4:28 PM, LIU Hao wrote:
在 2025-10-31 19:53, Richard Biener 写道:
On Fri, Oct 31, 2025 at 12:34 PM Peter0x44 wrote:
On 2025-10-31 08:40, Richard Biener wrote:
On Fri, Oct 31, 2025 at
On Wed, Nov 05, 2025 at 11:32:39PM +0100, Christopher Albert wrote:
> On Wed, 5 Nov 2025 13:36:59 -0800
> Steve Kargl wrote:
>
> > On Wed, Nov 05, 2025 at 10:30:57PM +0100, Christopher Albert wrote:
> > >
> > > Sorry, some trouble with email client. I try claws-mail now and
> > > attach the diff
Nov 5, 2025 11:40:46 PM Jonathan Yong <[email protected]>:
> On 10/31/25 4:28 PM, LIU Hao wrote:
>> 在 2025-10-31 19:53, Richard Biener 写道:
>>> On Fri, Oct 31, 2025 at 12:34 PM Peter0x44 wrote:
On 2025-10-31 08:40, Richard Biener wrote:
> On Fri, Oct 31, 2025 at 2:25 AM Peter Damiano
On 10/31/25 4:28 PM, LIU Hao wrote:
在 2025-10-31 19:53, Richard Biener 写道:
On Fri, Oct 31, 2025 at 12:34 PM Peter0x44 wrote:
On 2025-10-31 08:40, Richard Biener wrote:
On Fri, Oct 31, 2025 at 2:25 AM Peter Damianov
wrote:
This patch adds support for the BigObj COFF object file format to
l
On Wed, Nov 05, 2025 at 04:59:12PM +, Joseph Myers wrote:
> On Wed, 5 Nov 2025, Michael Meissner wrote:
>
> > On Wed, Nov 05, 2025 at 10:02:05AM +0100, Jakub Jelinek wrote:
> > > On Wed, Nov 05, 2025 at 03:53:15AM -0500, Michael Meissner wrote:
> > > > This patch adds the necessary support in
Print the record associated with the PATHS tag. While it just prints
the number of prime paths for the function, this is more useful than
the UNKNOWN it would otherwise print.
Before:
...
demo.gcno:0145: 31:LINES
demo.gcno: block 6:`demo.c':13
demo.gcno:0149: 4
The --coverage flag is a useful alias for -fprofile-arcs
-ftest-coverage where the latter makes gcc output the .gcno file.
While it makes sense to use -fprofile-arcs without a .gcno file (pgo,
maybe more), it never really makes sense to request -fpath-coverage or
-fcondition-coverage without also w
This test has been failing since this commit which introduces an extra
block in the loop, increasing the number of prime paths:
FAIL: gcc.misc-tests/gcov-29.c line 826: expected 0/5 covered paths, was 0/6
commit 385d9937f0e23cbf9c62f0b2553a33ff70e56ecf
Author: Jan Hubicka
Date: Fri Jul 11 13:0
The printed position should be the start of the record, as is the case
with lines.
Before:
ex.gcno: 795:0147: 16:CONDITIONS 2 conditions
ex.gcno: 811: block 2: 1
ex.gcno: 819: block 5: 1
ex.gcno: 819:0100: 50:FUNCTION ... `main' ...
After:
e
Fixes a regression introduced I bisected to this commit:
commit 385d9937f0e23cbf9c62f0b2553a33ff70e56ecf
Author: Jan Hubicka
Date: Fri Jul 11 13:01:13 2025 +0200
Rewrite assign_discriminators
That patch adds discriminators to edge->goto_locus which will map to
the right source location, bu
Hi,
These patches are a mix of features, bugfixes, and quality of life
improvements.
* fixes a wrong line count when multiple blocks touch the same line
* -fpath-coverage and -fcondition-coverage implies -ftest-coverage
(.gcno, a prerequisite for running gcov)
* gcov-dump prints paths and the
On Wed, 5 Nov 2025 13:36:59 -0800
Steve Kargl wrote:
> On Wed, Nov 05, 2025 at 10:30:57PM +0100, Christopher Albert wrote:
> > On Wed, 5 Nov 2025 13:12:04 -0800
> > Steve Kargl wrote:
> >
> > > On Sun, Nov 02, 2025 at 02:20:59PM +0100, Christopher Albert
> > > wrote:
> > > > Rebased again o
On Wed, Nov 05, 2025 at 10:30:57PM +0100, Christopher Albert wrote:
> On Wed, 5 Nov 2025 13:12:04 -0800
> Steve Kargl wrote:
>
> > On Sun, Nov 02, 2025 at 02:20:59PM +0100, Christopher Albert wrote:
> > > Rebased again on trunk with small corrections, correct text format
> > > directly pasted in
On Wed, 5 Nov 2025 13:12:04 -0800
Steve Kargl wrote:
> On Sun, Nov 02, 2025 at 02:20:59PM +0100, Christopher Albert wrote:
> > Rebased again on trunk with small corrections, correct text format
> > directly pasted in the e-mail and without attachments (sorry for
> > the mess before, I'm new to to
On Sun, Nov 02, 2025 at 02:20:59PM +0100, Christopher Albert wrote:
> Rebased again on trunk with small corrections, correct text format directly
> pasted in the e-mail and without attachments (sorry for the mess before, I'm
> new to to the GCC patch workflow). Tested on x86_64 by Stefan Kargl on
>
On Thu, Oct 23, 2025 at 07:25:17PM +0530, Surya Kumari Jangala wrote:
> Hi Mike,
>
> On 23/09/25 3:32 am, Michael Meissner wrote:
> > See https://gcc.gnu.org/pipermail/gcc-patches/2025-September/695920.html for
> > (struct rs6000_cpu_opt_mask): Likewise.
>
> 'Likewise' is incorrect here. 'New
The RM 3.8(12/3) subclause says that a discriminant mentioned in a constraint
must appear alone as a direct name. The last part is not consistently checked
and, while the first part is, it generates a slightly different error message
depending on the form of the input.
This fixes the last part
On 28/10/2025 13:51, Richard Biener wrote:
On Tue, 28 Oct 2025, Christopher Bazley wrote:
vect_create_constant_vectors is updated to pad with zeros
between the end of a group and the end of a vector of the type
chosen for the SLP node, when used for BB SLP. This function
calls gimple_build_ve
On Wed, 5 Nov 2025, Michael Meissner wrote:
> On Wed, Nov 05, 2025 at 10:02:05AM +0100, Jakub Jelinek wrote:
> > On Wed, Nov 05, 2025 at 03:53:15AM -0500, Michael Meissner wrote:
> > > This patch adds the necessary support in libgcc to allow using the machine
> > > independent 16-bit floating poin
Recently, I wrote a neovim plugin for myself that automates/facilitates
common dejagnu testsuite tasks for c++ frontend bug fixing:
- Searching/executing tests from within neovim
- Extracting cc1plus invocations from xg++ for GDB debugging
- Running testsuite cases with proper libstdc++ inclu
Ping!
Please review.
Thanks,
Avinash Jayakar
On Fri, 2025-10-24 at 14:45 +0530, Avinash Jayakar wrote:
> Hi Segher,
>
> Please ignore the v7 patch, had minor errors in capitalization.
> Thanks for the review of the v6 patch. I have incorporated all the
> mentioned
> changes in this patch.
> Boo
From: Richard Ball
This patch adds support for the __pldir intrinsic.
This is a new prefetch intrinsic which declares an
intent to read from an address.
This intrinsic is part of FEAT_PCDPHINT.
gcc/ChangeLog:
* config/aarch64/aarch64-builtins.cc
(enum aarch64_builtins): New buil
From: Richard Ball
This patch series adds support for FEAT_PCDPHINT,
this includes two patches. The first adds a new atomic_store
intrinsic that generates an STSHH hint instruction immmediately
before the store instruction. The second adds a new prefetch
intrinsic, that is used to declare an inte
From: Richard Ball
This patch adds support for the atomic_store_with_stshh intrinsic
in aarch64. This intrinsic is part of FEAT_PCDPHINT.
gcc/ChangeLog:
* config/aarch64/aarch64-builtins.cc
(enum aarch64_builtins): Add new flags.
(aarch64_init_pcdphint_builtins): Create
On Wed, Nov 05, 2025 at 09:56:21AM -0500, Michael Meissner wrote:
> On Wed, Nov 05, 2025 at 10:34:37AM +0100, Jakub Jelinek wrote:
> > On Wed, Nov 05, 2025 at 03:48:46AM -0500, Michael Meissner wrote:
> > > This set of patches is a request for comments (RFC) on the support to
> > > add 16-bit float
On Wed, Nov 05, 2025 at 10:34:37AM +0100, Jakub Jelinek wrote:
> On Wed, Nov 05, 2025 at 03:48:46AM -0500, Michael Meissner wrote:
> > This set of patches is a request for comments (RFC) on the support to
> > add 16-bit floating point support to the GCC 16 PowerPC. In GCC 16, I
> > anticipate this
> diff --git a/gcc/common/config/riscv/Makefile
> b/gcc/common/config/riscv/Makefile
> new file mode 100644
> index 000..471dcc9faed
> --- /dev/null
> +++ b/gcc/common/config/riscv/Makefile
> @@ -0,0 +1,10 @@
> +all: riscv-arch-canonicalize
> +
> +riscv-arch-canonicalize: riscv-arch-canoni
On 11/5/25 04:55, Richard Biener wrote:
This clarifies the constraints of the immediate use iterators,
documenting how exactly stmts and their immediate uses might be
altered during it.
I have bootstrapped and tested the series on x86_64-unknown-linux-gnu,
the prerequesites have been pushed.
Do
This patch implements a new RTL pass that combines "li a0, 0" and
"cm.popret" into a single "cm.popretz" instruction for the Zcmp
extension.
This optimization cannot be done during prologue/epilogue expansion
because it would cause shrink-wrapping to generate incorrect code as
documented in PR1137
On 28/10/2025 13:29, Richard Biener wrote:
On Tue, 28 Oct 2025, Christopher Bazley wrote:
+tree
+vect_slp_get_bb_mask (slp_tree slp_node, gimple_stmt_iterator *gsi,
+ unsigned int nvectors, tree vectype, unsigned int index)
+{
+ gcc_checking_assert (SLP_TREE_CAN_USE_MASK_
On functional safety devices (AVR-SD), each executed instruction must
be followed by a valid opcode. This is because instruction fetch and
decode for the next instruction runs while the 2-stage pipeline is
executing the current instruction.
There is only one case where avr-gcc generates code int
From: Christophe Lyon
Implement sqrshrl and sqrshrl_sat48 using the new MVE builtins
framework.
gcc/ChangeLog:
* config/arm/arm-mve-builtins-base.cc (enum which_scalar_shift):
Add ss_SQRSHRL, ss_SQRSHRL_SAT48.
(mve_function_scalar_shift): Add support for ss_SQRSHRL,
From: Christophe Lyon
Implement sqrshr, sqshl, srshr, uqrshl, uqshl and urshr using the new
MVE builtins framework.
The patch fixes a probable copy/paste typo in mve_sqshl_si and
mve_srshr_si: operand 1 should have mode SI, and not DI.
gcc/ChangeLog:
* config/arm/arm-mve-builtins-base
From: Christophe Lyon
This helper is not needed anymore, so remove it.
gcc/ChangeLog:
* config/arm/arm_mve.h (__ARM_undef): Delete.
(__ARM_mve_coerce): Delete.
(__ARM_mve_coerce_i_scalar): Delete.
(__ARM_mve_coerce_s8_ptr): Delete.
(__ARM_mve_coerce_u8_pt
From: Christophe Lyon
Implement sqshll, srshrl, uqshll and urshrl using the new MVE builtins
framework.
gcc/ChangeLog:
* config/arm/arm-mve-builtins-base.cc (enum which_scalar_shift):
Add ss_SQSHLL, ss_SRSHRL, ss_UQSHLL, ss_URSHRL.
(mve_function_scalar_shift): Add suppor
From: Christophe Lyon
Implement asrl and lsll using the new MVE builtins framework.
gcc/ChangeLog:
PR target/122216
* config/arm/arm-mve-builtins-base.cc (enum which_scalar_shift): New.
(mve_function_scalar_shift): New.
(asrl, lsll): New.
* config/arm/ar
From: Christophe Lyon
Implement vgetq_lane and vsetq_lane using the new MVE builtins
framework.
Although MVE intrinsics are not supported in big-endian mode, we keep
the code to convert lane indices into GCC's vector indices, so that
it's already in place in case we want to support big-endian i
From: Christophe Lyon
The thumb2_asrl, thumb2_lsll and thumb2_lsrl patterns were incorrecly
using (match_dup 0) for the first argument of the shift operator.
This patch replaces that with (match_operand:DI 1
arm_general_register_operandarm_general_register_operand "0") and
fixes the related exp
From: Christophe Lyon
Implement uqrshll and uqrshll_sat48 using the new MVE builtins
framework.
gcc/ChangeLog:
* config/arm/arm-mve-builtins-base.cc (enum which_scalar_shift):
Add ss_UQRSHLL, ss_UQRSHLL_SAT48.
(mve_function_scalar_shift): Add support for ss_UQRSHLL,
From: Christophe Lyon
The previous patch makes __fp16 always available on arm (using
-mfp16-format is no longer needed), so the documentation needs an
update.
In the process, clarify the peculiarities of __fp16 on arm, and
reorder information to make it easier to understand.
gcc/ChangeLog:
From: Christophe Lyon
MVE asrl and lsll instructions have two variants:
- immediate shift amount in the [1..32] range
- shift amount in a register, where negative values reverse the
direction of the shift
However, RTL assumes that the shift amount is interpreted unsigned, so
we want to make s
From: Christophe Lyon
Implement vuninitialized using the new MVE builtins framework.
Introduce a new inherent1 shape to support 'vuninitializedq' with no
type suffix, where the expected type is taken from the first argument.
This can only work in C++, because C does not support such overloading
From: Christophe Lyon
This patch adds the scalar_s64_shift and scalar_u64_shift shape
descriptions.
gcc/ChangeLog:
PR target/122216
* config/arm/arm-mve-builtins-shapes.cc (scalar_s64_shift): New.
(scalar_u64_shift): New.
* config/arm/arm-mve-builtins-shapes.h:
From: Christophe Lyon
If the target does not support floating-point, we register FP vector
types as 'void' (see register_vector_type).
This leads to warnings about 'pure attribute on function returning
void' when we declare the various load intrinsics because their
call_properties say CP_READ_M
From: Christophe Lyon
Implement vpnot using the new MVE builtins framework.
gcc/ChangeLog:
* config/arm/arm-mve-builtins-base.cc (class mve_function_vpnot): New.
(vpnot): New.
* config/arm/arm-mve-builtins-base.def (vpnot): New.
* config/arm/arm-mve-builtins-bas
Hi gcc-patches mailing list,
Christophe Lyon has requested that the following forgejo
pull request
be published on the mailing list.
Created on: 2025-11-05 13:54:48+00:00
Latest update: 2025-11-05 14:03:53+00:00
Changes: 49 changed files, 1787 additions, 794 deletions
Head revision: clyon/gcc-TE
On 11/5/25 12:01 PM, Nathaniel Shead wrote:
On Tue, Nov 04, 2025 at 12:57:53PM +0300, Jason Merrill wrote:
On 10/30/25 3:00 PM, Nathaniel Shead wrote:
One unfortunate side effect of this is that even with -pedantic-errors,
unless the user specifies '-Wtemplate-names-tu-local' when building the
Hi All,
The fix for this one was essentially a one-liner, apart from the
indentation changes. The possibility that PDTs could extend non-PDTs
was forgotten in the original implementation.
The fix was sufficiently 'obvious, that it was pushed as r16-5045.
Paul
Change.Logs
Description: Binary da
Pushed to mainline as r16-5044.
Thanks for the review and testing.
Paul
On Tue, 4 Nov 2025 at 20:16, Jerry D wrote:
>
> On 11/4/25 6:23 AM, Paul Richard Thomas wrote:
> > Hi All,
> >
> > It turned out that attempting to pick out specific interfaces for PDT
> > constructors in primary.cc was way
On Tue, 4 Nov 2025, Christopher Bazley wrote:
> On 28/10/2025 13:29, Richard Biener wrote:
> >> +/* Materialize mask number INDEX for a group of scalar stmts in SLP_NODE
> >> that
> >> + operate on NVECTORS vectors of type VECTYPE, where 0 <= INDEX <
> >> NVECTORS.
> >> + Masking is only requi
On Tue, 4 Nov 2025, Christopher Bazley wrote:
>
> On 04/11/2025 13:57, Christopher Bazley wrote:
> > On 28/10/2025 13:29, Richard Biener wrote:
> >> Isn't SLP_TREE_CAN_USE_PARTIAL_VECTORS_P redundant given
> >> SLP_TREE_CAN_USE_MASK_P || SLP_TREE_CAN_USE_LEN_P should be exactly this?
> >>
> >> SL
Committed as r16-5043-gdd62c97f1227d3.
I think it was me who messed up the removal code of
r16-4540-g80af807e52e4f4
OpenMP: Handle non-executable directives in intervening
code [PR120180,PR122306]
In any case, it wasn't quite right, which caused compile
fails. - The attached and committed
On Tue, Nov 4, 2025 at 4:00 PM Robin Dapp wrote:
>
> Hi,
>
> Similar to the signed/unsigned patch before this one relaxes the
> gather/scatter restrictions on scale factors. The basic idea is that a
> natively unsupported scale factor can still be reached by emitting a
> multiplication before the
With USM, the testcase libgomp.c++/target-std__multimap-concurrent-usm.C
segfaults on the host in the destructor of the multimap _map.
Freeing device allocated memory on the device fixes this.
I intent to commit it later today, unless there are comments
implying otherwise.
Thanks,
Tobias
libgo
On Wed, 5 Nov 2025, Dhruv Chawla wrote:
> On 27/08/25 18:27, Richard Biener wrote:
> > External email: Use caution opening links or attachments
> >
> >
> > On Mon, 25 Aug 2025, [email protected] wrote:
> >
> >> From: Dhruv Chawla
> >>
> >> For ==, < and <=, the fold is to 0. For !=, > and >=,
SIG_IGN also needs to be defined according to the C++ standard.
This was missing in the test.
libstdc++-v3/testsuite/ChangeLog:
* 18_support/headers/csignal/macros.cc: New test.
Signed-off-by: Xavier Bonaventura
---
libstdc++-v3/testsuite/18_support/headers/csignal/macros.cc | 4
1 fi
"long long" and "unsinged long long" min and max macros were added in
C++11, but they were not present in the climits test.
libstdc++-v3/testsuite/ChangeLog:
* 18_support/headers/climits/values_c++11.cc: New test.
Signed-off-by: Xavier Bonaventura
---
.../testsuite/18_support/headers/climi
I modified the patch to make it in the same file
Bests,
Xavi
It has turned out the normal code model isn't enough for some large
LoongArch link units in practice. Quoting WANG Rui's comment [1]:
We’ve actually been considering pushing for a change to the default
code model for LoongArch compilers (including GCC) for a while now.
In fact, this was one of th
The following implements additional checking around
SSA immediate use iteration. Specifically this prevents
- any nesting of FOR_EACH_IMM_USE_STMT inside another iteration
via FOR_EACH_IMM_USE_STMT or FOR_EACH_IMM_USE_FAST when iterating
on the same SSA name
- modification (for now unlin
This is an attempt to fix PR122502 by making a FOR_EACH_IMM_USE_FAST
with in an FOR_EACH_IMM_USE_STMT on _the same_ VAR work without
the former running into the FOR_EACH_IMM_USE_STMT inserted marker
use operand. It does this by getting rid of the marker.
The downside is that this in principle res
From: Claudio Bantaloukas
This patch adds support for the following intrinsics when sme-f8f16 is enabled:
* svmla_lane_za16[_mf8]_vg2x1_fpm
* svmla_lane_za16[_mf8]_vg2x2_fpm
* svmla_lane_za16[_mf8]_vg2x4_fpm
* svmla_za16[_mf8]_vg2x1_fpm
* svmla[_single]_za
From: Claudio Bantaloukas
This patch adds the following intrinsics (all __arm_streaming only) along with
asm tests for them.
- FSCALE (multiple and single vector)
- svfloat16x2_t svscale[_single_f16_x2](svfloat16x2_t zd, svint16_t zm)
- svfloat32x2_t svscale[_single_f32_x2](svfl
From: Karl Meakin
This patch adds support for the following intrinsics when sme-f8f16 is enabled:
* svdot_za16[_mf8]_vg1x2_fpm
* svdot_za16[_mf8]_vg1x4_fpm
* svdot[_single]_za16[_mf8]_vg1x2_fpm
* svdot[_single]_za16[_mf8]_vg1x4_fpm
* svdot_lane_za16[_mf8]_
From: Claudio Bantaloukas
This patch adds support for FMOPA (widening, 2-way, FP8 to FP16) when
sme-f8f16 is enabled using svmopa_za16[_mf8]_m_fpm and for FMOPA (widening,
4-way) when sme-f8f32 is enabled using svmopa_za32[_mf8]_m_fpm.
Asm tests for the new intrinsics are added, similar to thos
From: Claudio Bantaloukas
This patch adds support for the SME_F8F16 and SME_F8F32 features as architecture
options, along with related definitions. This support is required for subsequent
intrinsics to work.
gcc/
* config/aarch64/aarch64.h:
(TARGET_STREAMING_SME_F8F16, TARGET_ST
Hi gcc-patches mailing list,
Claudio Bantaloukas has requested that the following
forgejo pull request
be published on the mailing list.
Created on: 2025-11-05 10:06:07+00:00
Latest update: 2025-11-05 10:24:33+00:00
Changes: 131 changed files, 14286 additions, 45 deletions
Head revision: rdfm/gc
From: Claudio Bantaloukas
This patch adds the following intrinsics (all __arm_streaming only) along with
asm tests for them.
BFCVT, FCVT Convert to packed 8-bit floating-point format:
- svmfloat8_t svcvt_mf8[_f16_x2]_fpm(svfloat16x2_t zn, fpm_t fpm)
- svmfloat8_t svcvt_mf8[_bf16_x2]_fpm(svbfloa
From: Claudio Bantaloukas
This patch adds the following intrinsics (all __arm_streaming only) along with
asm tests for them:
- svfloat16x2_t svcvt1_f16[_mf8]_x2_fpm(svmfloat8_t zn, fpm_t fpm)
- svfloat16x2_t svcvt2_f16[_mf8]_x2_fpm(svmfloat8_t zn, fpm_t fpm)
- svfloat16x2_t svcvt1_bf16[_mf8]_x2_
From: Claudio Bantaloukas
These functions could already support svmfloat8_t types but were missing tests.
This change uses the similar ones for uint8.
gcc/testsuite/
* gcc.target/aarch64/sme2/acle-asm/luti2_mf8_x2.c: New test.
* gcc.target/aarch64/sme2/acle-asm/luti2_mf8_x4.c: L
On Tue, 4 Nov 2025, Artemiy Volkov wrote:
> This is an attempt to fix
> https://gcc.gnu.org/pipermail/gcc-patches/2025-October/697879.html in the
> middle-end; the motivation in that patch was to teach gcc to compile:
>
> int16x8_t foo (int16x8_t x)
> {
> return vcombine_s16 (vget_high_s16 (x),
On Tue, 4 Nov 2025, Avinash Jayakar wrote:
> Hi,
>
> This is a follow-up to the previous patch I raised for fixing PR122065. Here I
> handle cases when vector constant is uniform, but may not be a power of 2.
> Bootstrapped and regtests on powerpc64le-linux. Kindly review.
>
> Thanks and regards
On Tue, Nov 04, 2025 at 12:57:53PM +0300, Jason Merrill wrote:
> On 10/30/25 3:00 PM, Nathaniel Shead wrote:
> > One unfortunate side effect of this is that even with -pedantic-errors,
> > unless the user specifies '-Wtemplate-names-tu-local' when building the
> > module interface there will be no
This clarifies the constraints of the immediate use iterators,
documenting how exactly stmts and their immediate uses might be
altered during it.
I have bootstrapped and tested the series on x86_64-unknown-linux-gnu,
the prerequesites have been pushed.
Does this look OK? If so I'll go ahead with
On Wed, Nov 05, 2025 at 03:48:46AM -0500, Michael Meissner wrote:
> This set of patches is a request for comments (RFC) on the support to
> add 16-bit floating point support to the GCC 16 PowerPC. In GCC 16, I
> anticipate this will be listed as an experimental feature, to allow
> the code to be r
On Tue, Nov 4, 2025 at 5:54 PM Kees Cook wrote:
>
> Implement x86_64-specific KCFI backend:
>
> - Implies -mindirect-branch-register since KCFI needs call target in
> a register for typeid hash loading.
>
> - Function preamble generation with type IDs positioned at -(4+prefix_nops)
> offset fr
This patch documents the -mfloat16 switch.
2025-11-05 Michael Meissner
gcc/
* doc/invoke.texi (RS/6000 and PowerPC Options): Document -mfloat16.
---
gcc/doc/invoke.texi | 36 +++-
1 file changed, 35 insertions(+), 1 deletion(-)
diff --git a/gcc/doc/in
From: Indu Bhagat
Add basic tests for memtag-stack sanitizer. Memtag stack sanitizer
uses target hooks to emit AArch64 specific MTE instructions.
gcc/testsuite:
* lib/target-supports.exp:
* gcc.target/aarch64/memtag/alloca-1.c: New test.
* gcc.target/aarch64/memtag/allo
From: Claudiu Zissulescu
Memory tagging is used for detecting memory safety bugs. On AArch64, the
memory tagging extension (MTE) helps in reducing the overheads of memory
tagging:
- CPU: MTE instructions for efficiently tagging and untagging memory.
- Memory: New memory type, Normal Tagged Mem
On Wed, Nov 05, 2025 at 10:02:05AM +0100, Jakub Jelinek wrote:
> On Wed, Nov 05, 2025 at 03:53:15AM -0500, Michael Meissner wrote:
> > This patch adds the necessary support in libgcc to allow using the machine
> > independent 16-bit floating point support.
>
> No exports from libgcc_s.so.1? Is th
From: Claudiu Zissulescu
Add a new target instruction. Hardware-assisted sanitizers on
architectures providing instructions to tag/untag memory can then
make use of this new instruction pattern. For example, the
memtag-stack sanitizer uses these instructions to tag and untag a
memory granule.
gc
From: Claudiu Zissulescu
MEMTAG sanitizer, which is based on the HWASAN sanitizer, will invoke
the target-specific hooks to create a random tag, add tag to memory
address, and finally tag and untag memory.
Implement the target hooks to emit MTE instructions if MEMTAG sanitizer
is in effect. Con
This patch adds basic vectorization support for _Float16 and
__bfloat16.
It does this by using expanders to generate the appropriate
vectorization code.
Note, _Float16 will only be vectorized if -Ofast is used (the machine
independent code does not do the expansion for smaller floating point
form
From: Claudiu Zissulescu
Add a new target instruction used by hardware-assisted sanitizers on
architectures providing memory-tagging instructions. This instruction
is used to compute assign tags at a fixed offset from a tagged address
base. For example, in AArch64 case, this pattern instantiate `
From: Indu Bhagat
Add new command line option -fsanitize=memtag-stack with the following
new params:
--param memtag-instrument-alloca [0,1] (default 1) to use MTE insns
for enabling dynamic checking of stack allocas.
Along with the new SANITIZE_MEMTAG_STACK, define a SANITIZE_MEMTAG
which will b
From: Claudiu Zissulescu
Hi Wilco,
Please find a updated series of patches for adding memtag-stack
sanitizer using AArch64 MTE instructions.
What is new:
- handle the situations when tagging a memory with size zero.
- add a new test for the above situation.
- remove typos.
Older message:
M
This patch adds support for negate, absolute value, and negative
absolute value. It does this by doing IOR, XOR, and ANDC on the BF/HF
values. In order to do this optimization, it also needs to define the
logical instructions for HFmode and BFmode.
2025-11-05 Michael Meissner
gcc/
*
On Wed, Nov 05, 2025 at 03:53:15AM -0500, Michael Meissner wrote:
> This patch adds the necessary support in libgcc to allow using the machine
> independent 16-bit floating point support.
No exports from libgcc_s.so.1? Is that because it is an experimental
feature so far, so you only want it in l
This patch adds insns to convert between the 16-bit floating point
types and to the floating point scalar types other than float/double.
It also adds conversions to/from integer types.
These conversions are done by doing the conversion in 2 steps and
converting the values to double, and from to/f
This patch adds support to generate xscvhpdp and xscvdphp on Power9 systems and
later, to convert between _Float16 and float scalar values.
2025-11-04 Michael Meissner
gcc/
* config/rs6000/float16.md (FP16_HW): New mode iterator.
(extendhf2): Add support converting between HFm
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