Re: [ARM EABI] Adjust 'libgomp.c++/target-cdtor-{1,2}.C' for 'targetm.cxx.use_aeabi_atexit' [PR119853, PR119854] (was: [Linaro-TCWG-CI] gcc-16-130-gaafe942227b: 10 regressions on arm)

2025-07-20 Thread Thomas Schwinge
Hi! Maxim, thanks for the explanations. Otherwise: On 2025-07-21T15:12:59+1200, Maxim Kuvyrkov wrote: >> On Jul 18, 2025, at 23:51, Thomas Schwinge wrote: >> On 2025-04-26T00:09:21+, ci_notify--- via Gcc-regression >> wrote: >>> Our automatic CI has detected problems related to your patc

[r16-2334 Regression] FAIL: g++.dg/concepts/expression.C -std=gnu++17 (test for excess errors) on Linux/x86_64

2025-07-20 Thread haochen.jiang
On Linux/x86_64, 9e3309773855d3639fdb9a7a7f7176612f16cd28 is the first bad commit commit 9e3309773855d3639fdb9a7a7f7176612f16cd28 Author: Jonathan Wakely Date: Thu Jun 5 12:05:19 2025 +0100 libstdc++: Add std::inplace_vector for C++26 (P0843R14) [PR119137] caused FAIL: g++.dg/concepts/ex

RE: [PATCH] RISC-V: Add testcase for unsigned scalar SAT_ADD form 8 and form 9

2025-07-20 Thread Li, Pan2
Ok, thanks Ciyan. Pan -Original Message- From: Ciyan Pan Sent: Monday, July 21, 2025 12:04 PM To: gcc-patches@gcc.gnu.org Cc: kito.ch...@gmail.com; richard.guent...@gmail.com; tamar.christ...@arm.com; juzhe.zh...@rivai.ai; Li, Pan2 ; jeffreya...@gmail.com; rdapp@gmail.com; panciya

[PATCH] RISC-V: Add testcase for unsigned scalar SAT_ADD form 8 and form 9

2025-07-20 Thread Ciyan Pan
From: panciyan This patch adds testcase for form8 and form9, as shown below: T __attribute__((noinline)) \ sat_u_add_##T##_fmt_8(T x, T y) \ { \ return x <= (T)(x + y) ? (x + y) : -1; \ } T __attribute__((noinlin

Re: [PATCH v2] RISCV: MIPS prefetch extensions for MIPS RV64 P8700 and can be enabled with xmipscbop.

2025-07-20 Thread Umesh Kalappa
Hi @Jeff Law , Please share your feedback and comments on the below changes . https://patchwork.sourceware.org/project/gcc/patch/20250717051448.733449-1-ukalappa.m...@gmail.com/ Thank you ~U On Thu, Jul 17, 2025 at 10:44 AM Umesh Kalappa wrote: > Updated the testcase for the prefetch write

Re: [ARM EABI] Adjust 'libgomp.c++/target-cdtor-{1,2}.C' for 'targetm.cxx.use_aeabi_atexit' [PR119853, PR119854] (was: [Linaro-TCWG-CI] gcc-16-130-gaafe942227b: 10 regressions on arm)

2025-07-20 Thread Maxim Kuvyrkov
> On Jul 18, 2025, at 23:51, Thomas Schwinge wrote: > > Hi! > > On 2025-04-26T00:09:21+, ci_notify--- via Gcc-regression > wrote: >> Our automatic CI has detected problems related to your patch(es). Please >> find some details below. >> >> In gcc_check master-arm, after: >> | commit gcc

Re: [PATCH] x86-64: Remove redundant TLS calls

2025-07-20 Thread Hongtao Liu
On Thu, Jul 17, 2025 at 11:22 PM H.J. Lu wrote: > > For TLS calls: > > 1. UNSPEC_TLS_GD: > > (parallel [ > (set (reg:DI 0 ax) > (call:DI (mem:QI (symbol_ref:DI ("__tls_get_addr"))) > (const_int 0 [0]))) > (unspec:DI [(symbol_ref:DI ("e") [flags 0x50]) >

[PATCH v1 5/5] RISC-V: Add test for vec_duplicate + vaaddu.vv combine for DImode

2025-07-20 Thread pan2 . li
From: Pan Li Add asm dump check and run test for vec_duplicate + vaaddu.vv combine to vaaddu.vx, with the GR2VR cost is 0, 1, 2 and 15 for the case 0 and case 1. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Add asm check. * gcc.target/riscv/rvv/autov

[PATCH v1 3/5] RISC-V: Add test for vec_duplicate + vaaddu.vv combine case 1 with GR2VR cost 0, 1 and 2 for QI, HI and SI mode

2025-07-20 Thread pan2 . li
From: Pan Li Add asm dump check test for vec_duplicate + vaaddu.vv combine to vaaddu.vx, with the GR2VR cost is 0, 1 and 2. Please note DImode is not included. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c: Add asm check. * gcc.target/riscv/rvv/autove

[PATCH v1 4/5] RISC-V: Allow VLS DImode for sat_op vx DImode pattern

2025-07-20 Thread pan2 . li
From: Pan Li When try to introduce the vaaddu.vx combine for DImode, we will meet ICE like below: 0x4889763 internal_error(char const*, ...) .../riscv-gnu-toolchain/gcc/__build__/../gcc/diagnostic-global-context.cc:517 0x4842f98 fancy_abort(char const*, int, char const*) .../ris

[PATCH v1 2/5] RISC-V: Add test for vec_duplicate + vaaddu.vv combine case 0 with GR2VR cost 0, 2 and 15 for QI, HI and SI mode

2025-07-20 Thread pan2 . li
From: Pan Li Add asm dump check and run test for vec_duplicate + vaaddu.vv combine to vaaddu.vx, with the GR2VR cost is 0, 2 and 15. Please note DImode is not included here. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Add asm check. * gcc.target/ri

[PATCH v1 1/5] RISC-V: Combine vec_duplicate + vaaddu.vv to vaaddu.vx on GR2VR cost for HI, QI and SI mode

2025-07-20 Thread pan2 . li
From: Pan Li This patch would like to combine the vec_duplicate + vaaddu.vv to the vaaddu.vx. From example as below code. The related pattern will depend on the cost of vec_duplicate from GR2VR. Then the late-combine will take action if the cost of GR2VR is zero, and reject the combination if

[PATCH v1 0/5] RISC-V: Combine vec_duplicate + vaaddu.vv to vaaddu.vx on GR2VR cost

2025-07-20 Thread pan2 . li
From: Pan Li This patch would like to introduce the combine of vec_dup + vaaddu.vv into vaaddu.vx on the cost value of GR2VR. The late-combine will take place if the cost of GR2VR is zero, or reject the combine if non-zero like 1, 2, 15 in test. There will be two cases for the combine: Case 0:

[PATCH] match: Add `cmp - 1` simplification to `-icmp` [PR110949]

2025-07-20 Thread Andrew Pinski
I have seen this a few places though the testcase from PR 95906 is an obvious place where this shows up for sure. This convert `cmp - 1` into `-icmp` as that form is more useful in many cases. Bootstrapped and tested on x86_64-linux-gnu. PR tree-optimization/110949 PR tree-optimiz

[pushed] wwwdocs: mirrors: Drop netgull.com

2025-07-20 Thread Gerald Pfeifer
Pushed. Gerald This mirror has not been updating (nor carrying full bits) since 2020 without response from the admins. --- htdocs/mirrors.html | 1 - 1 file changed, 1 deletion(-) diff --git a/htdocs/mirrors.html b/htdocs/mirrors.html index 7a823ceb..8cd6180f 100644 --- a/htdocs/mirrors.html ++

Re: Coarray shared memory testing

2025-07-20 Thread Toon Moene
On 7/19/25 23:26, Thomas Koenig wrote: I wrote: I have grave concerns. At the last (to me an Nicolas) known state, before he was ousted from the project, there were known race conditions, which can cause freezing and/or data corruption. I believe these have not been addressed, neither tested

[PATCH] libstdc++: Export std::byteswap from std.cc.in

2025-07-20 Thread hexne
After import std, std::byteswap cannot be used. After my observation, this function is the only one in the header file that has not been exported. The purpose of this patch is to export std::byteswap so that it can be used normally after import std. Signed-off-by: hexne <61956889+he...@users.no

[PATCH] Use regular libdir/includedir in libssp Makefiles

2025-07-20 Thread John Ericson
The details are exactly the same as https://gcc.gnu.org/pipermail/gcc-patches/2025-July/689865.html, except this is for libssp not libgcc. It probably makes sense to just pick one of these to review first, and then based on any feedback I can rework the other one. But for posterity, and to illustr

Re: [PATCH] [RFC] Delayed parsing for bounds safety attributes

2025-07-20 Thread Martin Uecker
I think the question is not whether this could be done somehow, but whether it should. Why design a language feature that requires  storing tokens and parsing it outside the original context?   For an attribute this may still be acceptable, but we need the same thing for array sizes in C. For

[PATCH] [RFC] Delayed parsing for bounds safety attributes

2025-07-20 Thread morbo
From: Bill Wendling Also, this code doesn't go further than parsing. I.e., it doesn't generate the internal gimple code that accesses the struct fields. The code is meant to show that it *is* possible to perform a delayed parsing with no "double parsing" and still be performant. Minor Nomenclatu

RE: [PATCH 1/2] aarch64: NFC - Make vec_* rtx costing logic consistent

2025-07-20 Thread Tamar Christina
> -Original Message- > From: Kyrylo Tkachov > Sent: Friday, July 18, 2025 5:48 PM > To: Tamar Christina > Cc: GCC Patches ; Richard Sandiford > ; Alex Coplan ; Andrew > Pinski > Subject: Re: [PATCH 1/2] aarch64: NFC - Make vec_* rtx costing logic > consistent > > Hi Tamar, > > > On 18