[PUSHED] testsuite: Fix afdo-crossmodule-1b.c [PR120859]

2025-07-19 Thread Andrew Pinski
The problem here is that the testcase is part of another testcase but dg-final does not work across source files so it needs its own dg-* headers to that match up with afdo-crossmodule-1.c. Pushed as preapproved in https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120859#c4 . PR testsuite/120

Re: Coarray shared memory testing

2025-07-19 Thread Jerry D
On 7/19/25 2:26 PM, Thomas Koenig wrote: I wrote: I have grave concerns. At the last (to me an Nicolas) known state, before he was ousted from the project, there were known race conditions, which can cause freezing and/or data corruption. I believe these have not been addressed, neither teste

Re: [PATCH] Export std::dextents from std.cc.in [PR121174]

2025-07-19 Thread Jonathan Wakely
On Sat, 19 Jul 2025, 14:20 Jakub Jelinek, wrote: > Hi! > > r16-442 implemented both std::extents and std::dextents (and perhaps other > stuff), but exported only std::extents. > I went through https://eel.is/c++draft/mdspan.syn and I think > std::dextents > is the only one implemented but not exp

Re: Coarray shared memory testing

2025-07-19 Thread Thomas Koenig
I wrote: I have grave concerns. At the last (to me an Nicolas) known state, before he was ousted from the project, there were known race conditions, which can cause freezing and/or data corruption. I believe these have not been addressed, neither tested nor by inspection. Maybe a word of exp

[PATCH v3] Change __builtin_unreachable to __builtin_trap (or infinite loop) if only thing in function [PR109267]

2025-07-19 Thread Andrew Pinski
When we have an empty function, things can go wrong with cfi_startproc/cfi_endproc and a few other things like exceptions. So if the only thing the function does is a call to __builtin_unreachable, let's replace that with a __builtin_trap instead if the target has a trap instruction. For targets w

[COMMITTED, GCC-15, PATCH] libstdc++: Update some baseline_symbols.txt (x32)

2025-07-19 Thread H.J. Lu
On Tue, Jul 8, 2025 at 6:46 PM H.J. Lu wrote: > > * config/abi/post/x86_64-linux-gnu/x32/baseline_symbols.txt: > Updated. > > > -- > H.J. I am backporting it to GCC 15 branch. -- H.J. From 88faa4c2d3be236059feabbcc6fe390961a8764b Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Wed, 9 Jul 2025 0

Re: Coarray shared memory testing

2025-07-19 Thread Jerry D
On 7/19/25 10:59 AM, Toon Moene wrote: On 7/19/25 18:32, Jerry D wrote: I expanded on Toon's random_weather.f90 test using: !integer, parameter :: DNX = 72, DNY = 70, DNZ = 30, BDSIZE = 4, HORSTEP =   1, VERSTEP = 100, FCLEN = 3600, TIMSTEP = 240 integer, parameter :: DNX = 1000, DNY =

Re: Coarray shared memory testing

2025-07-19 Thread Toon Moene
On 7/19/25 18:32, Jerry D wrote: I expanded on Toon's random_weather.f90 test using: !integer, parameter :: DNX = 72, DNY = 70, DNZ = 30, BDSIZE = 4, HORSTEP = 1, VERSTEP = 100, FCLEN = 3600, TIMSTEP = 240 integer, parameter :: DNX = 1000, DNY = 1500, DNZ = 100, BDSIZE = 4, HORSTEP =

Re: Coarray shared memory testing

2025-07-19 Thread Jerry D
On 7/17/25 9:37 PM, Jerry D wrote: I have created a new gfortran-test branch on gcc here. origin/devel/gfortran-test This has the patches applied as needed to do the testing I have done. When Andre's patches are approved I will revert and rebase this so we can test the next set of major chang

[committed] pru: Use signed HOST_WIDE_INT for handling ctable addresses

2025-07-19 Thread Dimitar Dimitrov
The ctable base address for SBCO/LBCO load/store patterns was incorrectly stored as unsigned integer. That prevented matching addresses with bit 31 set, because const_int RTL expression is expected to be sign-extended. Fix by using sign-extended 32-bit values for ctable base addresses. Pushed to

Re: [PATCH] [RISC-V] Fix wrong CFA during stack probe

2025-07-19 Thread Jeff Law
On 7/16/25 7:04 AM, Andreas Schwab wrote: PR target/121121 * config/riscv/riscv.cc (riscv_allocate_and_probe_stack_space): Use temp2 instead of temp1 for the CFA note. --- gcc/config/riscv/riscv.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/g

Re: [PATCH] RISC-V: Vector-scalar widening negate-multiply-(subtract-)accumulate [PR119100]

2025-07-19 Thread Jeff Law
On 7/16/25 8:38 AM, Paul-Antoine Arras wrote: This pattern enables the combine pass (or late-combine, depending on the case) to merge a float_extend'ed vec_duplicate into a (possibly negated) minus-mult RTL instruction. Before this patch, we have six instructions, e.g.: vsetivli zero

Re: [PATCH v5 0/3] Hard Register Constraints

2025-07-19 Thread Jeff Law
On 7/17/25 2:24 AM, Stefan Schulze Frielinghaus wrote: On Wed, Jul 09, 2025 at 03:48:43PM +0200, Stefan Schulze Frielinghaus wrote: This is a follow-up to https://gcc.gnu.org/pipermail/gcc-patches/2025-May/684181.html I added the last missing pieces namely changelogs, and bootstrapped and re

Re: [PATCH v1] RISC-V: Support RVVDImode for avg3_ceil auto vect

2025-07-19 Thread Jeff Law
On 7/18/25 7:06 AM, Li, Pan2 wrote: OK. Curious if you've seen this show up in practice and is using the vaaddu and similar instructions actually profitable? I remember avg will be presented in somewhere else but not for DImode. I tried to add vaadd related vx combine and notice we don't ha

Re: [PATCH] RISC-V: prevent NULL_RTX dereference in riscv_macro_fusion_pair_p ()

2025-07-19 Thread Jeff Law
On 7/18/25 12:29 PM, Artemiy Volkov wrote: On Fri, Jul 18, 2025 at 11:42:59AM -0600, Jeff Law wrote: On 7/18/25 11:03 AM, Artemiy Volkov wrote: On Wed, Jul 02, 2025 at 08:15:40PM -0600, Jeff Law wrote: A number of folks have had their fingers in this code and it's going to take a few subm

Re: [PATCH v1] RISC-V: Add ashiftrt operand 2 for vector avg_floor and avg_ceil

2025-07-19 Thread Jeff Law
On 7/19/25 3:37 AM, pan2...@intel.com wrote: From: Pan Li According to the semantics of the avg_floor and avg_ceil as below: floor: op0 = (narrow) (((wide) op1 + (wide) op2) >> 1); ceil: op0 = (narrow) (((wide) op1 + (wide) op2 + 1) >> 1); Aka we have (const_int 1) as the op2 of the ashif

Re: [PATCH v1] RISC-V: Refine the test case for vector avg_floor and avg_ceil [NFC]

2025-07-19 Thread Jeff Law
On 7/18/25 8:49 PM, pan2...@intel.com wrote: From: Pan Li The previous test case doesn't leverage the right test helper macro, it should be DEF_AVG_0_WRAP instead of DEF_AVG_0. We prefer the test function name is test_avg_floor_int64_t_int32_t_0 instead of test_avg_floor_WT_NT_0 for DEF_AVG

[PATCH] Export std::dextents from std.cc.in [PR121174]

2025-07-19 Thread Jakub Jelinek
Hi! r16-442 implemented both std::extents and std::dextents (and perhaps other stuff), but exported only std::extents. I went through https://eel.is/c++draft/mdspan.syn and I think std::dextents is the only one implemented but not exported. The following patch exports it, and additionally appends

[patch,avr,applied] Fuse get_insns with end_sequence

2025-07-19 Thread Georg-Johann Lay
There were two cases where get_insns() can be fused with end_sequence(). Applied as obvious. Johann -- AVR: Fuse get_insns with end_sequence. gcc/ * config/avr/avr-passes.cc (avr_optimize_casesi): Fuse get_insns() with end_sequence(). diff --git a/gcc/config/avr/avr-passes.cc

[PATCH v4] libstdc++: Implement Philox Engine [PR119794]

2025-07-19 Thread 1nfocalypse
Implements Philox Engine (P2075R6) and associated tests. Implements additional feedback from v3 from Patrick Palka. I went ahead and qualified the STL functions to avoid ADL ambiguity, as recommended. However, if this was erroneous, I'd be happy to go back and change it. Additionally, the suspic

[PATCH v1] RISC-V: Add ashiftrt operand 2 for vector avg_floor and avg_ceil

2025-07-19 Thread pan2 . li
From: Pan Li According to the semantics of the avg_floor and avg_ceil as below: floor: op0 = (narrow) (((wide) op1 + (wide) op2) >> 1); ceil: op0 = (narrow) (((wide) op1 + (wide) op2 + 1) >> 1); Aka we have (const_int 1) as the op2 of the ashiftrt but seems missed. Thus, add it back to align t

[PATCHv3] libstdc++: Add NTTP bind_front, -back, not_fn (P2714) [PR119744]

2025-07-19 Thread Nathan Myers
This should be close to ready. However, std::is_invocable and noexcept still fail oddly applied to the not_fp result. The remaining failing test cases in */nttp.cc, commented out, need careful examination to see whether they should be expecting different results given that the argument function obj

Re: [PATCH] [RFC] Move STMT_VINFO_TYPE to SLP_TREE_TYPE

2025-07-19 Thread Richard Biener
> Am 18.07.2025 um 20:06 schrieb Robin Dapp : > >  >> >> Can the risc-v people try to sort out this up to a point >> where I can just s/STMT_VINFO_TYPE/SLP_TREE_TYPE there? > > I think for us this mainly (only?) concerns the dynamic LMUL heuristic. > Currently we go through all vectorized in