On 5/20/25 1:22 AM, Stefan Schulze Frielinghaus wrote:
This implements error handling for hard register constraints including
potential conflicts with register asm operands.
In contrast to register asm operands, hard register constraints allow
more than just one register per operand. Even mo
On Sat, Jun 21, 2025 at 2:41 PM Max Filippov wrote:
>
> On Sat, Jun 21, 2025 at 2:12 PM Takayuki 'January June' Suwa
> wrote:
> >
> > That hook has since been deprecated
> > (commit a670ebde3995481225ec62b29686ec07a21e5c10) and has led to incorrect
> > results on Xtensa:
> >
> > /* example *
On Sat, Jun 21, 2025 at 2:12 PM Takayuki 'January June' Suwa
wrote:
>
> That hook has since been deprecated
> (commit a670ebde3995481225ec62b29686ec07a21e5c10) and has led to incorrect
> results on Xtensa:
>
> /* example */
> #define
> uint32_t __attribute__((noinline)) test0(uint3
On Sun, Jun 22, 2025 at 6:35 AM Max Filippov wrote:
>
> On Sat, Jun 21, 2025 at 2:41 PM Max Filippov wrote:
> >
> > On Sat, Jun 21, 2025 at 2:12 PM Takayuki 'January June' Suwa
> > wrote:
> > >
> > > That hook has since been deprecated
> > > (commit a670ebde3995481225ec62b29686ec07a21e5c10) and
Hi,
when splitting functions, tree-inline determined correctly entry count of the
new function part, but then in case entry block of new function part is in a
loop it scales body which is not suposed to happen.
Bootstrapped/regtested x86_64-linux, comitted.
* tree-inline.cc (copy_cfg_body
On Sun, Jun 22, 2025 at 5:41 AM Max Filippov wrote:
>
> On Sat, Jun 21, 2025 at 2:12 PM Takayuki 'January June' Suwa
> wrote:
> >
> > That hook has since been deprecated
> > (commit a670ebde3995481225ec62b29686ec07a21e5c10) and has led to incorrect
> > results on Xtensa:
> >
> > /* example *
Since there is
/* X86_TUNE_SPLIT_LONG_MOVES: Avoid instructions moving immediates
directly to memory. */
DEF_TUNE (X86_TUNE_SPLIT_LONG_MOVES, "split_long_moves", m_PPRO)
to avoid long immediate store instructions, like
c7 02 00 00 00 00movl $0x0,(%rdx)
c7 02 ff ff ff ffmovl $0xff
From: Mikael Morin
Changes v1 -> v2:
- Also handle complex conjugate operator.
- Don't create the NON_LVALUE_EXPR if there is a type conversion between the
doubled operators.
Regression tested on x86_64-linux. OK for master?
-- 8< --
gcc/ChangeLog:
* match.pd (`-(-X)`, `~(~X)`,
It was an accidental typo that snuck in that I missed. it was suppose
to be "int" and I thought I had changed it back.
thanks
Andrew
PS. And this is only called if mask is != 0, but point taken, we
should guard the routine inside for future proofing. Ill take care of
it monday.
On 6/
On 6/20/25 5:59 AM, Richard Sandiford wrote:
In this PR, we started with:
(subreg:V2DI (reg:DI virtual-reg) 0)
and vregs instantiated the virtual register to the argument pointer.
But:
(subreg:V2DI (reg:DI ap) 0)
is not a sensible subreg, since the argument pointer certainly can'
On 6/12/25 10:53 AM, Alfie Richards wrote:
Previously, the `record` argument in maybe_version_function allowed the
call to cgraph_node::record_function_versions to be skipped. However,
this was only skipped when both decls were already marked as versioned,
in which case we trigger the early e
On Tue, Jun 17, 2025 at 09:27:27PM -0400, Andrew MacLeod wrote:
> + uint z = wi::ctz (m_bitmask.mask ());
uint is some compatibility type in glibc sys/types.h enabled in misc/GNU
modes, so it doesn't exist on many hosts.
Furthermore, wi::ctz returns int rather than unsigned and the var is
only us
On 6/21/25 3:52 AM, Robin Dapp wrote:
This patch would like to introduce the combine of vec_dup + vsaddu.vv
into vsaddu.vx on the cost value of GR2VR. The late-combine will take
place if the cost of GR2VR is zero, or reject the combine if non-zero
like 1, 2, 15 in test. There will be two cas
Ping for this patch.
On Wed, May 28, 2025 at 02:19:11PM -0400, Patrick Palka wrote:
> On Sat, 24 May 2025, Nathaniel Shead wrote:
>
> > Bootstrapped and regtested on x86_64-pc-linux-gnu, OK for trunk/15?
>
> LGTM FWIW
>
> >
> > -- >8 --
> >
> > When emitting a primary module interface, we mus
Ping.
On Thu, May 22, 2025 at 12:15:34PM +1000, Nathaniel Shead wrote:
> This type currently has a DECL_NAME of an IDENTIFIER_DECL. Although the
> documentation indicates this is legal, this confuses modules streaming
> which expects all RECORD_TYPEs to have a TYPE_DECL, which is used to
> determ
Ping for this patch.
On Sun, Jun 01, 2025 at 11:23:01PM -0400, Patrick Palka wrote:
> On Sat, 31 May 2025, Nathaniel Shead wrote:
>
> > On Fri, May 30, 2025 at 11:10:08AM -0400, Patrick Palka wrote:
> > > On Fri, 30 May 2025, Patrick Palka wrote:
> > >
> > > > On Fri, 30 May 2025, Nathaniel Shea
On 5/20/25 1:22 AM, Stefan Schulze Frielinghaus wrote:
Implement hard register constraints of the form {regname} where regname
must be a valid register name for the target. Such constraints may be
used in asm statements as a replacement for register asm and in machine
descriptions.
It is exp
On Thu, May 22, 2025 at 12:16:07PM +1000, Nathaniel Shead wrote:
> I'm not sure if there might be a better way to retrieve the prefix back
> off an IDENTIFIER_NODE? I'm also not sure if IDENTIFIER_INTERNAL_P
> could ever clash with IDENTIFIER_TRANSPARENT_ALIAS; I'm pretty sure not
> (and it looks
On Thu, May 22, 2025 at 12:14:34PM +1000, Nathaniel Shead wrote:
> This patch isn't currently necessary with how I've currently done the
> follow-up patches, but is needed for avoiding any potential issues in
> the future with DECL_CONTEXT'ful types getting created in the compiler
> with no names o
On Fri, Jun 20, 2025 at 4:12 PM H.J. Lu wrote:
>
> Don't use vmovdqu16/vmovdqu8 with non-EVEX registers even if AVX512BW is
> available.
>
> gcc/
>
> PR target/120728
> * config/i386/i386.cc (ix86_get_ssemov): Use vmovdqu16/vmovdqu8
> only with EVEX registers.
>
> gcc/testsuite/
>
> PR target/1207
On Fri 2025-06-20 10:46:08, Alex Coplan wrote:
> Hi,
>
> This adds a main() function to mklog.py (like e.g. check_GNU_style.py
> has), which makes it easier to import and invoke from another python
> script. This is useful when using a wrapper script to set up the python
> environment.
>
> Smoke
On 2025-06-20 11:26, Qing Zhao wrote:
the mentioned code change:
+else if (TREE_CODE (rhs) == MEM_REF
+ && POINTER_TYPE_P (TREE_TYPE (rhs))
+ && TREE_CODE (TREE_OPERAND (rhs, 0)) == SSA_NAME)
+ reexamine = merge_object_sizes (osi, var, TREE_OPERAND (rhs
On 2025-06-20 10:22, Qing Zhao wrote:
Okay, this is a reasonable solution to this problem.
I will add a new —param option as suggested, and then guard the generation of
the size expression for:
__builtin_dynamic_object_size (p, 1)
With this opinion before the NULL pointer checking. Then upda
This patch would like to introduce the combine of vec_dup + vsaddu.vv
into vsaddu.vx on the cost value of GR2VR. The late-combine will take
place if the cost of GR2VR is zero, or reject the combine if non-zero
like 1, 2, 15 in test. There will be two cases for the combine:
OK, thanks.
--
Rega
From: Pan Li
Add asm dump check test for vec_duplicate + vsaddu.vv combine to
vsaddu.vx, with the GR2VR cost is 0, 1 and 2.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c: Add asm check
for vsaddu.vx combine.
* gcc.target/riscv/rvv/autovec/vx_vf
From: Pan Li
Add asm dump check and run test for vec_duplicate + vsaddu.vv
combine to vsaddu.vx, with the GR2VR cost is 0, 2 and 15.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Add asm check.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto.
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