From: Ronan Desplanques
This patch visually packs together the statements that implement the
exceptions in Rewrite that a few fields are not actually overwritten, in
order to improve the readability of the code.
gcc/ada/ChangeLog:
* atree.adb (Rewrite): Improve readability.
Tested on x
From: Ronan Desplanques
Setting the proper Ekind on object entities was once needed to catch
cases of premature usages. The introduction of Is_Self_Hidden changed
that, so this patch replaces the Mutate_Ekind calls in the natural
place.
gcc/ada/ChangeLog:
* sem_ch3.adb (Analyze_Object_D
From: Bob Duff
A previous change (commit 33eebd96d27fa2b29cec79f55167a11aaf7f4802)
removed code in Analyze_Object_Renaming that tranformed renamings
into object declarations. This reinstates that code.
Removing the code causes failures in
gnatbugs-large/2023/gnat-435_deep_blue_capital.
Ideally,
From: Ronan Desplanques
This patch removes a comment that misleadingly presented a condition as
being met only in rare situations, while it's in fact satisfied in very
basic cases such as simple object declarations.
gcc/ada/ChangeLog:
* sem_util.adb (Enter_Name): Remove comment.
Tested
From: Ronan Desplanques
gcc/ada/ChangeLog:
* sem_util.ads (Current_Entity_In_Scope): Add example in comment.
Tested on x86_64-pc-linux-gnu, committed on master.
---
gcc/ada/sem_util.ads | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/gcc/ada/sem_ut
From: Ronan Desplanques
Before this patch, the constant mark of object declarations was stripped
in some error situations. This behavior is currently not useful so this
patch removes it.
gcc/ada/ChangeLog:
* sem_ch3.adb (Analyze_Object_Declaration): Tweak error handling.
Tested on x86_
From: Ronan Desplanques
Is_Object returns True for "record field" entities, which might make
sense in some contexts but not when Kill_Current_Values is called in a
default expression of a record component. This patch refines the choice
of considered entities in Kill_Current_Values accordingly.
g
From: Daniel King
gcc/ada/ChangeLog:
* libgnat/i-cheri.ads
(Set_Bounds, Set_Exact_Bounds): Remove wrong intrinsic binding.
* libgnat/i-cheri.adb
(Set_Bounds, Set_Exact_Bounds): New subprogram bodies.
Tested on x86_64-pc-linux-gnu, committed on master.
---
gcc/a
From: Gary Dismukes
GNAT was incorrectly implementing the Ada rules for resolving calls to
primitive functions within inherited class-wide pre- and postconditions,
as specified in RM22 6.1.1 (relating to AI12-0113). Only function calls
that involve formals of the associated primitive subprogram
From: Eric Botcazou
Even though the actual subtype of the anonymous array is not yet set on the
object itself by the time Insert_Conditional_Object_Declaration is called,
it is set on its initialization expression, so it can simply be forwarded
to Insert_Conditional_Object_Declaration from there,
In the case where the overlaid object is nested in a record or is an
array element as in:
for Foo'Address use Item.Nested_Item'Address;
or for Foo'Address use Item (Bar)'Address;
the compiler was not emitting a warning in case of differing
Scalar_Storage_Order values.
gcc/ada/ChangeLog:
From: Eric Botcazou
The predicate is used to detect corner cases in multiplicative operations
and also returns True for NaNs.
gcc/ada/ChangeLog:
* libgnat/s-dourea.adb (Is_Infinity): Rename to...
(Is_Infinity_Or_NaN): ...this.
("*"): Adjust accordingly.
("/"): Li
From: Ronan Desplanques
gcc/ada/ChangeLog:
* sem_ch8.adb (Find_Selected_Component): Fix error path.
Tested on x86_64-pc-linux-gnu, committed on master.
---
gcc/ada/sem_ch8.adb | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/ada/sem_ch8.adb b/gcc/ada/sem_ch8.adb
index 4cd6b7d93
From: Ronan Desplanques
This patch adds a mention of the relevant Ada RM clause to a comment
about a part of Find_Selected_Component, to make it easier to find.
gcc/ada/ChangeLog:
* sem_ch8.adb (Find_Selected_Component): Add mention.
Tested on x86_64-pc-linux-gnu, committed on master.
One thing I noticed while working on copy prop for aggregates is that we start
with
a memcpy like statement and then walk backwards. This means we could have a few
walks
backwards to see there was no statement for zeroing. Instead this changes the
walk
backwards into a true forwprop. In the futu
The following example:
#define N 640
int a[N] = {};
int b[N] = {};
int c[N] = {};
void f1 (int d)
{
for (int i = 0; i < N; i++)
{
b[i] += a[i];
if (a[i] != d)
break;
}
}
today generates with
-Ofast -march=armv8-a+sve --param aarch64-autovec-preference=asimd-only
.L
In the example
void f1 ()
{
for (int i = 0; i < N; i++)
{
b[i] += a[i];
if (a[i] > 0)
break;
}
}
when compiled for SVE we generate:
ld1wz28.s, p7/z, [x4, x0, lsl 2]
cmpgt p14.s, p7/z, z28.s, #0
ptest p15, p14.b
b.none .L3
Wh
This patch introduces two new vector cbranch optabs vec_cbranch_any and
vec_cbranch_all.
To explain why we need two new optabs let me explain the current cbranch and its
limitations and what I'm trying to optimize. So sorry for the long email, but I
hope it explains why I think we want new optabs.
> OK. ANd if there's a vremu variant in the works that looks basically
> the same from an implementation standpoint, then consider it
> pre-approved as well.
Thanks Jeff, will commit if CI is Ok.
Pan
-Original Message-
From: Jeff Law
Sent: Sunday, June 8, 2025 10:39 PM
To: Li, Pan2
[sending again as the email seems to have not delivered]
Hi Richard,
> On 7 Jun 2025, at 1:12 am, Richard Sandiford
> wrote:
>
> External email: Use caution opening links or attachments
>
>
> Jan Hubicka writes:
>>> Should I go with:
>>>
>>> +autofdo_target
>>>
>>> +autofdo_target="i386"
> On 9 Jun 2025, at 9:43 am, Kugan Vivekanandarajah
> wrote:
>
>
>
> > On 7 Jun 2025, at 3:30 pm, Kugan Vivekanandarajah
> > wrote:
> >
> > Hi,
> >
> >
> > > On 6 Jun 2025, at 4:15 pm, Kugan Vivekanandarajah
> > > wrote:
> > >
> > > Hi Andrew,
> > >
> > >
> > >> On 6 Jun 2025, at 4:06 pm, A
FRM mode switching state machine has DYN as default state which it also
fallsback to after transitioning to other states such as DYN_CALL.
Currently TARGET_MODE_EMIT generates a FRM restore on any transition to
DYN leading to spurious/extraneous FRM restores.
Only do this if an interim static Roun
As described in prior patches of this series, FRM mode switching state
machine has special handling around calls. After a call_insn, if in DYN_CALL
state, it needs to transition back to DYN, which requires back checking
if prev insn was indeed a call.
Defering/delaying this could lead to unncessar
This is effectively reverting e5d1f538bb7d
"(RISC-V: Allow different dynamic floating point mode to be merged)"
while retaining the testcase.
The change itself is valid, however it obfuscates the deficiencies in
current frm mode switching code.
Also for a SPEC2017 -Ofast -march=rv64gcv build, it
On 6/8/25 08:02, Jeff Law wrote:
> OK. Thanks for your patience.
No worries, thx for the review. I pushed the series.
-Vineet
gcc/ChangeLog:
* emit-rtl.cc (next_nonnote_nondebug_insn): Update comments.
Signed-off-by: Vineet Gupta
---
gcc/emit-rtl.cc | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/gcc/emit-rtl.cc b/gcc/emit-rtl.cc
index 50e3bfcb777a..e64032970d09 100644
--- a/gcc/emit-r
This showed up when debugging the testcase for PR119164.
RISC-V FRM mode-switching state machine has special handling for transitions
to and from a call_insn as FRM needs to saved/restored around calls
despite it not being a callee-saved reg; rather it's a "global" reg
which can be temporarily mod
Another czero related adjustment. This time in costing of conditional
move sequences. Essentially a copy from a promoted subreg can and
should be ignored from a costing standpoint. We had some code to do
this, but its conditions were too strict.
No real surprises evaluating spec. This shou
This is based on the review of cond_if_else_store_replacement_limited
(https://gcc.gnu.org/pipermail/gcc-patches/2025-June/686076.html).
Moves else_vdef definition/assignment to be next to the usage in
single_trailing_store_in_bb.
Pushed as obvious after test on x86_64-linux-gnu.
gcc/ChangeLog:
Here is a new attempt preserving symbols.
libstdc++: Make debug iterator pointer sequence const [PR116369]
In revision a35dd276cbf6236e08bcf6e56e62c2be41cf6e3c the debug sequence
have been made mutable to allow attach iterators to const containers.
This change completes this fix
On Sun, Jun 8, 2025 at 2:03 AM Richard Biener
wrote:
>
> On Sat, Jun 7, 2025 at 12:32 AM Andrew Pinski
> wrote:
> >
> > So currently cselim is limited to targets which have conditional move
> > and also happens later in the pipeline. This adds the limited form of
> > cselim;
> > where there is
Don't inline finding of the virtual op phi node, instead use get_virtual_phi.
This is based on the review of a different patch
(https://gcc.gnu.org/pipermail/gcc-patches/2025-June/686076.html).
Pushed as obvious after a bootstrap/test on x86_64-linux-gnu.
gcc/ChangeLog:
* tree-ssa-phiop
While thinking about how to implement the rest of the copy prop and makes sure
not
to introduce some compile time problems, optimize_agr_copyprop should be changed
into a forwproping rather than looking backwards.
Bootstrapped and tested on x86_64-linux-gnu.
gcc/ChangeLog:
* tree-ssa-fo
Hmm okay. Doesn't seem to work for me on latest master at least.
Here's the error i'm getting with makeinfo 4.13:
../../gcc/doc//invoke.texi:249: warning: unlikely character , in @var.
../../gcc/doc//invoke.texi:3801: warning: unlikely character , in @var.
../../gcc/doc//invoke.texi:5247: warning
On 6/5/25 2:16 PM, Dimitar Dimitrov wrote:
PR119966 showed that combine could generate unfoldable hardware subregs
for pru-unknown-elf. To fix, strengthen the checks performed by
validate_subreg.
The simplify_subreg_regno performs more validity checks than
the simple info.representable_p. M
On 6/7/25 4:11 AM, Henrik Lindström wrote:
The build fails with older versions.
Signed-off-by: Henrik Lindström
---
gcc/configure| 2 +-
gcc/configure.ac | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
I think that was just a bug in our documentation that was subsequently
f
On 6/7/25 4:38 AM, Stafford Horne wrote:
## Note on cstoresi4 and PUT_MODE.
There was some concern raised by Jeff about the use of PUT_MODE in cstoresi4.
This is here to convert a 'ne' to 'ne:SI', for example, allowing the generated
RTL to match with the "*scc" insn pattern later.
It seems
On 6/5/25 6:04 PM, Vineet Gupta wrote:
Changes since v1:
- NFC change to commitlog and drop test case for PR/119164
As described in prior patches of this series, RM manipulation could require
save/restore around calls (not in the caller-saved sense) but to retain
the global semantics. To t
On 6/5/25 6:04 PM, Vineet Gupta wrote:
Changes since v1
- Dropped removal of TARGET_MODE_AFTER
- NFC changes to last 2 patches, with reattribution to PRs they address
seperately.
Hi,
This came out of Rivos perf team reporting (shoutout to Siavash) that
some of the SPEC2017 workloads h
On 6/5/25 10:15 PM, Vineet Gupta wrote:
On 6/5/25 20:09, 钟居哲 wrote:
Hi. Vineet. The series of patches LGTM from myside.
Thx.
But I wonder whether you would like to optimize VXRM which is using
mode-switching too.
Was not planning to :-)
I saw in spec 2017 spec 624 x264.
csrwi vxrm i
On 6/6/25 12:41 AM, Richard Biener wrote:
On Fri, Jun 6, 2025 at 2:08 AM Vineet Gupta wrote:
gcc/ChangeLog:
* emit-rtl.cc (next_nonnote_nondebug_insn): Update comments.
Signed-off-by: Vineet Gupta
---
gcc/emit-rtl.cc | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
On 6/8/25 3:30 AM, pan2...@intel.com wrote:
From: Pan Li
This patch would like to introduce the combine of vec_dup + vrem.vv into
vrem.vx on the cost value of GR2VR. The late-combine will take place
if the cost of GR2VR is zero, or reject the combine if non-zero like 1, 15
in test. There w
VxWorks kernel mode doesn't support thumb code, so the test fails.
Require thumb2 support.
Tested with arm-vx7r2 on gcc-14, where this came up, and with arm-eabi
on trunk. Absent objections, I'm going to install this as obvious in
the next few days.
for gcc/testsuite/ChangeLog
* g++
On Sat, Jun 7, 2025 at 10:05 PM Takayuki 'January June' Suwa
wrote:
>
> By using the previously unused CEIL|FLOOR.S floating-point coprocessor
> instructions. In addition, two instruction operand format codes are added
> to output the scale value as assembler source.
>
> /* example */
>
From: Pan Li
Add asm dump check test for vec_duplicate + vrem.vv combine to vrem.vx,
with the GR2VR cost is 0, 1 and 2.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c: Add asm check
for vrem.vx combine.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-4-
From: Pan Li
Add asm dump check test for vec_duplicate + vrem.vv combine to vrem.vx,
with the GR2VR cost is 0, 2 and 15.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add asm check
for vrem.vx combine.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1
From: Pan Li
This patch would like to introduce the combine of vec_dup + vrem.vv into
vrem.vx on the cost value of GR2VR. The late-combine will take place
if the cost of GR2VR is zero, or reject the combine if non-zero like 1, 15
in test. There will be two cases for the combine:
Case 0:
| .
From: Pan Li
This patch would like to combine the vec_duplicate + vrem.vv to the
vrem.vx. From example as below code. The related pattern will depend
on the cost of vec_duplicate from GR2VR. Then the late-combine will
take action if the cost of GR2VR is zero, and reject the combination
if the
From: Pan Li
Some existing vrem related test need some adjust for the
asm check due to cost model.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c: Adjust the
asm check for vrem.
* gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c: Ditto.
Si
On Fri, 6 Jun 2025, Pengfei Li wrote:
> Current GCC uses either peeling or versioning, but not in combination,
> to handle unaligned data references (DRs) during vectorization. This
> limitation causes some loops with early break to fall back to scalar
> code at runtime.
>
> Consider the followin
On Sat, Jun 7, 2025 at 9:32 PM Andrew Pinski wrote:
>
> On Fri, Jun 6, 2025 at 12:02 PM Andrew Pinski wrote:
> >
> > On Thu, Jun 5, 2025 at 11:39 PM Richard Biener
> > wrote:
> > >
> > > On Fri, Jun 6, 2025 at 12:14 AM Andrew Pinski
> > > wrote:
> > > >
> > > > Currently we expand `{}` and sto
On Sun, Jun 8, 2025 at 1:06 AM Andrew Pinski wrote:
>
> Since r13-707-g68e0063397ba82 COND_EXPR in gimple assign does
> not have a special case for COND_EXPR and conditional as the first operand.
> This removes the code from tree-ssa-math-opts.cc which was for that special
> case.
>
> Bootstrappe
On Sat, Jun 7, 2025 at 12:32 AM Andrew Pinski wrote:
>
> So currently cselim is limited to targets which have conditional move
> and also happens later in the pipeline. This adds the limited form of cselim;
> where there is only one store in the two sides and no loads after the store.
>
> This fix
On Sat, Jun 7, 2025 at 12:31 AM Andrew Pinski wrote:
>
> So the current code iterates through the uses of the vdef of the store to see
> if there
> is an use of the vdef inside the bb. Except in this case we know the only
> usage will
> be a phi node, so change the loop into calling single_imm_u
On Fri, 6 Jun 2025, Jakub Jelinek wrote:
> Hi!
>
> On top of the just posted patch, the following patch attempts to
> use value range to see if MSB is known to be false and for scalar integral
> extension in that case tries to expand both sign and zero extension and
> chooses based on RTX costs t
On Fri, 6 Jun 2025, Andrew MacLeod wrote:
>
> Interesting.
>
> I don't remember details about the order of things... Is there any chance
> that you might query an SSA_NAME whose DEF was in a block which has been
> converted to RTL? Ranger will query all the way back to the def block,
> acces
On Fri, Jun 6, 2025 at 5:28 PM James K. Lowden wrote:
>
> I have committed a change to the master branch in my local repository
> with the following message. Since it's my first time, before pushing,
> I would like to know if there's any problem with the message itself.
>
> I have tried to follow
On Sat, Jun 7, 2025 at 12:34 PM Andrew Pinski wrote:
>
> On Fri, Jun 6, 2025 at 11:50 AM Andrew Pinski
> wrote:
> >
> > This improves copy prop for aggregates by working over statements that
> > don't modify the access
> > just like how it is done for copying zeros.
> > To speed up things, we s
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