RE: [PATCH v2 1/3] RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR cost

> Ah, I see, thanks. So vec_dup costs 1 + 2 and vadd.vv costs 1 totalling 4 > while vadd.vx costs 1 + 2, making it cheaper? Yes, looks we need to just assign the GR2VR when vec_dup. I also tried diff cost here to see the impact to late-combine. + if (rcode == VEC_DUPLICATE && SCALAR_INT_MODE_

Re: [PATCH] [x86] Generate 2 FMA instructions in ix86_expand_swdivsf.

On Thu, Apr 24, 2025 at 12:54 AM Jan Hubicka wrote: > > > From: "hongtao.liu" > > > > When FMA is available, N-R step can be rewritten with > > > > a / b = (a - (rcp(b) * a * b)) * rcp(b) + rcp(b) * a > > > > which have 2 fma generated.[1] > > > > [1] https://bugs.llvm.org/show_bug.cgi?id=21385 >

Re: [PATCH] Consider frequency in cost estimation when converting scalar to vector.

On Thu, Apr 24, 2025 at 12:50 AM Jan Hubicka wrote: > > > In some benchmark, I notice stv failed due to cost unprofitable, but the > > igain > > is inside the loop, but sse<->integer conversion is outside the loop, > > current cost > > model doesn't consider the frequency of those gain/cost. > >

Re: [PATCH] Add std::deque shrink_to_fit test

AFAICT I've never got proper validation for this small patch. Is it ok to commit ? Thanks On 14/04/2025 22:25, François Dumont wrote: On 14/04/2025 08:29, Tomasz Kaminski wrote: On Sun, Apr 13, 2025 at 12:13 PM François Dumont wrote: On 11/04/2025 08:36, Tomasz Kaminski wrote:

[GCC16 stage 1][PATCH v2 0/3] extend "counted_by" attribute to pointer fields of structures

Hi, This is the 2nd version of the patch set to extend "counted_by" attribute to pointer fields of structures. the first version was submitted 3 months ago on 1/16/2025, and triggered a lot of discussion on whether we need a new syntax for counted_by attribute. https://gcc.gnu.org/pipermail/gcc

[PATCH] GCN, nvptx offloading: Host/device compatibility: Itanium C++ ABI, DSO Object Destruction API [PR119853, PR119854]

'__dso_handle' for '__cxa_atexit', '__cxa_finalize'. See . PR target/119853 PR target/119854 libgcc/ * config/gcn/crt0.c (_fini_array): Call '__GCC_offload___cxa_finalize'. * config/nvptx/

[GCC16 stage1][PATCH v2 3/3] Use the counted_by attribute of pointers in array bound checker.

Current array bound checker only instruments ARRAY_REF, and the INDEX information is the 2nd operand of the ARRAY_REF. When extending the array bound checker to pointer references with counted_by attributes, the hardest part is to get the INDEX of the corresponding array ref from the offset comput

[GCC16 stage1][PATCH v2 2/3] Convert a pointer reference with counted_by attribute to .ACCESS_WITH_SIZE and use it in builtinin-object-size.

gcc/c/ChangeLog: * c-typeck.cc (build_counted_by_ref): Handle pointers with counted_by. (build_access_with_size_for_counted_by): Likewise. gcc/ChangeLog: * tree-object-size.cc (access_with_size_object_size): Handle pointers with counted_by. (collect_object

[GCC16 stage1][PATCH v2 1/3] Extend "counted_by" attribute to pointer fields of structures.

For example: struct PP { size_t count2; char other1; char *array2 __attribute__ ((counted_by (count2))); int other2; } *pp; specifies that the "array2" is an array that is pointed by the pointer field, and its number of elements is given by the field "count2" in the same structure. gcc/c-

[committed] testsuite: Require fstack_protector for no-stack-protector-attr-3.C

The test fails on pru-unknown-elf with: cc1plus: warning: '-fstack-protector' not supported for this target Even though the compiled functions have the feature disabled using an attribute, the command line option is still not supported by some targets. Tested x86_64-pc-linux-gnu and ensured th

[PATCH v2] loop2_unroll: split loop exit during unrolling of uncountable loops

Hi all, sending a v2 of https://gcc.gnu.org/pipermail/gcc-patches/2025-April/680893.html after fixing several issues with the original patch. Namely, the changes since v1 are: - Remove the call to df_finish_pass () at the end of split_exit () and simply restore the previous value of the DF fla

Re: [PATCH] [x86] Generate 2 FMA instructions in ix86_expand_swdivsf.

> From: "hongtao.liu" > > When FMA is available, N-R step can be rewritten with > > a / b = (a - (rcp(b) * a * b)) * rcp(b) + rcp(b) * a > > which have 2 fma generated.[1] > > [1] https://bugs.llvm.org/show_bug.cgi?id=21385 > > Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. > Ok fo

Re: [PATCH] Consider frequency in cost estimation when converting scalar to vector.

> In some benchmark, I notice stv failed due to cost unprofitable, but the igain > is inside the loop, but sse<->integer conversion is outside the loop, current > cost > model doesn't consider the frequency of those gain/cost. > The patch weights those cost with frequency just like LRA does. > >

Re: Help: Re: Questions on replacing a structure pointer reference to a call to .ACCESS_WITH_SIZE in C FE

Richard, Thanks a lot for the hint. > On Apr 23, 2025, at 04:17, Richard Biener wrote: > >> I have met the following issue when I tried to implement the following into >> tree-object-size.cc: >> (And this took me quite some time, still don’t know what’s the best solution) >> >>> On Apr 16, 20

Re: [PATCH] modulo-sched: reject loop conditions when not decrementing with one [PR 116479]

On Wed, Apr 23, 2025 at 04:46:04PM +0100, Andre Vieira (lists) wrote: > On 23/04/2025 16:22, Jakub Jelinek wrote: > > On Wed, Apr 23, 2025 at 03:57:58PM +0100, Andre Vieira (lists) wrote: > > > +++ b/gcc/testsuite/gcc.target/aarch64/pr116479.c > > > @@ -0,0 +1,20 @@ > > > +/* PR 116479 */ > > > +/*

Re: [PATCH] modulo-sched: reject loop conditions when not decrementing with one [PR 116479]

On 23/04/2025 16:22, Jakub Jelinek wrote: On Wed, Apr 23, 2025 at 03:57:58PM +0100, Andre Vieira (lists) wrote: +++ b/gcc/testsuite/gcc.target/aarch64/pr116479.c @@ -0,0 +1,20 @@ +/* PR 116479 */ +/* { dg-do run } */ +/* { dg-additional-options "-O -funroll-loops -finline-stringops -fmodulo-s

Re: [PATCH] modulo-sched: reject loop conditions when not decrementing with one [PR 116479]

On Wed, Apr 23, 2025 at 03:57:58PM +0100, Andre Vieira (lists) wrote: > +++ b/gcc/testsuite/gcc.target/aarch64/pr116479.c > @@ -0,0 +1,20 @@ > +/* PR 116479 */ > +/* { dg-do run } */ > +/* { dg-additional-options "-O -funroll-loops -finline-stringops > -fmodulo-sched --param=max-iterations-computa

Re: [PATCH 30/61] MSA: Make MSA and microMIPS R5 unsupported

HTEC Public Hi, > > There are no platforms nor simulators for MSA and microMIPS R5 so > > turning off this support for now. > > > > gcc/ChangeLog: > > > > * config/mips/mips.cc (mips_option_override): Error out for > > -mmicromips -mmsa. > OK and pushed to the trunk. > Jeff We have s

[PATCH] modulo-sched: reject loop conditions when not decrementing with one [PR 116479]

In the commit titled 'doloop: Add support for predicated vectorized loops' the doloop_condition_get function was changed to accept loops with decrements larger than 1. This patch rejects such loops for modulo-sched. I've put the test for this in the aarch64 testsuite, but I just realized eve

Re: [PATCH] s390: Allow 5+ argument tail-calls in some special cases [PR119873]

On Wed, Apr 23, 2025 at 04:23:37PM +0200, Stefan Schulze Frielinghaus wrote: > > So, the following patch checks for this special case, where the argument > > which uses %r6 is passed in a single register and it is passed default > > definition of SSA_NAME of a PARM_DECL with the same DECL_INCOMING_

Re: [PATCH] s390: Allow 5+ argument tail-calls in some special cases [PR119873]

Hi Jakub, On Tue, Apr 22, 2025 at 10:41:29AM +0200, Jakub Jelinek wrote: > Hi! > > protobuf (and therefore firefox too) currently doesn't build on s390*-linux. > The problem is that it uses [[clang::musttail]] attribute heavily, and in > llvm (IMHO llvm bug) [[clang::musttail]] calls with 5+ argu

[PATCH] libstdc++: Update baseline symbols for powerpc-linux and powerpc64-linux

* config/abi/post/powerpc-linux-gnu/baseline_symbols.txt: Update. * config/abi/post/powerpc64-linux-gnu/32/baseline_symbols.txt: Update. * config/abi/post/powerpc64-linux-gnu/baseline_symbols.txt: Update. --- .../abi/post/powerpc-linux-gnu/baseline_symbols.txt | 11 ++

Re: [PATCH] libstdc++: Update baseline symbols for powerpc-linux and powerpc64-linux

On Wed, 23 Apr 2025 at 14:41, Andreas Schwab wrote: > > * config/abi/post/powerpc-linux-gnu/baseline_symbols.txt: Update. > * config/abi/post/powerpc64-linux-gnu/32/baseline_symbols.txt: Update. > * config/abi/post/powerpc64-linux-gnu/baseline_symbols.txt: Update. OK for t

RE: [PATCH] Add a bootstrap-native build config

> -Original Message- > From: Jakub Jelinek > Sent: Wednesday, April 23, 2025 10:39 AM > To: Tamar Christina > Cc: Richard Biener ; Andi Kleen > ; GCC Patches > Subject: Re: [PATCH] Add a bootstrap-native build config > > On Wed, Apr 23, 2025 at 09:36:11AM +, Tamar Christina wrote: >

RE: [PATCH]middle-end: Add new "max" vector cost model

> -Original Message- > From: Richard Biener > Sent: Wednesday, April 23, 2025 9:37 AM > To: Tamar Christina > Cc: gcc-patches@gcc.gnu.org; nd ; Richard Sandiford > > Subject: Re: [PATCH]middle-end: Add new "max" vector cost model > > On Wed, 23 Apr 2025, Richard Biener wrote: > > > On

Re: [PATCH] libstdc++: Minimalize temporary allocations when width is specified [PR109162]

On Wed, Apr 23, 2025 at 2:03 PM Tomasz Kamiński wrote: > When width parameter is specified for formatting range, tuple or escaped > presentation of string, we used to format characters to temporary string, > and write produce sequence padded according to the spec. However, once the > estimated wi

[PATCH] libstdc++: Minimalize temporary allocations when width is specified [PR109162]

When width parameter is specified for formatting range, tuple or escaped presentation of string, we used to format characters to temporary string, and write produce sequence padded according to the spec. However, once the estimated width of formatted representation of input is larger than the value

[PATCH v2] Document AArch64 changes for GCC 15

Thanks for all the feedback. I've tried to address it in the version below. I'll push later today if there are no further comments. Richard The list is structured as: - new configurations - command-line changes - ACLE changes - everything else As usual, the list of new architectures, CPUs, a

Re: [PATCH] Document AArch64 changes for GCC 15

Evgeny Karpov writes: > Tuesday, April 23, 2025 > Richard Sandiford wrote: >> Thanks the summary. Does the entry below look ok? >> >> Support has been added for the AArch64 MinGW target >>(aarch64-w64-mingw32). At present, this target >>supports C and C++ for base Armv8-A, but with som

Re: [PATCH 1/3] match: Move `(cmp (cond @0 @1 @2) @3)` simplification after the bool compare simplifcation

On Wed, Apr 23, 2025 at 5:58 AM Andrew Pinski wrote: > > This moves the `(cmp (cond @0 @1 @2) @3)` simplifcation to be after the > boolean comparison > simplifcations so that we don't end up simplifing into the same thing for a > GIMPLE_COND. OK. Richard. > gcc/ChangeLog: > > * match.

[COMMITTED] testsuite: Skip g++.dg/eh/pr119507.C on Solaris/SPARC with as

The new g++.dg/eh/pr119507.C test FAILs on Solaris/SPARC with the native as: FAIL: g++.dg/eh/pr119507.C -std=gnu++17 scan-assembler-times .section[\\t ][^\\n]*.gcc_except_table._Z6comdatv 1 FAIL: g++.dg/eh/pr119507.C -std=gnu++17 scan-assembler-times .section[\\t ][^\\n]*.gcc_except_table._Z

Re: [PATCH 07/61] Testsuite: Fix tests properly for compact-branches

HTEC Public Hi, > This likely needs to be updated for the trunk. > Before: > === gcc Summary === > # of expected passes95 > # of unexpected failures25 > After: > === gcc Summary === > # of expected passes70 > # of unexpected

Re: [PATCH] GCN: Properly switch sections in 'gcn_hsa_declare_function_name' [PR119737]

On 22/04/2025 21:41, Thomas Schwinge wrote: From: Andrew Pinski There are GCN/C++ target as well as offloading codes, where the hard-coded section names in 'gcn_hsa_declare_function_name' do not fit, and assembly thus fails: LLVM ERROR: Size expression must be absolute. This commit progr

RE: [PATCH]middle-end: Add new "max" vector cost model

On Wed, 23 Apr 2025, Tamar Christina wrote: > > -Original Message- > > From: Richard Biener > > Sent: Wednesday, April 23, 2025 10:14 AM > > To: Tamar Christina > > Cc: Richard Sandiford ; gcc-patches@gcc.gnu.org; > > nd > > Subject: RE: [PATCH]middle-end: Add new "max" vector cost mode

RE: [PATCH]middle-end: Add new "max" vector cost model

On Wed, 23 Apr 2025, Tamar Christina wrote: > > -Original Message- > > From: Richard Biener > > Sent: Wednesday, April 23, 2025 9:46 AM > > To: Tamar Christina > > Cc: gcc-patches@gcc.gnu.org; nd ; Richard Sandiford > > > > Subject: RE: [PATCH]middle-end: Add new "max" vector cost model

Re: [PATCH] Add a bootstrap-native build config

On Wed, Apr 23, 2025 at 10:05:25AM +, Tamar Christina wrote: > > -Original Message- > > From: Jakub Jelinek > > Sent: Wednesday, April 23, 2025 10:39 AM > > To: Tamar Christina > > Cc: Richard Biener ; Andi Kleen > > ; GCC Patches > > Subject: Re: [PATCH] Add a bootstrap-native build

Re: [PATCH] Add a bootstrap-native build config

On Wed, Apr 23, 2025 at 09:36:11AM +, Tamar Christina wrote: > On AArch64 it does but only if no other > tuning options are specified. That is the case on x86 as well, -march=native -mtune=znver5 will still tune for znver5, but -march=native will tune for native. Jakub

RE: [PATCH] Add a bootstrap-native build config

> -Original Message- > From: Richard Biener > Sent: Wednesday, April 23, 2025 9:19 AM > To: Andi Kleen ; GCC Patches > Subject: Re: [PATCH] Add a bootstrap-native build config > > On Tue, Apr 22, 2025 at 5:43 PM Andi Kleen wrote: > > > > On 2025-04-22 13:22, Richard Biener wrote: > > >

RE: [PATCH]middle-end: Add new "max" vector cost model

> -Original Message- > From: Richard Biener > Sent: Wednesday, April 23, 2025 10:14 AM > To: Tamar Christina > Cc: Richard Sandiford ; gcc-patches@gcc.gnu.org; > nd > Subject: RE: [PATCH]middle-end: Add new "max" vector cost model > > On Wed, 23 Apr 2025, Tamar Christina wrote: > > > >

RE: [PATCH]middle-end: Add new "max" vector cost model

On Wed, 23 Apr 2025, Tamar Christina wrote: > > -Original Message- > > From: Richard Sandiford > > Sent: Wednesday, April 23, 2025 9:45 AM > > To: Tamar Christina > > Cc: Richard Biener ; gcc-patches@gcc.gnu.org; nd > > > > Subject: Re: [PATCH]middle-end: Add new "max" vector cost model

[PATCH] simplify-rtx: Combine bitwise operations in more cases

This patch transforms RTL expressions of the form (subreg (not X) off) into (not (subreg X off)) when the subreg is an operand of a bitwise AND or OR. This transformation can expose opportunities to combine a NOT operation with the bitwise AND/OR. For example, it improves the codegen of the follow

Re: [PATCH 3/3] gimple-fold: Don't replace `bool_var != 0` with `bool_var` inside GIMPLE_COND

On Wed, Apr 23, 2025 at 6:00 AM Andrew Pinski wrote: > > Since match and simplify will simplify `bool_var != 0` to just `bool_var` and > this is inside a GIMPLE_COND, fold_stmt will return true but nothing has > changed. > So let's just reject the replacement if we are replacing with the same >

RE: [PATCH]middle-end: Add new "max" vector cost model

> -Original Message- > From: Richard Sandiford > Sent: Wednesday, April 23, 2025 9:45 AM > To: Tamar Christina > Cc: Richard Biener ; gcc-patches@gcc.gnu.org; nd > > Subject: Re: [PATCH]middle-end: Add new "max" vector cost model > > Tamar Christina writes: > >> -Original Message--

Re: [PATCH 2/3] gimple-fold: Return early for GIMPLE_COND with true/false

On Wed, Apr 23, 2025 at 5:59 AM Andrew Pinski wrote: > > To speed up things slightly so not needing to call all the way through > to match and simplify, we should return early for true/false on GIMPLE_COND. I think we'd still canonicalize the various forms matched by gimple_cond_true/false_p to a

[PATCH] Document AArch64 changes for GCC 15

Tuesday, April 23, 2025 Richard Sandiford wrote: > Thanks the summary. Does the entry below look ok? > > Support has been added for the AArch64 MinGW target >(aarch64-w64-mingw32). At present, this target >supports C and C++ for base Armv8-A, but with some caveats: > > Although

RE: [PATCH]middle-end: Add new "max" vector cost model

> -Original Message- > From: Richard Biener > Sent: Wednesday, April 23, 2025 9:46 AM > To: Tamar Christina > Cc: gcc-patches@gcc.gnu.org; nd ; Richard Sandiford > > Subject: RE: [PATCH]middle-end: Add new "max" vector cost model > > On Wed, 23 Apr 2025, Tamar Christina wrote: > > > >

Re: [PATCH]middle-end: Add new "max" vector cost model

On Wed, 23 Apr 2025, Richard Biener wrote: > On Wed, 23 Apr 2025, Tamar Christina wrote: > > > Hi All, > > > > This patch proposes a new vector cost model called "max". The cost model > > is an > > intersection between two of our existing cost models. Like `unlimited` it > > disables the cost

RE: [PATCH]middle-end: Add new "max" vector cost model

On Wed, 23 Apr 2025, Tamar Christina wrote: > > -Original Message- > > From: Richard Biener > > Sent: Wednesday, April 23, 2025 9:37 AM > > To: Tamar Christina > > Cc: gcc-patches@gcc.gnu.org; nd ; Richard Sandiford > > > > Subject: Re: [PATCH]middle-end: Add new "max" vector cost model

Re: [PATCH]middle-end: Add new "max" vector cost model

Tamar Christina writes: >> -Original Message- >> From: Richard Biener >> Sent: Wednesday, April 23, 2025 9:31 AM >> To: Tamar Christina >> Cc: gcc-patches@gcc.gnu.org; nd ; Richard Sandiford >> >> Subject: Re: [PATCH]middle-end: Add new "max" vector cost model >> >> On Wed, 23 Apr 2025

RE: [PATCH]middle-end: Add new "max" vector cost model

> -Original Message- > From: Richard Biener > Sent: Wednesday, April 23, 2025 9:31 AM > To: Tamar Christina > Cc: gcc-patches@gcc.gnu.org; nd ; Richard Sandiford > > Subject: Re: [PATCH]middle-end: Add new "max" vector cost model > > On Wed, 23 Apr 2025, Tamar Christina wrote: > > > Hi

Re: [PATCH] Document AArch64 changes for GCC 15

Andrew Pinski writes: > On Tue, Apr 22, 2025 at 5:32 AM Richard Sandiford > wrote: >> >> The list is structured as: >> >> - new configurations >> - command-line changes >> - ACLE changes >> - everything else >> >> As usual, the list of new architectures, CPUs, and features is from a >> purely mec

Re: [PATCH]middle-end: Add new "max" vector cost model

On Wed, 23 Apr 2025, Tamar Christina wrote: > Hi All, > > This patch proposes a new vector cost model called "max". The cost model is > an > intersection between two of our existing cost models. Like `unlimited` it > disables the costing vs scalar and assumes all vectorization to be profitable

Re: [PATCH] Document AArch64 changes for GCC 15

Evgeny Karpov writes: > Tuesday, April 22, 2025 > "Richard Sandiford" wrote: > >> +  Support has been added for the AArch64 MinGW target >> +    (aarch64-w64-mingw32).  At present, this target only >> +    supports C, but further work is planned. >> +  > > Thank you for the release summary for A

Re: [PATCH]middle-end: Add new "max" vector cost model

> On 23 Apr 2025, at 08:37, Tamar Christina wrote: > > Hi All, > > This patch proposes a new vector cost model called "max". The cost model is > an > intersection between two of our existing cost models. Like `unlimited` it > disables the costing vs scalar and assumes all vectorization to

Re: [PATCH] Add a bootstrap-native build config

On Tue, Apr 22, 2025 at 5:43 PM Andi Kleen wrote: > > On 2025-04-22 13:22, Richard Biener wrote: > > On Sat, Apr 12, 2025 at 5:09 PM Andi Kleen wrote: > >> > >> From: Andi Kleen > >> > >> ... that uses -march=native -mtune=native to build a compiler > >> optimized > >> for the host. > > > > -mar

Re: Help: Re: Questions on replacing a structure pointer reference to a call to .ACCESS_WITH_SIZE in C FE

On Tue, Apr 22, 2025 at 5:22 PM Qing Zhao wrote: > > Hi, > > I have met the following issue when I tried to implement the following into > tree-object-size.cc: > (And this took me quite some time, still don’t know what’s the best solution) > > > On Apr 16, 2025, at 10:46, Qing Zhao wrote: > > >

Re: [Fortran, Patch, PR119200, v1] Use correct locus while check()ing coarray functions.

Hi Harald, thanks for the review. > this is bordering on the obvious and thus OK, except for: Well, it wasn't so obvious, when was able to add a mistake ;-) I have fixed that and committed as gcc-16-94-gcc2716a3f52. Thanks again for the review, Andre > > @@ -6967,7 +6972,8 @@ gfc_che

Re: [PATCH v1 0/4] Refactor long function expand_const_vector

These patches LGTM from myside. But please wait for other folks to comment. The series LGTM as well. But please wait with merging until GCC 15.1 is released (as requested by the release maintainers). -- Regards Robin

[PATCH]middle-end: Add new "max" vector cost model

Hi All, This patch proposes a new vector cost model called "max". The cost model is an intersection between two of our existing cost models. Like `unlimited` it disables the costing vs scalar and assumes all vectorization to be profitable. But unlike unlimited it does not fully disable the vect

Re: [PATCH v2 1/3] RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR cost

The only thing I think we want for the patch (as Pan also raised last time) is the param to set those .vx costs to zero in order to ensure the tests test the right thing (--param=vx_preferred/gr2vr_cost or something). I see, shall we start a new series for this? AFAIK, we may need some more al

Re: [PATCH] testsuite: AMDGCN test for vect-early-break_38.c as well to consistent architecture [PR119286]

On Wed, 23 Apr 2025, Tamar Christina wrote: > Hi All, > > I had missed this one during the AMDGCN test failures. > > Like vect-early-break_18.c this test is also scalaring the > loads and thus leading to unexpected vectorization for this > testcase. > > Bootstrapped Regtested on aarch64-none-li

[committed] OpenMP: Add libgomp.fortran/target-enter-data-8.f90

Looking through old patches, I came across this testcase. It was originally part of the patch [Patch] Fortran/OpenMP: Fix DT struct-component with 'alloc' and array descr https://gcc.gnu.org/pipermail/gcc-patches/2022-November/604887.html under the name testsuite/libgomp.fortran/target-enter-da

Re: docs: Document PFA support in GCC-15 changes

On Wed, 23 Apr 2025, Tamar Christina wrote: > Hi All, > > This documents the PFA support in GCC-15. > > Ok for master? OK. > Thanks, > Tamar > > --- > diff --git a/htdocs/gcc-15/changes.html b/htdocs/gcc-15/changes.html > index > f03e29c8581f2749a968e592eae2e40ce3ca8521..7fb70b993c56ff43c09a

docs: Document PFA support in GCC-15 changes

Hi All, This documents the PFA support in GCC-15. Ok for master? Thanks, Tamar --- diff --git a/htdocs/gcc-15/changes.html b/htdocs/gcc-15/changes.html index f03e29c8581f2749a968e592eae2e40ce3ca8521..7fb70b993c56ff43c09aeb7bfaa4479385679dec 100644 --- a/htdocs/gcc-15/changes.html +++ b/htdocs