[pushed] wwwdocs: readings: Switch www.andestech.com to https

--- htdocs/readings.html | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/htdocs/readings.html b/htdocs/readings.html index 6ca9cc07..66f5ce0b 100644 --- a/htdocs/readings.html +++ b/htdocs/readings.html @@ -71,7 +71,7 @@ names. andes (nds32) Manufacturer: Various licenses

[pushed] wwwdocs: gcc-3.*: Remove links to MTL project from 20 years ago

The entire osl.iu.edu site has gone away without direct replacement. This complements commit fb0591c5b3e8 from July where we removed the download links. --- htdocs/gcc-3.1/criteria.html | 2 +- htdocs/gcc-3.3/criteria.html | 2 +- htdocs/gcc-3.4/criteria.html | 2 +- 3 files changed, 3 insertions

Re: [PING][PATCH 00/15] Fix data races with sub-longword accesses on Alpha

On Sun, 15 Dec 2024, Jeff Law wrote: > > Ping for: > > > > > > > >

Re: [PING][PATCH 00/15] Fix data races with sub-longword accesses on Alpha

On Sat, 14 Dec 2024, Jeff Law wrote: > > Ping for: > > > > > > > > (this will presumably need tweak

[PATCH v3] LoongArch: Implement vector cbranch optab for LSX and LASX

In order to support vectorization of loops with multiple exits, this patch adds the implementation of the conditional branch optab for LoongArch LSX/LASX instructions. This patch causes the gen-vect-{2,25}.c tests to fail. This is because the support for vectorizing loops with multiple exits has

Re: [pushed][PATCH] LoongArch: Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS hook

Pushed to r15-6432. 在 2024/12/17 上午10:41, Jiahao Xu 写道: The hook changes the allocno class to either FP_REGS or GR_REGS depending on the mode of the register. This results in better register allocation overall, fewer spills and reduced codesize - particularly in SPEC2017 lbm. gcc/ChangeLog:

[PATCH V3 1/2] RISC-V: Add intrinsics support for SiFive Xsfvcp extensions.

From: yulong This commit adds intrinsics support for Xsfvcp extension. Diff with V2: Change the RTL mode from unspec to unspec_volatile. Co-Authored by: Jiawei Chen Co-Authored by: Shihua Liao Co-Authored by: Yixuan Chen gcc/ChangeLog: * config/riscv/constraints.md (Ou01): New cons

[PATCH V3 2/2] RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions.

From: Liao Shihua This commit adds testcases for Xsfvcp. Co-Authored by: Jiawei Chen Co-Authored by: Shihua Liao Co-Authored by: Yixuan Chen gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/xsfvector/sf_vc_f.c: New test. * gcc.target/riscv/rvv/xsfvector/sf_vc_i.c: New test.

[PATCH V3 0/2] RISC-V: Add intrinsics support and testcases for SiFive Xsfvcp extension.

From: yulong This patch implements the Sifvie vendor extension Xsfvfnrclipxfqf[1] support to gcc. Providing support for FP32-to-int8 Ranged Clip instrctions. [1] https://www.sifive.com/document-file/sifive-vector-coprocessor-interface-vcix-software Co-Authored by: Jiawei Chen Co-Authored by