Pushed to r14-6847.
在 2023/12/25 上午11:20, Li Wei 写道:
We found that using the latest compiled gcc will cause a miscompare error
when running spec2006 400.perlbench test with -flto turned on. After testing,
it was found that only the LoongArch architecture will report errors.
The first error comm
Pused to r14-6848.
在 2023/12/22 下午4:22, Chenghui Pan 写道:
When investigaing failure of gcc.dg/vect/slp-reduc-sad.c, following
instruction block are being generated by vec_concatv32qi (which is
generated by vec_initv32qiv16qi) at entrance of foo() function:
vldx$vr3,$r5,$r6
vld $vr2
Pushed to r14-6849.
在 2023/12/22 下午4:18, Chenghui Pan 写道:
Following code will cause ICE on LoongArch target:
#include
extern void bar (__m128i, __m128i);
__m128i a;
void
foo ()
{
bar (a, a);
}
It is caused by missing constraint definition in mov_lsx. This
patch fi
LGTM!
Thanks!
在 2023/12/24 下午8:33, Xi Ruoyao 写道:
gcc/ChangeLog:
* config/loongarch/loongarch.md (rotl3):
New define_expand.
* config/loongarch/simd.md (vrotl3): Likewise.
(rotl3): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/rotl-with-rotr
在 2023/12/27 上午6:37, Xi Ruoyao 写道:
The GCC internal doc says:
X might be a pseudo-register or a 'subreg' of a pseudo-register,
which could either be in a hard register or in memory. Use
'true_regnum' to find out; it will return -1 if the pseudo is in
memory and the har
在 2023/12/23 下午6:44, Xi Ruoyao 写道:
On Sat, 2023-12-23 at 10:29 +0800, chenglulu wrote:
The performance drop has nothing to do with this patch. I found that the h264
performance compiled
by r14-6787 compared to r14-6421 dropped by 6.4%.
Then I guess we should create a bug report...
The code h
Hi Jeff,
Yes, I will change soemthing in vector_csr_operand in the following
patches.
Constraints will be added that the AVL cannot be encoded as an
immediate for xtheadvecotr vsetvl.
Joshua
--
发件人：Jeff Law
发送时间：2023年12月21日(
Thanks Feng, the patch is LGTM from my side, I am happy to accept
vector crypto stuffs for GCC 14, it's mostly intrinsic stuff, and the
only few non-intrinsic stuff also low risk enough (e.g. vrol, vctz)
On Fri, Dec 22, 2023 at 10:04 AM Feng Wang wrote:
>
> 2023-12-22 09:59 Feng Wang wrote:
>
>
Hi Jeff,
Perhaps fold_fault_load cannot be moved to riscv-protos.h since
gimple_folder is declared in riscv-vector-builtins.h. It's not reasonable
to include riscv-vector-builtins.h in riscv-protos.h.
In fact, fold_fault_load is defined specially for some builtin functions, and
it would be bette
send V2 with test tweak:
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641447.html
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-12-27 09:52
To: gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH] RISC-V: Disallow transformation into VL
Notice we have this following situation:
vsetivlizero,4,e32,m1,ta,ma
vlseg4e32.v v4,(a5)
vlseg4e32.v v12,(a3)
vsetvli a5,zero,e32,m1,tu,ma ---> This is redundant since
VLMAX AVL = 4 when it is fixed-vlmax
vfadd.vfv3,v13,f
Notice we have this following situation:
vsetivlizero,4,e32,m1,ta,ma
vlseg4e32.v v4,(a5)
vlseg4e32.v v12,(a3)
vsetvli a5,zero,e32,m1,tu,ma ---> This is redundant since
VLMAX AVL = 4 when it is fixed-vlmax
vfadd.vfv3,v13,f
Ping, thanks.
I did some benchmarks, and there is some significant time optimization for
float/double types,
while there is no regression for long double type.
Hi Will,
Will Hawkins writes:
> On Thu, Dec 21, 2023 at 4:26 PM Arsen Arsenović wrote:
>>
>> libstdc++-v3/ChangeLog:
>>
>
> ... snip ...
>
>> + void
>> + _M_jump_in(_Coro_handle __rest, _Coro_handle __new) noexcept
>> + {
>> + __glibcxx_assert(&__new.promise()._M_nest
The GCC internal doc says:
X might be a pseudo-register or a 'subreg' of a pseudo-register,
which could either be in a hard register or in memory. Use
'true_regnum' to find out; it will return -1 if the pseudo is in
memory and the hard register number if it is in a register.
On 12/20/2023 2:55 PM, Edwin Lu wrote:
On 12/20/2023 10:57 AM, Jeff Law wrote:
On 12/15/23 11:53, Edwin Lu wrote:
This patch copies the vector reservations from generic-ooo.md and
inserts them into generic.md and sifive.md. The vector pipelines are
necessary to avoid an ICE from the assert
On Thu, 21 Dec 2023 at 00:00, Richard Sandiford
wrote:
>
> If cse sees:
>
> (set (reg R) (const_vector [A B ...]))
>
> it creates fake sets of the form:
>
> (set R[0] A)
> (set R[1] B)
> ...
>
> (with R[n] replaced by appropriate rtl) and then adds them to the tables
> in the same way as f
On Thu, Dec 21, 2023 at 4:26 PM Arsen Arsenović wrote:
>
> libstdc++-v3/ChangeLog:
>
... snip ...
> + void
> + _M_jump_in(_Coro_handle __rest, _Coro_handle __new) noexcept
> + {
> + __glibcxx_assert(&__new.promise()._M_nest == this);
> + __glibcxx_assert(this->_
On 12/23/23 02:10, waffl3x wrote:
On Friday, December 22nd, 2023 at 10:26 AM, Jason Merrill
wrote:
On 12/22/23 04:01, waffl3x wrote:
int n = 0;
auto f = [](this Self){
static_assert(__is_same (decltype(n), int));
decltype((n)) a; // { dg-error {is not captured} }
};
f();
Could you clarify
gcc/testsuite/ChangeLog:
* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-10.c: Fix typo.
---
.../gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-10.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-10.
From: Pan Li
This patch would like to XFAIL the test case pr30957-1.c for the RVV when
build the elf with some configurations (list at the end of the log)
It will be vectorized during vect_transform_loop with a variable factor.
It won't benefit from unrolling/peeling and mark the loop->unroll as
Tweak some codes of dynamic LMUL cost model to make computation more
predictable and accurate.
Tested on both RV32 and RV64 no regression.
Committed.
PR target/113112
gcc/ChangeLog:
* config/riscv/riscv-vector-costs.cc (compute_estimated_lmul): Tweak
LMUL estimation.
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