[PATCH V3 3/3] RISC-V: Add C intrinsic for Scalar Bitmanip Extension

This patch adds C intrinsics for Bitmanip Extension. RISCV_BUILTIN_NO_PREFIX is a new riscv_builtin_description like RISCV_BUILTIN. But it uses CODE_FOR_##INSN rather than CODE_FOR_riscv_##INSN. Changed orcb, clmul, brev8 pattern's mode form X to GPR because orcbsi, clmul_si, brev8_si are both in

[PATCH V3 2/3] RISC-V: Add C intrinsic for Scalar Crypto Extension

This patch adds C intrinsics for Scalar Crypto Extension. gcc/ChangeLog: * config.gcc: Include riscv_crypto.h. * config/riscv/riscv_crypto.h: New file. gcc/testsuite/ChangeLog: * gcc.target/riscv/scalar_crypto_intrinsic-32.c: New test. * gcc.target/riscv/scalar_c

[PATCH V3 0/3] RISC-V: Add intrinsics for Bitmanip and Scalar Crypto extensions

Update v2 -> v3: 1. Change pattern mode form X to GPR in orcb, clmul, and brev8. 2. Add emulated testsuite. 3. Removed duplicate testsuite between built-in and intrinsic. 4. Typo fix. Update v1 -> v2: 1. Rename *_intrinsic-* to *_intrinsic-XLEN. 2. Typo fix. 3. Intrinsics with immed

[PATCH V3 1/3] RISC-V: Remove the Scalar Bitmanip and Crypto Built-In function testsuites

The serials patch provides a mapping from the RV intrinsics to the builtin names. There are some duplicates testsuites between intrinsic and built-in function. Remove the Scalar Bitmanip and Scalar Crypto Built-In function testsuites that will be included in the intrinsic functions. gcc/testsuit

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[PATCH v2] LoongArch: Replace -mexplicit-relocs=auto simple-used address peephole2 with combine

The problem with peephole2 is it uses a naive sliding-window algorithm and misses many cases. For example: float a[1]; float t() { return a[0] + a[8000]; } is compiled to: la.local$r13,a la.local$r12,a+32768 fld.s $f1,$r13,0 fld.s $f0,$r12,-768

Re: [PATCH] RISC-V: Move RVV V_REGS liveness computation into analyze_loop_vinfo

LGTM :) On Mon, Dec 25, 2023 at 5:18 PM Juzhe-Zhong wrote: > > Currently, we compute RVV V_REGS liveness during better_main_loop_than_p > which is not appropriate > time to do that since we for example, when have the codes will finally pick > LMUL = 8 vectorization > factor, we compute liveness

[PATCH][committed]middle-end: explicitly initialize vec_stmts [PR113132]

Hi All, when configured with --enable-checking=release we get a false positive on the use of vec_stmts as the compiler seems unable to notice it gets initialized through the pass-by-reference. This explicitly initializes the local. Bootstrapped Regtested on x86_64-pc-linux-gnu and no issues. Co

[r14-6822 Regression] FAIL: 25_algorithms/partition_point/constrained.cc -std=gnu++26 execution test on Linux/x86_64

On Linux/x86_64, 01f4251b8775c832a92d55e2df57c9ac72eaceef is the first bad commit commit 01f4251b8775c832a92d55e2df57c9ac72eaceef Author: Tamar Christina Date: Sun Dec 24 19:18:12 2023 + middle-end: Support vectorization of loops with multiple exits. caused FAIL: gcc.target/i386/sse4

[r14-6822 Regression] FAIL: 25_algorithms/partition_point/constrained.cc -std=gnu++26 execution test on Linux/x86_64

On Linux/x86_64, 01f4251b8775c832a92d55e2df57c9ac72eaceef is the first bad commit commit 01f4251b8775c832a92d55e2df57c9ac72eaceef Author: Tamar Christina Date: Sun Dec 24 19:18:12 2023 + middle-end: Support vectorization of loops with multiple exits. caused FAIL: 25_algorithms/partit

[r14-6796 Regression] FAIL: g++.dg/abi/mangle-regparm1a.C -std=gnu++98 (test for warnings, line 6) on Linux/x86_64

On Linux/x86_64, 2fa122cae50cd87c1262c4ec18a783ee9bbbdaaa is the first bad commit commit 2fa122cae50cd87c1262c4ec18a783ee9bbbdaaa Author: Jason Merrill Date: Thu Dec 21 16:16:37 2023 -0500 testsuite: suppress mangling compatibility aliases caused FAIL: g++.dg/abi/mangle-regparm1a.C -std

Re: Ping: [PATCH] LoongArch: Replace -mexplicit-relocs=auto simple-used address peephole2 with combine

On Mon, 2023-12-25 at 10:08 +0800, chenglulu wrote: > > 在 2023/12/24 下午8:59, Xi Ruoyao 写道: > > On Sat, 2023-12-23 at 18:47 +0800, Xi Ruoyao wrote: > > > On Sat, 2023-12-23 at 18:44 +0800, Xi Ruoyao wrote: > > > > On Sat, 2023-12-23 at 10:29 +0800, chenglulu wrote: > > > > > > The performance drop

Re: [PATCH v1] LoongArch: Fixed bug in *bstrins__for_ior_mask template.

On Mon, 2023-12-25 at 11:20 +0800, Li Wei wrote: > We found that using the latest compiled gcc will cause a miscompare error > when running spec2006 400.perlbench test with -flto turned on.  After testing, > it was found that only the LoongArch architecture will report errors. > The first error com

[PATCH] RISC-V: Move RVV V_REGS liveness computation into analyze_loop_vinfo

Currently, we compute RVV V_REGS liveness during better_main_loop_than_p which is not appropriate time to do that since we for example, when have the codes will finally pick LMUL = 8 vectorization factor, we compute liveness for LMUL = 8 multiple times which are redundant. Since we have leverage

[PATCH] RISC-V: Fix misaligned stack offset for interrupt function

`interrupt` function will backup fcsr register, but it fixed to SImode, it's not big issue since fcsr only used 8 bits so far, however the offset should still using UNITS_PER_WORD to prevent the stack offset become non 8 byte aligned, it will cause problem for RV64. gcc/ChangeLog: * confi

Re: [r14-6770 Regression] FAIL: gcc.dg/gnu23-tag-4.c (test for excess errors) on Linux/x86_64

Yes, I am testing a patch. The DECL_FIELD_BIT_OFFSET are set inconsistently for some reason. Martin Am Montag, dem 25.12.2023 um 07:49 + schrieb Jiang, Haochen: > It is not a target specific issue, it will fail if we enabled AVX. > > e.g.: > > $ /export/users/haochenj/env/build_no_bootst

Re: [PATCH v4 4/6] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.

OK. juzhe.zh...@rivai.ai From: Jun Sha (Joshua) Date: 2023-12-25 16:14 To: gcc-patches CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu Subject: [PATCH v4 4/6] RISC-V: Adds the prefix "th." for the instruc

[PATCH v4 4/6] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.

This patch adds th. prefix to all XTheadVector instructions by implementing new assembly output functions. In this version, we follow Kito's suggestions and only check the prefix is 'v', so that no extra attribute is needed. gcc/ChangeLog: * config/riscv/riscv-protos.h (riscv_asm_output