On Mon, Dec 4, 2023 at 4:58 PM Vincenzo Palazzo
wrote:
>
> This commit is specifically targeting enhancements in
> Nix support for GCC development. This initiative stems
> from the recognized need within our community for a more
> streamlined and efficient development process when using Nix.
I th
Am Montag, dem 04.12.2023 um 19:51 +0100 schrieb Jakub Jelinek:
> On Mon, Dec 04, 2023 at 01:27:32PM -0500, Siddhesh Poyarekar wrote:
> > [Branching this into a separate conversation to avoid derailing the patch,
> > which isn't directly related]
> >
> > On 2023-12-04 12:21, Martin Uecker wrote:
>
From: Kong Lingling
For NDD form AND insn, there are three splitter fixes after extending legacy
patterns.
1. APX NDD does not support high QImode registers like ah, bh, ch, dh, so for
some optimization splitters that generates highpart zero_extract for QImode
need to be prohibited under NDD pat
For TImode shifts, they are splitted by splitter functions, which assume
operands[0] and operands[1] to be the same. For the NDD alternative the
assumption may not be true so add split functions for NDD to emit the NDD
form instructions, and omit the handling of !64bit target split.
Although the N
On Fri, Dec 01, 2023 at 07:43:35PM -0500, Jason Merrill wrote:
> On 12/1/23 18:37, Marek Polacek wrote:
> > On Thu, Nov 30, 2023 at 06:34:01PM -0500, Jason Merrill wrote:
> > > On 11/23/23 11:46, Marek Polacek wrote:
> > > > v5 greatly simplifies the code.
> > >
> > > Indeed, it's much cleaner now
From: Kong Lingling
Similar to AND insn, two splitters need to be adjusted to prevent
misoptimizaiton for NDD OR/XOR.
Also adjust *one_cmplsi2_2_zext and its corresponding splitter that will
generate xor insn.
gcc/ChangeLog:
* config/i386/i386.md (3): Add new alternative for NDD
From: Kong Lingling
APX NDD provides an extra destination register operand for several gpr
related legacy insns, so a new alternative can be adopted to operand1
with "r" constraint.
This first patch supports NDD for add instruction, and keeps to use lea
when all operands are registers since lea
From: Kong Lingling
Similar to *add3_doubleword, operands[1] may not equal to operands[0] so
extra move is required.
gcc/ChangeLog:
* config/i386/i386.md (*sub3_doubleword): Add new alternative for
NDD, and emit move when operands[0] not equal to operands[1].
(*sub3_doub
Στις Δευ 4 Δεκ 2023, 21:22 ο χρήστης Richard Sandiford <
richard.sandif...@arm.com> έγραψε:
> Manos Anagnostakis writes:
> > This is an RTL pass that detects store forwarding from stores to larger
> loads (load pairs).
> >
> > This optimization is SPEC2017-driven and was found to be beneficial fo
On Mon, Dec 4, 2023 at 3:51 PM Uros Bizjak wrote:
>
> On Mon, Dec 4, 2023 at 8:11 AM Hongtao Liu wrote:
> >
> > On Fri, Dec 1, 2023 at 10:26 PM Richard Biener
> > wrote:
> > >
> > > On Fri, Dec 1, 2023 at 3:39 AM liuhongt wrote:
> > > >
> > > > > Hmm, I would suggest you put reg_needed into the
From: Kong Lingling
Legacy adc patterns are commonly adopted to TImode add, when extending TImode
add to NDD version, operands[0] and operands[1] can be different, so extra move
should be emitted if those patterns have optimization when adding const0_rtx.
NDD instructions will automatically zero
OK.
Regards
Robin
Hi!
When working on the previous patch I put [[]] [[]] asm (""); into a
testcase, but was surprised it wasn't parsed.
The problem is that when cp_parser_std_attribute_spec returns NULL, it
can mean 2 different things, one is that the next token(s) are neither
[[ nor alignas (in that case the calle
Ciao all,
>+1. I think this is best left to the distros.
What do you mean? this is not a package, it is an env shell in order
to build an work on GCC on NixOS.
NixOS has already the packages for GCC
Cheers,
Vincent.
On Tue, Dec 5, 2023 at 2:07 AM Jeff Law wrote:
>
>
>
> On 12/4/23 18:02,
Hi Haochen,
on 2023/12/1 10:41, HAO CHEN GUI wrote:
> Hi,
> SImode in float register is supported on P7 above. It causes "fctiw"
> can be generated on old 32-bit processors as the output operand of
typo? I guess you meant to say "can NOT"?
> fctiw insn is a SImode in float/double register. Th
Tested x86_64-pc-linux-gnu, applying to trunk.
-- 8< --
Mentioning a noreturn function does not involve an lvalue-rvalue
conversion.
gcc/cp/ChangeLog:
* constexpr.cc (potential_constant_expression_1): Fix
check for loading volatile lvalue.
gcc/testsuite/ChangeLog:
* g+
On Fri, 1 Dec 2023, Jonny Grant wrote:
>
>
> On 30/11/2023 23:56, Joseph Myers wrote:
> > On Thu, 30 Nov 2023, Jonny Grant wrote:
> >
> >> ChangeLog:
> >>
> >>htdocs/git.html: change example to use git:// and correct
> >>spelling repostiory -> repository .
> >
> > git:/
On 12/4/23 18:02, Andrew Pinski wrote:
On Mon, Dec 4, 2023 at 4:58 PM Vincenzo Palazzo
wrote:
This commit is specifically targeting enhancements in
Nix support for GCC development. This initiative stems
from the recognized need within our community for a more
streamlined and efficient devel
Hi Harald,
The patch is OK for mainline.
Thanks
Paul
On Mon, 4 Dec 2023 at 22:47, Harald Anlauf wrote:
> Dear all,
>
> the attached patch picks up an observation by Tobias that we did
> not specify the RESTRICT qualifier for optional arguments even
> if that was allowed. In principle this m
On Linux/x86_64,
de0ab339a795352c843f6e9b2dfce222f26588de is the first bad commit
commit de0ab339a795352c843f6e9b2dfce222f26588de
Author: Richard Biener
Date: Mon Dec 4 10:46:11 2023 +0100
tree-optimization/112827 - corrupt SCEV cache during SCCP
caused
FAIL: gcc.dg/tree-ssa/ssa-sink-16.
Hi!
Seems in 2017 attribute-specifier-seq[opt] was added to asm-declaration
and the change was voted in as a DR.
The following patch implements it by parsing the attributes and warning
about them.
I found one attribute parsing bug I'll send a fix for momentarily.
And there is another thing I wo
> -Original Message-
> From: Richard Biener
> Sent: Monday, December 4, 2023 6:22 AM
> To: Andrew Pinski (QUIC)
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH 3/3] MATCH: (convert)(zero_one !=/== 0/1) for outer
> type and zero_one type are the same
>
> On Sat, Dec 2, 2023 at 7:38 AM
gcc/ChangeLog:
* config/i386/i386.md (*3_1): Extend with a new
alternative to support NDD for SI/DI rotate, and adjust output
template.
(*si3_1_zext): Likewise.
(*3_1): Likewise for QI/HI modes.
(rcrsi2): Likewise, and use nonimmediate_operand for op
For left shift, there is an optimization TARGET_DOUBLE_WITH_ADD that shl
1 can be optimized to add. As NDD form of add requires src operand to
be register since NDD cannot take 2 memory src, we currently just keep
using NDD form shift instead of add.
The optimization TARGET_SHIFT1 will try to remo
This commit is specifically targeting enhancements in
Nix support for GCC development. This initiative stems
from the recognized need within our community for a more
streamlined and efficient development process when using Nix.
Signed-off-by: Vincenzo Palazzo
---
flake.lock | 60
For shld/shrd insns, the old pattern use match_dup 0 as its shift src and use
+r*m as its constraint. To support NDD we added new define_insns to handle NDD
form pattern with extra input and dest operand to be fixed in register.
gcc/ChangeLog:
* config/i386/i386.md (x86_64_shld_ndd): New
>> @@ -15402,6 +15450,8 @@ tsubst_decl (tree t, tree args, tsubst_flags_t
>> complain,
>> gcc_checking_assert (TYPE_MAIN_VARIANT (TREE_TYPE (ve))
>>== TYPE_MAIN_VARIANT (type));
>> SET_DECL_VALUE_EXPR (r, ve);
>> +
On Mon, 4 Dec 2023, Richard Biener wrote:
> The following adjusts the C FE specific qualified type building
> to preserve address-space info also for ARRAY_TYPE.
>
> Bootstrap / regtest running on x86_64-unknown-linux-gnu, OK?
OK.
--
Joseph S. Myers
jos...@codesourcery.com
Relevant bugzilla:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112848
Thanks,
Patrick
On Mon, Dec 4, 2023 at 11:20 PM Li, Pan2 wrote:
> Hi Richard,
>
> It looks like this patch result in one ICE for RISC-V backend for case
> tree-ssa.exp=ssa-sink-16.c, could you please help to double check abo
The insert iteration can be corrupted by foldings of replace_uses_by,
within this particular PHI replacement but also with subsequent ones.
Recompute the insert location before insertion instead.
This fixes an obvserved ICE of gcc.dg/tree-ssa/ssa-sink-16.c.
Bootstrapped and tested on x86_64-unkno
I am writing to submit a patch for consideration to be included
in the mainline GCC repository. The patch aims to improve the ease of
using Nix for GCC development, a challenge that several developers
in our community have faced.
In the event that there is no current maintainer willing to take
Am Montag, dem 04.12.2023 um 15:35 -0500 schrieb Siddhesh Poyarekar:
> On 2023-12-04 13:48, Martin Uecker wrote:
> > > I empathize with Jakub's stated use case though of keeping the C
> > > frontend support for testing purposes, but that could easily be done
> > > behind a flag, or by putting neste
On 12/4/23 18:38, Vincenzo Palazzo wrote:
Ciao all,
+1. I think this is best left to the distros.
What do you mean? this is not a package, it is an env shell in order
to build an work on GCC on NixOS.
Distro build procedures are not something the GCC project generally gets
involved with
On 12/3/23 05:13, Richard Sandiford wrote:
[Gah. In my head I'd sent this a few weeks ago, but it turns out
that I hadn't even got to the stage of writing the changlog...]
LRA keeps track of the biggest mode for both hard registers and
pseudos. The updates assume that the modes are ordered
Similar to LSHIFT, rshift do not need to omit $1 for NDD form.
gcc/ChangeLog:
* config/i386/i386.md (ashr3_cvt): Extend with new
alternatives to support NDD, and adjust output templates.
(*ashr3_1): Likewise for SI/DI mode.
(*lshr3_1): Likewise.
(*si3_1_zex
Hi!
The following testcase ICEs in the movabsq $(i32 << shift), r64 peephole2
I've added a while back to use smaller code than movabsq if possible.
If i32 is 0xfa1e0ff3 and shift is not divisible by 8, then it creates
an invalid insn (as 0xfa1e0ff3 CONST_INT is not allowed as
x86_64_immediate_oper
On 12/4/23 9:01 PM, Vincenzo Palazzo wrote:
> On Tue, Dec 5, 2023 at 2:54 AM Jeff Law wrote:
>> Distro build procedures are not something the GCC project generally gets
>> involved with.
>
> I see, but to me, this do not look like a distro build procedure,
> because you can use
> with any kind of
Hi!
As discussed in the PR, for the middle (on x86-64 65..128 bit) _BitInt
types like
_1 = x_4(D) * 5;
where _1 and x_4(D) have _BitInt(128) type and x is PARM_DECL, the bitint
lowering pass wants to replace this with
_13 = (int128_t) x_4(D);
_12 = _13 * 5;
_1 = (_BitInt(128)) _12;
where _
Hi Richard,
It looks like this patch result in one ICE for RISC-V backend for case
tree-ssa.exp=ssa-sink-16.c, could you please help to double check about it?
Any more information required please feel free to let me know. Thanks.
compiler error: Segmentation fault
0x1903067 crash_signal
On Mon, 4 Dec 2023, Siddhesh Poyarekar wrote:
> On 2023-12-04 13:48, Martin Uecker wrote:
> > > I empathize with Jakub's stated use case though of keeping the C
> > > frontend support for testing purposes, but that could easily be done
> > > behind a flag, or by putting nested C func deprecation b
On Mon, Dec 04, 2023 at 04:49:29PM -0500, Jason Merrill wrote:
> On 12/4/23 15:23, Marek Polacek wrote:
> > +/* FN is not a consteval function, but may become one. Remember to
> > + escalate it after all pending templates have been instantiated. */
> > +
> > +void
> > +maybe_store_immediate_esc
This patch fixes ICE exposed on full coverage testing:
=== g++: Unexpected fails for
rv64gc_zve32f_zvfh_zfh lp64d medlow --param=riscv-autovec-lmul=dynamic ===
FAIL: g++.dg/pr106219.C -std=gnu++14 (internal compiler error: in require, at
machmode.h:313)
FAIL: g++
Am Montag, dem 04.12.2023 um 21:33 + schrieb Joseph Myers:
> On Mon, 4 Dec 2023, Siddhesh Poyarekar wrote:
>
> > On 2023-12-04 13:48, Martin Uecker wrote:
> > > > I empathize with Jakub's stated use case though of keeping the C
> > > > frontend support for testing purposes, but that could easi
both patches are landed, newlib trunk should be able to build with gcc
trunk now.
On Mon, Dec 4, 2023 at 3:45 PM Kito Cheng wrote:
>
> RISC-V newlib patch send, one for libgloss and another one for libm,
> the libm issue is because we don't have right long double support,
> however newlib has sup
>Distro build procedures are not something the GCC project generally gets
involved with.
I see, but to me, this do not look like a distro build procedure,
because you can use
with any kind of system (OSX/UNIX) by using nix.
I disagree with you just because my patch is not building a package
but i
Manos Anagnostakis writes:
> Στις Δευ 4 Δεκ 2023, 21:22 ο χρήστης Richard Sandiford <
> richard.sandif...@arm.com> έγραψε:
>
>> Manos Anagnostakis writes:
>> > This is an RTL pass that detects store forwarding from stores to larger
>> loads (load pairs).
>> >
>> > This optimization is SPEC2017-dr
Wilco Dijkstra writes:
> Hi Richard,
>
>>> Enable lock-free 128-bit atomics on AArch64. This is backwards compatible
>>> with
>>> existing binaries, gives better performance than locking atomics and is what
>>> most users expect.
>>
>> Please add a justification for why it's backwards compatible
On 2023-12-04 13:51, Jakub Jelinek wrote:
Why? The syntax doesn't seem to be something unexpected, and as C doesn't
have lambdas, one can use the nested functions instead.
The only problem is if you need to pass function pointers somewhere else
(and target doesn't have function descriptors or so
> -Original Message-
> From: Jakub Jelinek
> Sent: Tuesday, December 5, 2023 3:01 PM
> To: Uros Bizjak ; Liu, Hongtao
> Cc: gcc-patches@gcc.gnu.org
> Subject: [PATCH] i386: Improve code generation for vector __builtin_signbit
> (x.x[i]) ? -1 : 0 [PR112816]
>
> Hi!
>
> On the testcase
LoongArch V1.1 adds support for approximate instructions, which are utilized
along with additional
Newton-Raphson steps implement single precision floating-point division, square
root and reciprocal
square root operations for better throughput.
The patches are modifications made based on the pat
在 2023/12/2 下午9:41, Xi Ruoyao 写道:
On Sat, 2023-12-02 at 20:44 +0800, chenglulu wrote:
@@ -657,12 +658,18 @@ abi_str (struct loongarch_abi abi)
strlen (loongarch_abi_base_strings[abi.base]));
else
{
+ /* This situation has not yet occurred, so in order to
On 2023-12-04 13:48, Martin Uecker wrote:
I empathize with Jakub's stated use case though of keeping the C
frontend support for testing purposes, but that could easily be done
behind a flag, or by putting nested C func deprecation behind a flag.
I am relatively sure C will get some form of nest
On Mon, 4 Dec 2023, Richard Biener wrote:
> The following fixes the intermediate conversions inserted by
> convert_to_integer when facing address-spaces and converts
> to their effective [u]intptr_t when they are registered_builtin_types
> by considering those also from c_common_type_for_size and
On Mon, Dec 04, 2023 at 05:30:45PM +, Richard Sandiford wrote:
> > I don't think it's worth adding the note problem to shrink-wrapping
> > just for the regcprop code. If we're prepared to take that compile-time
> > hit, we might as well run a proper (fast) DCE.
>
> Here's a patch that tries t
Using -mrecip generates a sequence of instructions to replace divf, sqrtf and
rsqrtf. The number
of generated instructions is close to or exceeds the maximum issue instructions
per cycle of the
LoongArch, so vectorized loop unrolling is not performed on them.
gcc/ChangeLog:
* config/loo
When both the -mrecip and -mfrecipe options are enabled, use approximate
reciprocal
instructions and approximate reciprocal square root instructions with additional
Newton-Raphson steps to implement single precision floating-point division,
square
root and reciprocal square root operations, for a
Redefine pattern for [x]vfrecip instructions use rtx code instead of unspec,
and enable
[x]vfrecip instructions to be generated during auto-vectorization.
gcc/ChangeLog:
* config/loongarch/lasx.md (lasx_xvfrecip_): Renamed to ..
(recip3): .. this.
* config/loongarch/loong
This patch adds define_insn/builtins/intrinsics for these instructions, and add
option
-mfrecipe to control instruction generation.
gcc/ChangeLog:
* config/loongarch/genopts/isa-evolution.in (fecipe): Add.
* config/loongarch/larchintrin.h (__frecipe_s): New intrinsic.
(__
Rename lasx_xvfrsqrt*/lsx_vfrsqrt* to rsqrt2 to align with standard
pattern name. Define function use_rsqrt_p to decide when to use rsqrt optab.
gcc/ChangeLog:
* config/loongarch/lasx.md (lasx_xvfrsqrt_): Renamed to ..
(rsqrt2): .. this.
* config/loongarch/loongarch-builti
This implements TLS Descriptors (TLSDESC) as specified in [1].
The 4-instruction sequence is implemented as a single RTX insn for
simplicity, but this can be revisited later if instruction scheduling or
more flexible RA is desired.
The default remains to be the traditional TLS model, but can be c
Hi!
On the testcase I've recently fixed I've noticed bad code generation,
we emit
pxor%xmm1, %xmm1
psrld $31, %xmm0
pcmpeqd %xmm1, %xmm0
pcmpeqd %xmm1, %xmm0
or
vpxor %xmm1, %xmm1, %xmm1
vpsrld $31, %xmm0, %xmm0
vpcmpeqd%xmm1
On 12/4/23 15:23, Marek Polacek wrote:
+/* FN is not a consteval function, but may become one. Remember to
+ escalate it after all pending templates have been instantiated. */
+
+void
+maybe_store_immediate_escalating_fn (tree fn)
+{
+ if (unchecked_immediate_escalating_function_p (fn))
+
However, I understand your point.
Cheers,
Vincent.
On Tue, Dec 5, 2023 at 3:01 AM Vincenzo Palazzo
wrote:
>
> >Distro build procedures are not something the GCC project generally gets
> involved with.
>
> I see, but to me, this do not look like a distro build procedure,
> because you can use
Dear all,
the attached patch picks up an observation by Tobias that we did
not specify the RESTRICT qualifier for optional arguments even
if that was allowed. In principle this might have prevented
better optimization.
While looking more closely, I found and fixed an issue with CLASS
dummy argum
On Monday, December 4th, 2023 at 9:35 PM, waffl3x
wrote:
>
>
> >> @@ -15402,6 +15450,8 @@ tsubst_decl (tree t, tree args, tsubst_flags_t
> >> complain,
>
> > > gcc_checking_assert (TYPE_MAIN_VARIANT (TREE_TYPE (ve))
> > > == TYPE_MAIN_VARIANT (type));
> > > SET_DECL_VALUE_EXPR (r, ve)
Hi!
When committing the #pragma GCC unroll patch, I found I forgot one spot
for diagnosting the invalid unrolls - if #pragma GCC unroll argument is
dependent and the pragma is before a range for loop, the unroll tree (now,
before one converted form ushort) is saved into RANGE_FOR_UNROLL and
tsubst
From: Kong Lingling
gcc/ChangeLog:
* config/i386/i386-expand.cc (ix86_fixup_binary_operands_no_copy):
Add use_ndd parameter and parse it.
* config/i386/i386-protos.h (ix86_fixup_binary_operands_no_copy):
Change define.
* config/i386/i386.md (sub3): Add new
gcc/ChangeLog:
* config/i386/i386.md (*movcc_noc): Extend with new constraints
to support NDD.
(*movsicc_noc_zext): Likewise.
(*movsicc_noc_zext_1): Likewise.
(*movqicc_noc): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/i386/apx-ndd-cmov.c: New
NDD uses evex prefix, so when segment prefix is also applied, the instruction
could excceed its 15byte limit, especially adding immediates. This could happen
when "e" constraint accepts any UNSPEC_TPOFF/UNSPEC_NTPOFF constant and it will
add the offset to segment register, which will be encoded usi
gcc/ChangeLog:
* doc/extend.texi:Add modifiers to the vector of asm in the doc.
* doc/md.texi:Refine the description of the modifier 'f' in the doc.
---
gcc/doc/extend.texi | 47 +
gcc/doc/md.texi | 2 +-
2 files changed, 48 inserti
From: Xi Ruoyao
We'll use HOST_WIDE_INT in LoongArch static properties in following patches.
To keep the same readability as C99 designated initializers, create a
std::array like data structure with position setter function, and add
field setter functions for structs used in loongarch-def.cc.
R
From: Kong Lingling
gcc/ChangeLog:
* config/i386/i386.md: (addsi_1_zext): Add new alternatives for
NDD and adjust output templates.
(*add_2): Likewise.
(*addsi_2_zext): Likewise.
(*add_3): Likewise.
(*addsi_3_zext): Likewise.
(*adddi_4): Li
The instructions defined in LoongArch Reference Manual v1.1 are not the
instruction
set v1.1 version. The CPU defined later may only support some instructions in
LoongArch Reference Manual v1.1. Therefore, the macro ISA_BASE_LA64V110 and
related definitions are removed here.
gcc/ChangeLog:
1. Rebase Xi Ruoyao's patch a to the latest commit.
https://gcc.gnu.org/pipermail/gcc-patches/2023-November/636798.html
2. remove the #if
!defined(IN_LIBGCC2) && !defined(IN_TARGET_LIBS) && !defined(IN_RTS)
guards in loongarch-def.h and loongarch-opts.h as they'll be unneeded.
3. Described in Loo
Under APX NDD, previous TImode allocation will have issue that it was
originally allocated using continuous pair, like rax:rdi, rdi:rdx.
This will cause issue for all TImode NDD patterns. For NDD we will not
assume the arithmetic operations like add have dependency between dest
and src1, then writ
From: Kong Lingling
gcc/ChangeLog:
* config/i386/i386-expand.cc (ix86_expand_unary_operator): Add use_ndd
parameter and adjust for NDD.
* config/i386/i386-protos.h: Add use_ndd parameter for
ix86_unary_operator_ok and ix86_expand_unary_operator.
* config/i
On Tue, Dec 5, 2023 at 10:32 AM Hongyu Wang wrote:
>
> Hi,
>
> APX NDD patches have been posted at
> https://gcc.gnu.org/pipermail/gcc-patches/2023-November/636604.html
>
> Thanks to Hongtao's review, the V2 patch adds support of zext sematic with
> memory input as NDD by default clear upper bits
The process of creating BTF_KIND_DATASEC records involves iterating
through variable declarations, determining which section they will be
placed in, and creating an entry in the appropriate DATASEC record
accordingly.
For variables without e.g. an explicit __attribute__((section)), we use
categori
Hi,
APX NDD patches have been posted at
https://gcc.gnu.org/pipermail/gcc-patches/2023-November/636604.html
Thanks to Hongtao's review, the V2 patch adds support of zext sematic with
memory input as NDD by default clear upper bits of dest for any operand size.
Also we support TImode shift with n
Manos Anagnostakis writes:
> This is an RTL pass that detects store forwarding from stores to larger loads
> (load pairs).
>
> This optimization is SPEC2017-driven and was found to be beneficial for some
> benchmarks,
> through testing on ampere1/ampere1a machines.
>
> For example, it can transf
From: Kong Lingling
For *one_cmplsi2_2_zext, it will be splitted to xor, so its NDD form will be
added together with xor NDD support.
gcc/ChangeLog:
* config/i386/i386.md (one_cmpl2): Add new constraints for NDD
and adjust output template.
(*one_cmpl2_1): Likewise.
On Monday, December 4th, 2023 at 9:39 PM, waffl3x
wrote:
> On Monday, December 4th, 2023 at 9:35 PM, waffl3x waff...@protonmail.com
> wrote:
>
>
>
> > > > @@ -15402,6 +15450,8 @@ tsubst_decl (tree t, tree args, tsubst_flags_t
> > > > complain,
> >
> > > > gcc_checking_assert (TYPE_MAIN_VARIANT
The recently-installed patch for interprocedural value-range propagation
enabled some folding that was not expected by the strub-const testcases,
causing them to fail.
I'm making the following adjustments to them to restore the behavior
they tested for, and to make them more future-proof to future
On Mon, Dec 04, 2023 at 01:27:32PM -0500, Siddhesh Poyarekar wrote:
> [Branching this into a separate conversation to avoid derailing the patch,
> which isn't directly related]
>
> On 2023-12-04 12:21, Martin Uecker wrote:
> > I do not really agree with that. Nested functions can substantially
>
Am Montag, dem 04.12.2023 um 13:27 -0500 schrieb Siddhesh Poyarekar:
> [Branching this into a separate conversation to avoid derailing the
> patch, which isn't directly related]
>
> On 2023-12-04 12:21, Martin Uecker wrote:
> > I do not really agree with that. Nested functions can substantially
> "Arsen" == Arsen Arsenović writes:
Arsen> Thanks. I'll wait for the Binutils and GDB maintainers to weigh in
Arsen> before pushing (plus, I can't push there).
Seems fine to me. Thank you.
Tom
[Branching this into a separate conversation to avoid derailing the
patch, which isn't directly related]
On 2023-12-04 12:21, Martin Uecker wrote:
I do not really agree with that. Nested functions can substantially
improve code quality and in C can avoid type unsafe use of
void* pointers in ca
Hi Richard,
>> Enable lock-free 128-bit atomics on AArch64. This is backwards compatible
>> with
>> existing binaries, gives better performance than locking atomics and is what
>> most users expect.
>
> Please add a justification for why it's backwards compatible, rather
> than just stating that
This is an RTL pass that detects store forwarding from stores to larger loads
(load pairs).
This optimization is SPEC2017-driven and was found to be beneficial for some
benchmarks,
through testing on ampere1/ampere1a machines.
For example, it can transform cases like
str d5, [sp, #320]
fmul d
Richard Biener writes:
> OK.
Thanks. I'll wait for the Binutils and GDB maintainers to weigh in
before pushing (plus, I can't push there).
Have a lovely day!
--
Arsen Arsenović
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Richard Sandiford writes:
> Jakub Jelinek writes:
>> On Sat, Dec 02, 2023 at 11:04:04AM +, Richard Sandiford wrote:
>>> I still maintain that so much stuff relies on the lack of false-positive
>>> REG_UNUSED notes that (whatever the intention might have been) we need
>>> to prevent the false
Am Montag, dem 04.12.2023 um 11:46 -0500 schrieb Siddhesh Poyarekar:
> On 2023-12-04 11:39, Andreas Schwab wrote:
> > On Dez 04 2023, Siddhesh Poyarekar wrote:
> >
> > > For hardened code in C, I think we really should look to step away from
> > > nested functions instead of adding ways to continu
On Wed, 8 Nov 2023, Kito Cheng wrote:
> OK, then LGTM, thanks for the explanation :)
Please don't top-post on a GCC mailing list (and preferably in off-list
replies to such mailing list messages unless it's been agreed to somehow
with the participants), as it makes it difficult to make context
The tester recently started failing va-arg-22.c on microblaze-linux:
gcc.c-torture/execute/va-arg-22.c -O0 (test for excess errors)
It was failing with an undefined reference to "r7" at link time. This
was ultimately tracked down to a HImode load using (reg+reg) addressing
mode, but which
Szabolcs Nagy writes:
> gcc/testsuite/ChangeLog:
>
> * gcc.target/aarch64/eh_return-3.c: Fix when retaa is available.
OK, thanks.
Richard
> ---
> gcc/testsuite/gcc.target/aarch64/eh_return-3.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/e
Rainer Orth writes:
> The recent warning changes broke gm2 bootstrap on Solaris:
>
> /vol/gcc/src/hg/master/local/gcc/m2/mc/mc.flex: In function 'handleFile':
> /vol/gcc/src/hg/master/local/gcc/m2/mc/mc.flex:297:21: error: implicit
> declaration of function 'alloca' [-Wimplicit-function-declarat
Rainer Orth writes:
> The recent warning patches broke Solaris bootstrap:
>
> /vol/gcc/src/hg/master/local/libiberty/pex-unix.c:326:3: error:
> initialization of 'pid_t (*)(struct pex_obj *, pid_t, int *, struct pex_time
> *, int, const char **, int *)' {aka 'long int (*)(struct pex_obj *, lon
On 2023-12-04 11:39, Andreas Schwab wrote:
On Dez 04 2023, Siddhesh Poyarekar wrote:
For hardened code in C, I think we really should look to step away from
nested functions instead of adding ways to continue supporting it. There's
probably a larger conversation to be had about the utility of n
On Mon, Dec 04, 2023 at 05:39:04PM +0100, Andreas Schwab wrote:
> On Dez 04 2023, Siddhesh Poyarekar wrote:
>
> > For hardened code in C, I think we really should look to step away from
> > nested functions instead of adding ways to continue supporting it. There's
> > probably a larger conversatio
Hello!
Thank you, as always, for the great work that you do on libstdc++. The
inout_ptr implementation properly handles the issue raised in LWG 3897
but it seems like having an explicit test might be a good idea.
I hope that this helps!
Will
-- >8 --
Add a test to verify that the implementation
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