On Mon, Oct 17, 2022 at 4:47 PM Thomas Schwinge wrote:
>
> Hi!
>
> On 2022-10-17T15:58:47+0200, Aldy Hernandez wrote:
> > On Mon, Oct 17, 2022 at 9:44 AM Thomas Schwinge
> > wrote:
> >> On 2022-10-11T10:31:37+0200, Aldy Hernandez via Gcc-patches
> >> wrote:
> >> > When solving 0 = _15 & 1, we
On Mon, Oct 17, 2022 at 7:57 PM Takayuki 'January June' Suwa
wrote:
> On 2022/10/16 14:03, Max Filippov wrote:
> > There's also the following runtime failures, but only on call0
> > configuration:
> >
> > +FAIL: gcc.c-torture/execute/20010122-1.c -O1 execution test
> > +FAIL: gcc.c-torture/exe
On Tue, 2022-09-27 at 02:23 +0200, Ilya Leoshkevich wrote:
> Hi,
>
> This is a resend of v4 with slightly adjusted commit messages:
>
> v1: https://gcc.gnu.org/pipermail/gcc-patches/2019-July/525016.html
> v2: https://gcc.gnu.org/pipermail/gcc-patches/2019-July/525069.html
> v3: https://gcc.gnu.o
When a partial equivalency record is merged, the existing members are
updated. The resulting PE size for each member should be the minimum of
what it was, and the size of the object it is now based on. The code
was simply setting it to the new size, which sometimes overwrote the
correct resul
On 9/28/22 12:59, Ulrich Drepper via Gcc-patches wrote:
Ping. Anyone having problems with this? And the governance of the file?
Hmm, for some reason this didn't show up on my C++ patches filter.
Please do CC me when pinging C++ patches.
On Mon, Sep 12, 2022 at 1:51 PM Ulrich Drepper wrot
On Wed, 12 Oct 2022, Jørgen Kvalsvik via Gcc-patches wrote:
> This patch adds support in gcc+gcov for modified condition/decision
> coverage (MC/DC) with the -fprofile-conditions flag.
I'd love improvements in this area.
But this is a serious concern:
> gcov --conditions:
>
> 3: 17:vo
This patch actually fixes the bogus RTL seen in PR101697.
Basically we continue to use the insn condition to catch most of the
problem cases related to autoinc addressing modes. This patch adds
constraints which can guide reload (and hopefully LRA) away from doing
blind replacements during r
Continuing the work to add constraints to avoid invalid RTL with
autoinc addressing modes. Specifically this patch adds the memory
constraints similar to the pdp11.
Pushed to the trunk,
Jeff
commit 19859bd72119708c85cc6976b3547738be6f5b1c
Author: Jeff Law
Date: Mon Oct 17 19:42:27 2022 -
I was looking at H8 assembly code recently and noticed we had
unnecessary extensions. As it turns out we never enabled redundant
extension elimination on the H8. This patch fixes that oversight (and
was the trigger for the failure fixed my the prior patch).
Regression tested along with a
While testing a minor optimization on the H8 my builds failed due to
failure to split a zero-extended memory load. That particular pattern
is a bit special on the H8 in that it's split at assembly time primarily
to get the length computations correct. Arguably that alternative
should go awa
On 10/17/22 07:28, Martin Liška wrote:
Hello.
Based on the very positive feedback I was given at the Cauldron Sphinx
Documentation BoF,
I'm planning migrating the documentation on 9th November. There are still some
minor comments
from Sandra when it comes to the PDF output, but we can address
On Mon, Oct 17, 2022 at 09:33:02PM +, Joseph Myers wrote:
> > > And I/O etc. support is missing, not sure I'm able to handle that and if
> > > it
> > > is e.g. possible to keep that support out of libstdc++.so.6, because what
> > > extended floating point types one has on a particular arch cou
On Mon, 17 Oct 2022 at 22:33, Joseph Myers wrote:
>
> On Mon, 17 Oct 2022, Jonathan Wakely via Gcc-patches wrote:
>
> > > And I/O etc. support is missing, not sure I'm able to handle that and if
> > > it
> > > is e.g. possible to keep that support out of libstdc++.so.6, because what
> > > extende
On Mon, 17 Oct 2022, Jonathan Wakely via Gcc-patches wrote:
> > And I/O etc. support is missing, not sure I'm able to handle that and if it
> > is e.g. possible to keep that support out of libstdc++.so.6, because what
> > extended floating point types one has on a particular arch could change over
Dear all,
I've pushed a very obvious fix for a NULL pointer dereference
on behalf of Steve after regtesting on x86_64-pc-linux-gnu as
https://gcc.gnu.org/g:84807af0ca6dfdb81abb8e925ce32acbcab29868
Thanks,
Harald
Tested on x86_64-pc-linux-gnu, does this look OK for trunk?
libstdc++-v3/ChangeLog:
* include/std/ranges (stride_view): Define.
(stride_view::_Iterator): Define.
(views::__detail::__can_stride_view): Define.
(views::_Stride, views::stride): Define.
* testsu
On Thu, Oct 13, 2022 at 8:32 AM Andrew MacLeod via Gcc-patches
wrote:
>
> Rangers on entry cache propagation already evaluates equivalences when
> calculating values. This patch also allows it to work with partial
> equivalences, and if the bit sizes are compatible, make use of those
> ranges as w
The problem here is that we're exporting a range for an SSA range that
happens on the other side of a __builtin_unreachable, but the SSA does
not post-dominate the definition point. This is causing ivcanon to
unroll things incorrectly.
This was a snafu when converting the code from evrp.
On Mon, Sep 19, 2022 at 11:13:20AM -0500, will schmidt wrote:
> The _ARCH_PWR8 define is conditional on TARGET_DIRECT_MOVE,
> and can be disabled by dependent options when it should not be.
> This manifests in the issue seen in PR101865 where -mno-vsx
> mistakenly disables _ARCH_PWR8.
> This cha
Hi,
This splits up the targetdm sources so that each file only handles one
target platform.
Having all logic kept in the headers means that they could become out of
sync when a new target is added (loongarch*-*-linux*) or accidentally
broken if some headers in tm_file are omitted or changed about
The assume function can have many arguments (one is created for each
automatic var referenced or set by the condition), so it would be nice to
track all of them rather than just hardcoding the first. And, the argument
doesn't necessarily have to be a scalar, so perhaps later on we could derive
Hi,
thanks for the review.
On Fri, Oct 14 2022, Jan Hubicka wrote:
>>
[...]
>>
>> gcc/testsuite/ChangeLog:
>>
>> 2022-08-15 Martin Jambor
>>
>> * gcc.dg/ipa/ipcp-agg-11.c: Adjust dumps.
>> * gcc.dg/ipa/ipcp-agg-8.c: Likewise.
>> ---
>> gcc/ipa-cp.cc | 1
Hi Mikael,
Am 16.10.22 um 23:17 schrieb Mikael Morin:
Le 15/10/2022 à 22:15, Harald Anlauf via Fortran a écrit :
Dear all,
here is an updated version of the patch that includes suggestions
and comments by Mikael in PR93483.
Basic new features are:
- a new enum value ARITH_NOT_REDUCED to keep
On Mon, 2022-10-17 at 10:32 -0500, Segher Boessenkool wrote:
> Hi!
>
> Everything Ke Wen said. Some more commments / hints:
Thanks for the reviews. :-)
I'll rework things and repost 'soon'.
Thanks
-WIll
It looks like the constexpr commit r13-3313-g378a0f1840e694
caused some modules regressions:
FAIL: g++.dg/modules/xtreme-header-4_b.C -std=c++2b (test for excess errors)
FAIL: g++.dg/modules/xtreme-header_b.C -std=c++2b (test for excess errors)
Like PR105297, the problem seems to be the loca
Hi!
On Mon, Oct 17, 2022 at 02:07:00PM +0100, Jonathan Wakely wrote:
> Yes, that's now https://cplusplus.github.io/LWG/issue3790
> The current proposed resolution is to just restore the C++20 functions
> and not provide anything for the new types.
Ok.
> > If you want to have done in a different
Hi!
On Mon, Oct 17, 2022 at 06:55:40AM +, Richard Biener wrote:
> > That is what I wrote in the patch description as alternative:
> > "with the condition wrapped into a GIMPLE_BIND (I admit the above isn't
> > extra clean but it is just something to hold it from gimplifier until
> > gimple low
Hi!
Everything Ke Wen said. Some more commments / hints:
On Mon, Sep 19, 2022 at 11:05:17AM -0500, will schmidt wrote:
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/predefine_p7-novsx.c
> @@ -0,0 +1,9 @@
> +/* { dg-do preprocess } */
> +/* Test whether the ARCH_PWR7 and ARCH_PWR8 defi
On 14/10/2022 09:34, Haochen Jiang via Gcc-patches wrote:
gcc/ChangeLog:
* builtins.cc (expand_builtin_prefetch): Handle the fourth parameter in
expand function.
* config/aarch64/aarch64-sve.md: Add default parameter value.
* config/aarch64/aarch64.md (prefetch
On 17 October 2022 15:29:33 CEST, Christophe Lyon via Gcc-patches
wrote:
>Hi Srinath,
>
>
>On 10/10/22 10:20, Srinath Parvathaneni via Gcc-patches wrote:
>> Hi,
>>
>> This patch adds cde feature (optional) support for Cortex-M55 CPU, please
>> refer
>> [1] for more details. To use this feature
Yes, I received that one. The root cause is the -gstatement-frontiers issue
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100733 . I submitted a workaround
patch for that (
https://gcc.gnu.org/pipermail/gcc-patches/2022-October/603673.html ) but it
hasn't been approved yet. Another workaround is
Yes, -gstatement-frontiers is the root cause here but the new approach to
discriminators is especially prone to this. I added the workaround to pr85213.c
in my original discriminator patch but now two more -fcompare-debug bugs were
opened (PR107231 and PR107169). I suspect we'll keep getting mor
Hi!
On 2022-10-17T15:58:47+0200, Aldy Hernandez wrote:
> On Mon, Oct 17, 2022 at 9:44 AM Thomas Schwinge
> wrote:
>> On 2022-10-11T10:31:37+0200, Aldy Hernandez via Gcc-patches
>> wrote:
>> > When solving 0 = _15 & 1, we calculate _15 as:
>> >
>> > [irange] int [-INF, -2][0, +INF] NONZE
Recently I tried to set a function's target attribute conditionally
based on template parameters, eg.:
template
[[gnu::target (enable_sse ? "sse" : "")]]
void func () { /* ... */ }
I then discovered that this is currently not possible. This small patch
resolves that.
A possible alte
[Public]
Hi,
> BTW: Perhaps znver1.md is not the right filename anymore, since it hosts all
> four Zen schedulers.
I have renamed the file to znver.md in this revision, PFA.
Thank you for the review, we will push it for trunk if we don't get any further
comments.
Thanks and Regards,
Tejas
0
Ping.
On 2022/9/21 3:45 PM, Chung-Lin Tang via Gcc-patches wrote:
> Hi Tom,
> I had a patch submitted earlier, where I reported that the current way of
> implementing
> barriers in libgomp on nvptx created a quite significant performance drop on
> some SPEChpc2021
> benchmarks:
> https://gcc.gnu
Hi Martin,
Thank you very much for porting the documentation to Sphinx, it is
very convenient to use, especially the menu on the left and the
search bar.
However, I also regularly browse and search the documentation through
info, especially when I want to use regexps to search or need to
include
On Mon, Oct 17, 2022 at 9:44 AM Thomas Schwinge wrote:
>
> Hi!
>
> On 2022-10-11T10:31:37+0200, Aldy Hernandez via Gcc-patches
> wrote:
> > When solving 0 = _15 & 1, we calculate _15 as:
> >
> > [irange] int [-INF, -2][0, +INF] NONZERO 0xfffe
> >
> > The known value of _15 is [0, 1] NO
PR tree-optimization/105820
gcc/testsuite/ChangeLog:
* g++.dg/tree-ssa/pr105820.c: New test.
---
gcc/testsuite/g++.dg/tree-ssa/pr105820.c | 26
1 file changed, 26 insertions(+)
create mode 100644 gcc/testsuite/g++.dg/tree-ssa/pr105820.c
diff --git a/gcc
Hi Srinath,
On 10/10/22 10:20, Srinath Parvathaneni via Gcc-patches wrote:
Hi,
This patch adds cde feature (optional) support for Cortex-M55 CPU, please refer
[1] for more details. To use this feature we need to specify +cdecpN
(e.g. -mcpu=cortex-m55+cdecp), where N is the coprocessor number 0
Hello.
Based on the very positive feedback I was given at the Cauldron Sphinx
Documentation BoF,
I'm planning migrating the documentation on 9th November. There are still some
minor comments
from Sandra when it comes to the PDF output, but we can address that once the
conversion is done.
The r
PR tree-optimizatin/107286
gcc/ChangeLog:
* value-range.cc (range_tests_floats): Do not test for -Inf when
flag_finite_math_only.
---
gcc/value-range.cc | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/gcc/value-range.cc b/gcc/value-range.cc
3 tests from Aldy using the relations generated by GORI between operands
to set or clear NANs as appropriate on outgoing edges.
Pushed.
Andrew
From 7896a31d3003bad8b845881f59e570fbc3c78cfa Mon Sep 17 00:00:00 2001
From: Aldy Hernandez
Date: Mon, 10 Oct 2022 11:01:48 +0200
Subject: [PATCH 4/4]
When I first added relations to range_ops, I struggled with obfuscating
the API too much by adding all of the 3 possible relations. For
simplicity, it seemed like only one was ever relevant, so elected to add
one relation, and make it always the relation between the 2 known operands.
fold_ran
There is a path in which clear_nan() is called on an UNDEFINED range,
which is not allowed. This patch simply makes sure VARYING is set
before calling clear_nan().
In operator_not_equal, we should check if op1 == op1 AFTER the check for
a singleton.
operator_ordered was also cealring the NA
The oracle will not register nonsense/useless relations, (basically X op
X). Symbolically, x == x is implied, and x != x, x< x, etc are all
nonsense.
Now that we are using class value_relation in a couple of other places,
it shouldn't either.
Bootstrapped on x86_64-pc-linux-gnu with no r
* Richard Biener:
> On Mon, Oct 17, 2022 at 3:01 PM Florian Weimer via Gcc-patches
> wrote:
>>
>> "zR" and "zPLR" are the most common augmentations. Use a simple
>> SIMD-with-in-a-register technique to check for both augmentations,
>> and that the following variable-length integers have length 1
On Mon, Oct 17, 2022 at 3:01 PM Florian Weimer via Gcc-patches
wrote:
>
> "zR" and "zPLR" are the most common augmentations. Use a simple
> SIMD-with-in-a-register technique to check for both augmentations,
> and that the following variable-length integers have length 1, to
> get more quickly at
On Sun, 16 Oct 2022 at 11:23, Jakub Jelinek wrote:
>
> Hi!
>
> As the __bf16 support is now in at least on x86_64/i686, I've
> updated my patch to cover bfloat16_t as well and implemented almost
> everything for - the only thing missing I'm aware of is
> std::nextafter std::float16_t and std::bfl
On 10/13/22 19:16, David Malcolm wrote:
> On Thu, 2022-10-13 at 11:44 +0200, Gerald Pfeifer wrote:
>> Hi Martin,
>>
>> On Thu, 13 Oct 2022, Martin Liška wrote:
>>> I think we should add how Python scripts should be formatted. I
>>> noticed
>>> that while reading the Modula-2 patchset where it follo
"zR" and "zPLR" are the most common augmentations. Use a simple
SIMD-with-in-a-register technique to check for both augmentations,
and that the following variable-length integers have length 1, to
get more quickly at the encoding field.
libgcc/
* unwind-dw2-fde.c (get_cie_encoding_slow):
Hi Will,
Thanks for fixing this, some comments are inline as below.
on 2022/9/20 00:13, will schmidt wrote:
> [PATCH, rs6000] Split TARGET_POWER8 from TARGET_DIRECT_MOVE [PR101865]
>
> Hi,
> The _ARCH_PWR8 define is conditional on TARGET_DIRECT_MOVE,
> and can be disabled by dependent options
Hi Will,
Some comments are inline.
on 2022/9/20 00:05, will schmidt wrote:
> [PATCH, rs6000] Tests of ARCH_PWR8 and -mno-vsx option.
>
> Hi,
>
> This adds an assortment of tests to exercise the -mno-vsx option and
> confirm the impacts on the ARCH_PWR8 define.
>
> These are based on and inspir
Hi!
On 2022-10-11T12:02:03+0100, Andrew Stubbs wrote:
> --- a/gcc/config/gcn/gcn.cc
> +++ b/gcc/config/gcn/gcn.cc
> +/* Return a vector mode with N lanes of MODE. */
> +
> +static machine_mode
> +VnMODE (int n, machine_mode mode)
> +{
> + switch (mode)
> +{
> +case QImode:
Pushed to m
On Tue, 11 Oct 2022, juzhe.zh...@rivai.ai wrote:
> Hi, I apply this patch in RVV downstrean. Tested it with a lot of vector
> benchmark. It overal has a greate performance gain.
> Maybe the last thing to merge this patch is wait for Richard Sandiford test
> it in ARM SVE?
>
> By the way, would
Hi!
On 2015-11-03T02:29:41-0200, Alexandre Oliva wrote:
> Thanks, here's the patch as just installed.
> --- a/gcc/gimple-expr.c
> +++ b/gcc/gimple-expr.c
> +static void
> +mark_addressable_1 (tree x)
> +{
> + [...]
> +}
> +
> +/* Adaptor for mark_addressable_1 for use in hash_set traversal. *
Hi!
On 2022-09-12T14:02:16+0200, Tobias Burnus wrote:
> --- /dev/null
> +++ b/libgomp/testsuite/libgomp.c/reverse-offload-sm30.c
> @@ -0,0 +1,15 @@
> +/* { dg-do link { target { offload_target_nvptx } } } */
> +/* { dg-additional-options "-foffload-options=nvptx-none=-march=sm_30
> -foffload=-mp
Hi!
On 2022-10-17T06:11:01+, "Jiang, Haochen via Gcc-patches"
wrote:
> I just checkout to your commit and the test still got failed.
>
> It is reporting like this:
> xgcc: error:
> /export/users2/haochenj/src/gcc/master/./libgomp/testsuite/libgomp.oacc-c++/../libgomp.oacc-c-c++-common/kerne
On Mon, 10 Oct 2022 at 16:18, Prathamesh Kulkarni
wrote:
>
> On Fri, 30 Sept 2022 at 21:38, Richard Sandiford
> wrote:
> >
> > Richard Sandiford via Gcc-patches writes:
> > > Prathamesh Kulkarni writes:
> > >> Sorry to ask a silly question but in which case shall we select 2nd
> > >> vector ?
On 27/09/2022 08.54, Rasmus Villemoes wrote:
> On 12/09/2022 11.46, Rasmus Villemoes wrote:
>> On 29/08/2022 11.29, Rasmus Villemoes wrote:
>>> -ffile-prefix-map is supposed to be a superset of -fmacro-prefix-map
>>> and -fdebug-prefix-map. However, when building .S or .s files, gas is
>>> not call
> -Original Message-
> From: Richard Biener
> Sent: Monday, September 26, 2022 11:28 AM
> To: Tamar Christina
> Cc: gcc-patches@gcc.gnu.org; nd ; jeffreya...@gmail.com;
> ebotca...@adacore.com
> Subject: Re: [PATCH]middle-end fix floating out of constants in conditionals
>
> On Fri, 23 S
BFD ld (and the other linkers) only produce one encoding of these
values. It is not necessary to use the general
read_encoded_value_with_base decoding routine. This avoids the
data-dependent branches in its implementation.
libgcc/
* unwind-dw2-fde-dip.c (find_fde_tail): Special-case enc
Hi Iain,
on 2022/10/13 18:09, Iain Sandoe wrote:
>
>
>> On 12 Oct 2022, at 09:57, Iain Sandoe wrote:
>>> On 12 Oct 2022, at 09:12, Kewen.Lin wrote:
>>
>>> PR106680 shows that -m32 -mpowerpc64 is different from
>>> -mpowerpc64 -m32, this is determined by the way how we
>>> handle option powerpc
Yes, the mail service on script machine was down previously after expected
reboot
and it just recovered but still ran into some problems when sending previously
email.
That is why this is the only stuck mail got sent and sorry for the disturb.
> -Original Message-
> From: Hongtao Liu
>
This should be already fixed.
On Mon, Oct 17, 2022 at 4:34 PM haochen.jiang via Gcc-patches
wrote:
>
> On Linux/x86_64,
>
> 25413fdb2ac24933214123e24ba165026452a6f2 is the first bad commit
> commit 25413fdb2ac24933214123e24ba165026452a6f2
> Author: Andre Vieira
> Date: Tue Oct 11 10:49:27 2022
On Sat, 15 Oct 2022 at 21:26, Jonathan Wakely via Libstdc++
wrote:
>
> libstdc++-v3/ChangeLog:
>
> * include/bits/charconv.h (__to_chars_10_impl): Add constexpr
> for C++23. Remove 'static' from array.
> * include/std/charconv (__cpp_lib_constexpr_charconv): Define.
I mana
Richard Biener writes:
> On Tue, 11 Oct 2022, Richard Sandiford wrote:
>
>> Richard Biener writes:
>> > On Mon, 10 Oct 2022, Andrew Stubbs wrote:
>> >> On 10/10/2022 12:03, Richard Biener wrote:
>> >> > The following picks up the prototype by Ju-Zhe Zhong for vectorizing
>> >> > first order recur
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config.gcc: Add riscv-vector-builtins-bases.o and
riscv-vector-builtins-shapes.o
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_I_OPS): New macro.
(DEF_RVV_FUNCTION): Ditto.
(handle_pragma_vector): Add intrinsic framework.
On Linux/x86_64,
25413fdb2ac24933214123e24ba165026452a6f2 is the first bad commit
commit 25413fdb2ac24933214123e24ba165026452a6f2
Author: Andre Vieira
Date: Tue Oct 11 10:49:27 2022 +0100
vect: Teach vectorizer how to handle bitfield accesses
caused
FAIL: gcc.target/i386/pr101668.c scan-
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config.gcc: Add gt files since function_instance is GTY ((user)).
* config/riscv/riscv-builtins.cc (riscv_init_builtins): Add RVV
intrinsic framework.
(riscv_builtin_decl): Ditto.
(riscv_expand_builtin): Ditto.
* config
Committed :)
On Sat, Oct 15, 2022 at 7:03 AM wrote:
>
> From: Ju-Zhe Zhong
>
> Hi, this patch fixed my mistake in the previous commit patch.
> Since "mangle_builtin_type" is a global function will be called in riscv.cc.
> It's reasonable move it down and put them together stay with other global
Committed :)
On Mon, Oct 17, 2022 at 3:31 PM wrote:
>
> From: Ju-Zhe Zhong
>
> gcc/ChangeLog:
>
> * config/riscv/t-riscv: Change Tab into 2 space.
>
> ---
> gcc/config/riscv/t-riscv | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/config/riscv/t-riscv b/gcc/c
Hi!
On 2022-10-11T10:31:37+0200, Aldy Hernandez via Gcc-patches
wrote:
> When solving 0 = _15 & 1, we calculate _15 as:
>
> [irange] int [-INF, -2][0, +INF] NONZERO 0xfffe
>
> The known value of _15 is [0, 1] NONZERO 0x1 which is intersected with
> the above, yielding:
>
> [0, 1]
On 12.10.22 16:05, Tobias Burnus wrote:
This came up because the USM implementation with
-foffload-memory={unified,pinned}
as posted at
https://gcc.gnu.org/pipermail/gcc-patches/2022-July/597976.html
does not handle USM with static variables.
This shows up for the OG12 alias devel/omp/gcc-12 b
On 12.10.22 10:55, Tobias Burnus wrote:
On 11.10.22 13:12, Alexander Monakov wrote:
My understanding is such trickery should not be necessary with
the barrier-based approach, i.e. the sequence of PTX instructions
st % plain store
membar.sys
st.volatile
should be enough to guarante
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/t-riscv: Change Tab into 2 space.
---
gcc/config/riscv/t-riscv | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/riscv/t-riscv b/gcc/config/riscv/t-riscv
index 2f060437c23..15b9e7c01b1 100644
--- a/gcc/config
On Wed, Oct 5, 2022 at 5:33 AM H.J. Lu wrote:
>
> On Wed, Sep 21, 2022 at 1:42 PM H.J. Lu wrote:
> >
> > If shadow stack is enabled, when unwinding stack, we count how many stack
> > frames we pop to reach the landing pad and adjust shadow stack by the same
> > amount. When counting the stack fr
On Fri, Oct 14, 2022 at 4:18 PM Paul Iannetta via Gcc-patches
wrote:
>
> On Wed, Oct 12, 2022 at 01:18:19AM +0200, Paul Iannetta wrote:
> > On Mon, Oct 10, 2022 at 11:07:06PM +, Joseph Myers wrote:
> > > On Mon, 10 Oct 2022, Paul Iannetta via Gcc-patches wrote:
> > >
> > > > I have a patch to
On Mon, Oct 17, 2022 at 5:44 AM Hongtao Liu via Gcc-patches
wrote:
>
> On Mon, Oct 17, 2022 at 11:26 AM Liwei Xu via Gcc-patches
> wrote:
> >
> > gcc/testsuite/ChangeLog:
> >
> > * gcc.dg/tree-ssa/forwprop-19.c: Move scanning pass from forwprop1
> > to dse1, This fixs
> > the tes
On Sun, Oct 16, 2022 at 10:25 PM Eugene Rozenfeld via Gcc-patches
wrote:
>
> With -gstatement-frontiers we may end up with different IR
> coming from the front end with and without debug information turned on.
> See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100733 for details.
> That may result
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