On Fri, Sep 16, 2022 at 2:55 AM liuhongt via Gcc-patches
wrote:
>
> For ifloor/lfloor/iceil/lceil/irint/lrint/iround/lround when size of
> in_mode is not equal out_mode, vectorizer doesn't go to internal fn
> way,still left that part in the ix86_builtin_vectorized_function.
>
> Remove others built
On Fri, Sep 16, 2022 at 3:32 AM Jeff Law via Gcc-patches
wrote:
>
>
> On 9/15/22 19:06, liuhongt via Gcc-patches wrote:
> > There's peephole2 submit in 1990s which split cmp mem, 0 to load mem,
> > reg + test reg, reg. I don't know exact reason why gcc do this.
> >
> > For latest x86 processors, c
For Skylake based processor, decoder is 4-way.
For Sunny Cove and Willow Cove, decoder is 5-way.
For Golden cove, decoder is 6-way.
Bootstrapped and regtested on x86-64-pc-linux-gnu{-m32,}.
Ready to install.
gcc/ChangeLog:
* config/i386/x86-tune-sched.cc (ix86_issue_rate): Adjust for
Hello, gentle maintainer.
This is a message from the Translation Project robot.
A revised PO file for textual domain 'gcc' has been submitted
by the French team of translators. The file is available at:
https://translationproject.org/latest/gcc/fr.po
(This file, 'gcc-12.2.0.fr.po', has jus
Hi Richard,
Thanks again for your reviewing.
> Yes, use else if for the bitwise induction. Can you also make the new case
> conditional on 'def'
> (the compute_overall_effect_of_inner_loop) being chrec_dont_know? If that
> call produced something useful it will not be of either of the two speci
On 9/15/22 19:06, liuhongt via Gcc-patches wrote:
There's peephole2 submit in 1990s which split cmp mem, 0 to load mem,
reg + test reg, reg. I don't know exact reason why gcc do this.
For latest x86 processors, ciscization should help processor frontend
also codesize, for processor backend, th
On Fri, Sep 16, 2022 at 9:09 AM liuhongt via Gcc-patches
wrote:
>
> There's peephole2 submit in 1990s which split cmp mem, 0 to load mem,
> reg + test reg, reg. I don't know exact reason why gcc do this.
>
> For latest x86 processors, ciscization should help processor frontend
> also codesize, for
There's peephole2 submit in 1990s which split cmp mem, 0 to load mem,
reg + test reg, reg. I don't know exact reason why gcc do this.
For latest x86 processors, ciscization should help processor frontend
also codesize, for processor backend, they should be the same(has same
uops).
So the patch de
On Fri, Sep 16, 2022 at 8:55 AM liuhongt wrote:
>
> For ifloor/lfloor/iceil/lceil/irint/lrint/iround/lround when size of
> in_mode is not equal out_mode, vectorizer doesn't go to internal fn
> way,still left that part in the ix86_builtin_vectorized_function.
>
> Remove others builtins and add corr
For ifloor/lfloor/iceil/lceil/irint/lrint/iround/lround when size of
in_mode is not equal out_mode, vectorizer doesn't go to internal fn
way,still left that part in the ix86_builtin_vectorized_function.
Remove others builtins and add corresponding expanders.
Note the patch just refactor the codes,
Tested powerpc64le-linux, pushed to trunk.
-- >8 --
Previously included so that std::copy,
std::fill etc. could be used by . But that
includes it explicitly now, so that it can be compiled as a header unit.
There's no need to include it in , where its purpose isn't
obvious.
libstdc++-v3/Change
Hello-
https://gcc.gnu.org/pipermail/gcc-patches/2022-August/599397.html
May I please ping this patch? Thank you.
-Lewis
On Fri, Aug 5, 2022 at 12:14 PM Lewis Hyatt wrote:
>
>
> When libcpp reports diagnostics whose locus is a macro name (such as for
> -Wunused-macros), it uses the location in
Dear all,
we hit a NULL pointer dereference when trying to simplify PACK
when the MASK argument was present. The obvious and trivial
solution is to check for NULL pointer dereferences why looking
at the constructor for the ARRAY argument, which we already do
in the case the MASK is not present.
On Wed, 14 Sept 2022 at 23:28, Jonathan Wakely wrote:
>
> On Wed, 14 Sept 2022 at 23:25, Jonathan Wakely wrote:
> >
> > On Wed, 14 Sept 2022 at 23:05, Jonathan Wakely via Libstdc++
> > wrote:
> > > @@ -377,6 +401,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
> > > ~_Atomic_count()
> > > {
On Thu, Sep 15, 2022 at 9:06 AM Richard Biener
wrote:
>
> On Thu, Sep 15, 2022 at 7:41 AM Aldy Hernandez wrote:
> >
> > Hi Richard. Hi all.
> >
> > The attatched patch rewrites the NAN and sign handling, dropping both
> > tristates in favor of a pair of boolean flags for NANs, and nothing at
> >
Dear all,
the attached obvious patch fixes an ICE on a NULL pointer
dereference. We didn't properly check that the types of
expressions are character before referencing the length.
The issue was originally investigated by Steve, so I made
him co-author.
Regtested on x86_64-pc-linux-gnu and push
A couple of xtreme-header-* modules tests began ICEing in C++23 mode
ever since r13-2650-g5d84a4418aa962 introduced into the
dependently scoped friend declaration
friend /* typename */ _OuterIter::value_type;
ultimately because the streaming code assumes a TYPE_P friend must
be a class type, b
This patch permits accessing 'mutable' members of local objects during
constexpr evaluation (which other compilers seem to accept in C++14
mode, while we reject), while continuing to reject it for global objects
(as in the last line of cpp0x/constexpr-mutable1.C, which other
compilers also reject).
Here we're crashing during constraint matching for the instantiated
hidden friends due to two issues with dependent substitution into a
TEMPLATE_ID_EXPR naming a template from the current instantiation
(as performed from maybe_substitute_reqs_for for C<3> with T=T):
* tsubst_copy substitutes int
On Wed, 14 Sept 2022 at 15:19, Patrick Palka via Libstdc++
wrote:
>
> Tested on x86_64-pc-linux-gnu, does this look OK for trunk?
OK, thanks.
On Wed, 14 Sept 2022 at 18:26, François Dumont via Libstdc++
wrote:
>
> libstdc++: [_GLIBCXX_INLINE_VERSION] Fix test dg-prune-output
>
> libstdc++-v3/ChangeLog:
>
> *
> testsuite/20_util/is_complete_or_unbounded/memoization_neg.cc: Adapt
Please put the "Adapt" on the next
On Wed, 14 Sept 2022 at 18:22, François Dumont via Libstdc++
wrote:
>
> libstdc++: [_GLIBCXX_INLINE_VERSION] Cleanup
> gnu-versioned-namespace.ver
>
> Remove expressions for symbols in std::__detail::__8 namespace,
> they are obsolete since
> version namespace applies only at std::
Ping!
On 2022-09-07 15:21, Siddhesh Poyarekar wrote:
Ping!
On 2022-08-29 10:16, Siddhesh Poyarekar wrote:
Ping!
On 2022-08-15 15:23, Siddhesh Poyarekar wrote:
Use string length of input to strdup to determine the usable size of the
resulting object. Avoid doing the same for strndup since th
ChangeLog:
* MAINTAINERS (Write After Approval): Add myself.
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index e89eb343528..be146855ed8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -641,6 +641,7 @@ YunQiang Su
On Mon, 12 Sept 2022 at 19:57, Richard Sandiford
wrote:
>
> Prathamesh Kulkarni writes:
> > On Mon, 5 Sept 2022 at 15:51, Richard Sandiford
> > wrote:
> >>
> >> Sorry for the slow reply. I wrote a response a couple of weeks ago
> >> but I think it get lost in a machine outage.
> >>
> >> Pratham
PRE implicitely keeps virtual operands at the blocks incoming version
but the explicit updating point during PHI translation fails to trigger
when there are no PHIs at all in a block. Later lazy updating then
fails because of a too lose block check. A similar issues plagues
reference invalidation
> Yeah, rtx_costs (or preferably insn_cost, if that works) seem like the
> best way of addressing this. If the target says that register moves are
> cheaper than constant moves then it's a feature that CSE & co remove
> duplicate constants. The REG_EQUIV note is still useful in those cases
> beca
The expected scan dump output for this test will change after the
following patch is committed:
https://gcc.gnu.org/pipermail/gcc-patches/2022-September/601558.html
But for now, this patch reverts to the old expected pattern so the test
passes. I will apply as obvious.
2022-09-15 Julian Brown
Robin Dapp via Gcc-patches writes:
> Hi,
>
> I have been working on making better use of s390's vzero instruction.
> Currently we rather zero a vector register once and load it into other
> registers via vlr instead of emitting multiple vzeros.
>
> At IRA/reload point we e.g. have
>
> (insn 8 5 19
Small addition to clarify: (insn 8) from the example is of course
matched to a vzero. The "problem" begins when (reg 64) is later moved
into another register and the (const_vector) has been optimized to a
single definition e.g. by CSE, i.e. we have several
(insn yy (set (reg:V2DI xx) (reg:V2DI 6
From: zhongjuzhe
gcc/ChangeLog:
* config/riscv/riscv-modes.def (VECTOR_BOOL_MODE): Add RVV mask modes.
(ADJUST_NUNITS): Adjust nunits using riscv_vector_chunks.
(ADJUST_ALIGNMENT): Adjust alignment.
(ADJUST_BYTESIZE): Adjust bytesize using riscv_vector_chunks.
Hi,
I have been working on making better use of s390's vzero instruction.
Currently we rather zero a vector register once and load it into other
registers via vlr instead of emitting multiple vzeros.
At IRA/reload point we e.g. have
(insn 8 5 19 2 (set (reg/v:V2DI 64 [ zero ])
(const_vec
These testsuite hunks got left attached to the wrong patch in the series
I just posted. I will apply as obvious.
2022-09-15 Julian Brown
gcc/testsuite/
* c-c++-common/goacc/mdc-2.c: Update expected errors.
* g++.dg/goacc/mdc.C: Likewise.
---
gcc/testsuite/c-c++-common/goacc/md
Richard Biener via Gcc-patches writes:
> All frontends replicate this, so move it.
>
> Bootstrap and regtest running for all languages on
> x86_64-unknown-linux-gnu.
>
> OK if that succeeds?
LGTM FWIW.
Thanks,
Richard
> Thanks,
> Richard.
>
> gcc/
> * tree.cc (build_common_tree_nodes): I
From: zhongjuzhe
gcc/ChangeLog:
* config/riscv/riscv-modes.def (VECTOR_BOOL_MODE): Define RVV mask
modes.
(ADJUST_NUNITS): Adjust NUNITS using riscv_vector_chunks.
(ADJUST_ALIGNMENT): Adjust alignment.
(ADJUST_BYTESIZE): Adjust bytesize.
(RVV_MODES): New
Hi,
For a complicate 64bit constant, blow is one instruction-sequence to
build:
lis 9,0x800a
ori 9,9,0xabcd
sldi 9,9,32
oris 9,9,0xc167
ori 9,9,0xfa16
while we can also use below sequence to build:
lis 9,0xc167
lis 10,0x800a
ori 9,9,
From: zhongjuzhe
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Change "static void" to "void".
* config.gcc: Add riscv-selftests.o
* config/riscv/predicates.md: Allow const_poly_int.
* config/riscv/riscv-protos.h (riscv_reinit): New function.
(risc
Ping: https://gcc.gnu.org/pipermail/gcc-patches/2022-August/600475.html
BR,
Jeff(Jiufu)
Jiufu Guo writes:
> Hi,
>
> When checking eq/ne with a constant which has only 16bits, it can be
> optimized to check the rotated data. By this, the constant building
> is optimized.
>
> As the example i
On Thu, Sep 15, 2022 at 7:41 AM Aldy Hernandez wrote:
>
> Hi Richard. Hi all.
>
> The attatched patch rewrites the NAN and sign handling, dropping both
> tristates in favor of a pair of boolean flags for NANs, and nothing at
> all for signs. The signs are tracked in the range itself, so now it's
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