From: Xiong Hu Luo
This is a backport of r25, r257253 and r258137 of trunk to gcc-7-branch.
The patches were on trunk before GCC 8 forked already. Totally 5 files need
mannual resolve due to code changes for r25. r257253 and r258137 are
dependent testcases require vsx support need merge t
On Mon, Feb 18, 2019 at 04:04:15PM -1000, Jason Merrill wrote:
> > --- gcc/cp/constexpr.c.jj 2019-02-17 17:09:47.113351897 +0100
> > +++ gcc/cp/constexpr.c 2019-02-18 19:34:57.995136395 +0100
> > @@ -1269,6 +1301,49 @@ cxx_eval_builtin_function_call (const co
> > return t;
> >
On 2019-02-15 6:35 a.m., Andre Vieira (lists) wrote:
Hi Vlad,
On 13/02/2019 16:46, Vladimir Makarov wrote:
On 2019-02-13 5:54 a.m., Andre Vieira (lists) wrote:
PING.
Since Jeff is away can another maintainer have a look at this please?
I see the following patch
Yeah I uploaded the wro
On 07/02/19 23:39 -0500, Tom Honermann wrote:
On 2/7/19 4:54 AM, Jonathan Wakely wrote:
On 23/12/18 21:27 -0500, Tom Honermann wrote:
Attached is a revised patch that addresses changes in P0482R6.
Changes from the prior patch include:
- Updated the value of the __cpp_char8_t feature test macr
On 08/02/19 12:56 +, Jonathan Wakely wrote:
On 07/02/19 23:35 -0500, Tom Honermann wrote:
On 2/7/19 4:44 AM, Jonathan Wakely wrote:
On 23/12/18 21:27 -0500, Tom Honermann wrote:
Attached is a revised patch that addresses changes in P0482R6.
Changes from the prior patch include:
- Updated
On 18/02/19 21:22 +0100, Jakub Jelinek wrote:
On Mon, Feb 18, 2019 at 09:15:39PM +0100, Rainer Orth wrote:
2019-02-15 Rainer Orth
* g++.dg/torture/pr89303.C (bad_weak_ptr): Rename to
bad_weak_ptr_.
Ok, thanks.
If needed, guess we could rename much more (or rename the namesp
Please let me know what it will take to get the fix for these two
issues approved. I've answered the questions so I don't know what
else I'm expected to do here.
https://gcc.gnu.org/ml/gcc-patches/2019-02/msg00793.html
On 2/11/19 12:20 PM, Martin Sebor wrote:
This is a repost of a patch for
On 2/18/19 12:45 PM, Jakub Jelinek wrote:
Hi!
As mentioned in the PR, we've regressed on the trunk in diagnostics of some
invalid constexpr evaluations. The problem is that the constexpr evaluation
is effectively done on post-cp_fold_function bodies/arguments and cp_fold
optimizes away some imp
On 2/18/19 3:15 PM, Paolo Carlini wrote:
Hi,
On 19/02/19 00:52, Jason Merrill wrote:
On 2/18/19 12:14 PM, Paolo Carlini wrote:
Hi Jason,
On 18/02/19 19:28, Jason Merrill wrote:
On 2/18/19 5:31 AM, Paolo Carlini wrote:
Hi Jason,
On 18/02/19 10:20, Jason Merrill wrote:
On 2/17/19 6:58 AM, P
Hi,
On 19/02/19 00:52, Jason Merrill wrote:
On 2/18/19 12:14 PM, Paolo Carlini wrote:
Hi Jason,
On 18/02/19 19:28, Jason Merrill wrote:
On 2/18/19 5:31 AM, Paolo Carlini wrote:
Hi Jason,
On 18/02/19 10:20, Jason Merrill wrote:
On 2/17/19 6:58 AM, Paolo Carlini wrote:
Hi,
here, when we do
On 2/17/19 3:34 AM, Jakub Jelinek wrote:
On Sat, Feb 16, 2019 at 08:51:33AM -1000, Jason Merrill wrote:
The likely case is still that nothing has changed in between, so this patch
just quickly verifies if that is the case (by comparing
CONSTRUCTOR_ELT (ctor, 0) with the previously saved value of
On 2/18/19 1:02 PM, Jakub Jelinek wrote:
Hi!
On the following testcase, id_expr is false and TREE_CODE (*iter)
is USING_DECL (and the following one is FUNCTION_DECL).
Since the USING_DECL changes, this ICEs because
DECL_NONSTATIC_MEMBER_FUNCTION_P uses TREE_TYPE which can't be used here.
Previou
On 2/18/19 12:58 PM, Jakub Jelinek wrote:
Hi!
The if (TYPE_REF_IS_RVALUE (type)) code has been added recently,
but build_target_expr_with_type asserts that the expression doesn't have
void type. Fixed by using the old handling in that case (the expression is
not lvalue in that case and diagnost
On 2/18/19 12:50 PM, Jakub Jelinek wrote:
Hi!
On the following testcase we ICE because name is BIT_NOT_EXPR and
suggest_alternative_in_scoped_enum assumes it is called on IDENTIFIER_NODE
only.
Fixed thusly, bootstrapped/regtested on x86_64-linux and i686-linux, ok for
trunk?
OK.
There is an
On 2/18/19 12:14 PM, Paolo Carlini wrote:
Hi Jason,
On 18/02/19 19:28, Jason Merrill wrote:
On 2/18/19 5:31 AM, Paolo Carlini wrote:
Hi Jason,
On 18/02/19 10:20, Jason Merrill wrote:
On 2/17/19 6:58 AM, Paolo Carlini wrote:
Hi,
here, when we don't see an initializer we believe we are surel
On Sat, 2 Feb 2019 at 11:01, Johannes Pfau wrote:
>
> Adds a configure test for qsort_r and use the fallback code path if
> it's not available. Fixes d/88127. rt/qsort.d changes have been
> pushed upstream and reviewed there:
> https://github.com/dlang/druntime/pull/2480
> Bootstrapped & ran D te
On Sat, 16 Feb 2019, Jakub Jelinek wrote:
> Hi!
>
> Both the C and C++ standard guarantee that the argc argument to main is
> non-negative, the following patch sets (or adjusts) the corresponding
> SSA_NAME_RANGE_INFO. While main is just one, with IPA VRP it can also
> propagate etc. I had to c
On Tue, 29 Jan 2019 at 15:44, Rainer Orth wrote:
>
> Yet another trivial fix for a Solaris libphobos testsuite failure:
>
> FAIL: libphobos.shared/load.d -shared-libphobos -ldl (test for excess errors)
> Excess errors:
> /vol/gcc/src/hg/trunk/local/libphobos/testsuite/libphobos.shared/load.d:9:
>
On Mon, Feb 18, 2019 at 11:55:56PM +0100, Jakub Jelinek wrote:
> On Mon, Feb 18, 2019 at 04:47:57PM -0600, Segher Boessenkool wrote:
> > On Sat, Feb 16, 2019 at 08:12:34AM +0100, Jakub Jelinek wrote:
> > > Both the C and C++ standard guarantee that the argc argument to main is
> > > non-negative, t
Hi!
On the following testcase, id_expr is false and TREE_CODE (*iter)
is USING_DECL (and the following one is FUNCTION_DECL).
Since the USING_DECL changes, this ICEs because
DECL_NONSTATIC_MEMBER_FUNCTION_P uses TREE_TYPE which can't be used here.
Previously, I believe DECL_NONSTATIC_MEMBER_FUNCTI
Hi!
The if (TYPE_REF_IS_RVALUE (type)) code has been added recently,
but build_target_expr_with_type asserts that the expression doesn't have
void type. Fixed by using the old handling in that case (the expression is
not lvalue in that case and diagnostics is emitted if complain).
Bootstrapped/r
On Mon, Feb 18, 2019 at 04:47:57PM -0600, Segher Boessenkool wrote:
> On Sat, Feb 16, 2019 at 08:12:34AM +0100, Jakub Jelinek wrote:
> > Both the C and C++ standard guarantee that the argc argument to main is
> > non-negative, the following patch sets (or adjusts) the corresponding
> > SSA_NAME_RAN
Hi!
On the following testcase we ICE because name is BIT_NOT_EXPR and
suggest_alternative_in_scoped_enum assumes it is called on IDENTIFIER_NODE
only.
Fixed thusly, bootstrapped/regtested on x86_64-linux and i686-linux, ok for
trunk?
There is another issue, starting with 7.x we don't use sensibl
Hi Jakub,
On Sat, Feb 16, 2019 at 08:12:34AM +0100, Jakub Jelinek wrote:
> Both the C and C++ standard guarantee that the argc argument to main is
> non-negative, the following patch sets (or adjusts) the corresponding
> SSA_NAME_RANGE_INFO.
I think this should test for flag_hosted somehow? And
The issue in the PR is caused during simplification in the frontend
because it does not properly differentiate between expressions of
size 0 (e.g. arrays of length 0 or character strings of len=0)
and failure.
The attached patch tries to solve this problem by modifying the
helper functions gfc_ele
Hi!
As mentioned in the PR, we've regressed on the trunk in diagnostics of some
invalid constexpr evaluations. The problem is that the constexpr evaluation
is effectively done on post-cp_fold_function bodies/arguments and cp_fold
optimizes away some important trees for constexpr diagnostics, eith
On Tue, 29 Jan 2019 at 13:35, Rainer Orth wrote:
>
> With the set of libphobos Solaris patches just posted, it would become
> possible to enable libphobos on Solaris 11/x86 by default.
>
> This is what this patch does.
>
> * It uses a LIBPHOBOS_SUPPORTED variable both in toplevel configure and
>
On Tue, 27 Nov 2018 at 23:28, Rainer Orth wrote:
>
> As mentioned in passing in PR d/87864, libgphobos.so currently fails to
> link before Solaris 11.4. Until then, you needed to link with -lsocket
> -lnsl for the networking functions, in S11.4 they were merged into libc.
>
> To fix this, I've ad
On Sat, 16 Feb 2019 at 13:58, Bernd Edlinger wrote:
>
> On 2/9/19 7:21 PM, Bernd Edlinger wrote:
> > On 2/9/19 7:18 PM, Jakub Jelinek wrote:
> >> On Sat, Feb 09, 2019 at 06:11:00PM +, Bernd Edlinger wrote:
> >>> --- libphobos/libdruntime/Makefile.am (revision 268614)
> >>> +++ libphobos/
Hi Jason,
On 18/02/19 19:28, Jason Merrill wrote:
On 2/18/19 5:31 AM, Paolo Carlini wrote:
Hi Jason,
On 18/02/19 10:20, Jason Merrill wrote:
On 2/17/19 6:58 AM, Paolo Carlini wrote:
Hi,
here, when we don't see an initializer we believe we are surely
dealing with a case of C++17 template ar
Hello world,
this patch fixes the 9 regression in C interop with contiguous
arguments recently reported by Reinhold Bader.
ChangeLog and patch say it all. I hope I didn't overlook any
obvious things here (Paul, maybe you can take a look).
Regression-tested. OK for trunk?
Regards
Thom
Hi Bernd,
Am 16.02.19 um 13:58 schrieb Bernd Edlinger:
So here is the latest version with the requested change.
How is the procedure with libpobos patches?
Can we check them into the gcc svn, or will Ian have to
push them first into the upstream?
Most phobos/druntime changes should be upstre
On 2/17/19 11:54 AM, Marek Polacek wrote:
On Sat, Feb 16, 2019 at 03:54:21PM -0500, Marek Polacek wrote:
I noticed this test fails in c++2a since the implementation of P0846
landed in r265734. Since it's in g++.old-deja/, I never noticted the
fail (but I don't see any others). This patch tweak
Martin Sebor writes:
> Recent libgcc builds have been triggering -Wbuiltin-declaration-mismatch
> due to the declaration of the __clear_cache built-in being incompatible
> with how GCC declares it internally. The attached patch adjusts
> the libgcc declaration and the one in the manual to match w
Sharon Dvir writes:
> Description: fixed a couple of typos in testsuite/README.
> Testing: make dvi, make info, although I doubt needed.
Applied, thanks.
Richard
On Mon, Feb 18, 2019 at 10:30 PM Thomas Koenig
wrote:
> Hi Janne,
>
> > I'm not really sure if there is any good reason why GFortran occasionally
> > generates these varargs declarations, hence my suggestion to get rid of
> > them. Unless the middle-end is planning to get rid of untyped function
Hi Janne,
I'm not really sure if there is any good reason why GFortran occasionally
generates these varargs declarations, hence my suggestion to get rid of
them. Unless the middle-end is planning to get rid of untyped function
decls?
Are they still being generated after the patch went in? I'm
On Mon, Feb 18, 2019 at 09:15:39PM +0100, Rainer Orth wrote:
> 2019-02-15 Rainer Orth
>
> * g++.dg/torture/pr89303.C (bad_weak_ptr): Rename to
> bad_weak_ptr_.
Ok, thanks.
If needed, guess we could rename much more (or rename the namespace in which
most of it is from std to my_std,
On Mon, Feb 18, 2019 at 7:25 PM Segher Boessenkool <
seg...@kernel.crashing.org> wrote:
> On Mon, Feb 18, 2019 at 10:48:35AM +0200, Janne Blomqvist wrote:
> > I wonder if we shouldn't exorcise all the varargs stuff, it seems to
> > cause more problems than benefits? But not in stage4 if we can avo
Hi Jakub,
>> The following testcase is miscompiled on x86_64-linux (-m32 and -m64) at
>> -O1, as a pointer has two vars in points-to set, the first one is escaped
>> heap var and the second one is escaped non-heap var, and in the end the last
>> var that sets vars_contains_escaped won and overwrot
On 2/4/19 3:52 PM, Martin Jambor wrote:
> Hi,
>
> On Mon, Feb 04 2019, Marc Glisse wrote:
>> On Mon, 4 Feb 2019, Martin Sebor wrote:
>>>
>
> ...
>
>>> You're right that this is hard to imagine without first hand experience
>>> with the problem. If this is a common pattern with the warning in C+
Hi Christophe,
> dg-extract-results currently moves lines like
> WARNING: program timed out
> at the end of each .exp section when it generates .sum files.
>
> This is because it sorts its output based on the 2nd field, which is
> normally the testname as in:
> FAIL: gcc.c-torture/execute/20020129
On 2/14/19 7:23 AM, Tom Tromey wrote:
>> "Marc" == Marc Glisse writes:
>
>>> Lastly, in the case of uninitialized variables, the usual solution
>>> of initializing them is trivial and always safe (some coding styles
>>> even require it).
>
> Marc> Here it shows that we don't work with the sa
On Mon, Feb 18, 2019 at 2:48 AM Rainer Orth
wrote:
>
> > The code was already calling syscall, it was just doing it in a way
> > that the types didn't necessarily match the C declaration. This is
> > the implementation of Go's syscall.Syscall function, so there isn't
> > really anything else we
On 2/18/19 7:44 AM, Martin Liška wrote:
PING^1
On 11/30/18 11:26 AM, Martin Liška wrote:
Hi Jason.
Just small nits I noticed for:
cat test4.C
int a, b, c;
void
__attribute__((noinline))
bar()
{
if (a == 123)
[[likely]] c = 5;
else
[[likely]] b = 77;
}
int main()
{
bar ();
Description: fixed a couple of typos in testsuite/README.
Testing: make dvi, make info, although I doubt needed.
svn diff (with -up) yields:
Index: gcc/testsuite/README
===
--- gcc/testsuite/README(revision 268955)
+++ gcc/tes
Emulate MMX ssse3_phdv2si3 with SSE by moving bits
64:95 to bits 32:63 in SSE register. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/sse.md (ssse3_phdv2si3):
Changed to define_insn_and_split to support SSE emulation.
---
gcc/config/i386/sse.m
Emulate MMX mmx_uavgv4hi3 with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_uavgv4hi3): Also check TARGET_MMX and
TARGET_MMX_WITH_SSE.
(*mmx_uavgv4hi3): Add SSE emulation.
---
gcc/config/i386/mmx.md | 26 +
Emulate MMX ssse3_phwv4hi3 with SSE by moving bits
64:95 to bits 32:63 in SSE register. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/sse.md (ssse3_phwv4hi3):
Changed to define_insn_and_split to support SSE emulation.
---
gcc/config/i386/sse.m
On 2/15/19 9:01 PM, Sandra Loosemore wrote:
On 2/13/19 4:33 PM, Martin Sebor wrote:
Index: gcc/doc/extend.texi
===
--- gcc/doc/extend.texi (revision 268856)
+++ gcc/doc/extend.texi (working copy)
@@ -12890,6 +12890,22 @@ buil
PR target/89021
* config/i386/mmx.md (MMXMODE:mov): Also allow
TARGET_MMX_WITH_SSE.
(MMXMODE:*mov_internal): Likewise.
(MMXMODE:movmisalign): Likewise.
---
gcc/config/i386/mmx.md | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/c
Emulate MMX ssse3_pmaddubsw with SSE. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/sse.md (ssse3_pmaddubsw): Add SSE emulation.
---
gcc/config/i386/sse.md | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/gcc/con
This pach enables TM MMX intrinsics with SSE2 when MMX is disabled.
PR target/89021
* config/i386/i386.c (bdesc_tm): Enable MMX intrinsics with
SSE2.
---
gcc/config/i386/i386.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/gcc/config/
Emulate MMX V4HI smaxmin/V8QI umaxmin with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_v4hi3): Also check TARGET_MMX
and TARGET_MMX_WITH_SSE.
(mmx_v8qi3): Likewise.
(smaxmin:v4hi3): New.
(umaxmin:v8qi3
Emulate MMX maskmovq with SSE2 maskmovdqu for TARGET_MMX_WITH_SSE by
zero-extending source and mask operands to 128 bits. Handle unmapped
bits 64:127 at memory address by adjusting source and mask operands
together with memory address.
PR target/89021
* config/i386/xmmintrin.h: Em
Emulate MMX version of pshufb with SSE version by masking out the bit 3
of the shuffle control byte. Only SSE register source operand is allowed.
PR target/89021
* config/i386/sse.md (ssse3_pshufbv8qi3): Changed to
define_insn_and_split. Also allow TARGET_MMX_WITH_SSE. A
Emulate MMX mmx_umulv4hi3_highpart with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_umulv4hi3_highpart): Also check
TARGET_MMX and TARGET_MMX_WITH_SSE.
(*mmx_umulv4hi3_highpart): Add SSE emulation.
---
gcc/config/i38
Emulate MMX mmx_pinsrw with SSE. Only SSE register destination operand
is allowed.
PR target/89021
* config/i386/mmx.md (mmx_pinsrw): Also check TARGET_MMX and
TARGET_MMX_WITH_SSE.
(*mmx_pinsrw): Add SSE emulation.
---
gcc/config/i386/mmx.md | 33 +
PR target/89021
* config/i386/mmx.md (*vec_dupv2sf): Changed to
define_insn_and_split to support SSE emulation.
(*vec_extractv2sf_0): Likewise.
(*vec_extractv2sf_1): Likewise.
(*vec_extractv2si_0): Likewise.
(*vec_extractv2si_1): Likewise.
Emulate MMX movntq with SSE2 movntidi. Only register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (sse_movntq): Add SSE2 emulation.
---
gcc/config/i386/mmx.md | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/gcc/config/i386/mmx
From: Uros Bizjak
2019-02-18 Uroš Bizjak
PR target/89021
* config/i386/i386.md (*zero_extendsidi2): Add mmx_isa attribute.
* config/i386/sse.md (sse2_cvtpi2pd): Ditto.
(sse2_cvtpd2pi): Ditto.
(sse2_cvttpd2pi): Ditto.
(*vec_concatv2sf_sse4_1): Di
Emulate MMX abs2 with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/sse.md (abs2): Add SSE emulation.
---
gcc/config/i386/sse.md | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/gcc/config/i386/sse.md b/gcc/conf
Emulate MMX mmx_uavgv8qi3 with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_uavgv8qi3): Also check TARGET_MMX
and TARGET_MMX_WITH_SSE.
(*mmx_uavgv8qi3): Add SSE emulation.
---
gcc/config/i386/mmx.md | 25 +
Emulate MMX mmx_psadbw with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_psadbw): Add SSE emulation.
---
gcc/config/i386/mmx.md | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/gcc/config/i386/
Emulate MMX version of palignrq with SSE version by concatenating 2
64-bit MMX operands into a single 128-bit SSE operand, followed by
SSE psrldq. Only SSE register source operand is allowed.
PR target/89021
* config/i386/sse.md (ssse3_palignrdi): Changed to
define_insn_an
Emulate MMX umulv1siv1di3 with SSE2. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/mmx.md (sse2_umulv1siv1di3): Add SSE emulation
support.
(*sse2_umulv1siv1di3): Add SSE2 emulation.
---
gcc/config/i386/mmx.md | 26 -
Emulate MMX ssse3_psign3 with SSE. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/sse.md (ssse3_psign3): Add SSE emulation.
---
gcc/config/i386/sse.md | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/gcc/config/i3
On 2/16/19 12:12 AM, Jakub Jelinek wrote:
Hi!
Both the C and C++ standard guarantee that the argc argument to main is
non-negative, the following patch sets (or adjusts) the corresponding
SSA_NAME_RANGE_INFO. While main is just one, with IPA VRP it can also
propagate etc. I had to change one t
On 2/15/19 8:30 PM, Sandra Loosemore wrote:
On 2/13/19 2:46 PM, Martin Sebor wrote:
The attached patch adds documentation for the __has_attribute (and
__has_cpp_attribute) and __has_include operators added in r215752.
Thanks!
I was a little unsure where to add this, whether the preprocessor
Allow MMX intrinsic emulation with SSE/SSE2/SSSE3. Don't enable MMX ISA
by default with TARGET_MMX_WITH_SSE.
For pr82483-1.c and pr82483-2.c, "-mssse3 -mno-mmx" compiles in 64-bit
mode since MMX intrinsics can be emulated wit SSE.
gcc/
PR target/89021
* config/i386/i386-builtin.
With SSE emulation of MMX intrinsics, we should make _mm_empty () as NOP
without MMX.
PR target/89021
* config/i386/mmx.md (mmx_): Renamed to ...
(*mmx_): This.
(mmx_): New expander.
---
gcc/config/i386/mmx.md | 30 +-
1 file changed, 29
Emulate MMX mmx_pmovmskb with SSE by zero-extending result of SSE pmovmskb
from QImode to SImode. Only SSE register source operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_pmovmskb): Changed to
define_insn_and_split to support SSE emulation.
---
gcc/config/i3
Emulate MMX pshufw with SSE. Only SSE register source operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_pshufw): Also check TARGET_MMX and
TARGET_MMX_WITH_SSE.
(mmx_pshufw_1): Add SSE emulation.
(*vec_dupv4hi): Changed to define_insn_and_split a
Emulate MMX ssse3_pmulhrswv4hi3 with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/sse.md (ssse3_pmulhrswv4hi3): Require TARGET_MMX
or TARGET_MMX_WITH_SSE.
(*ssse3_pmulhrswv4hi3): Add SSE emulation.
---
gcc/config/i386/sse.md | 26
Emulate MMX sse_cvtps2pi/sse_cvttps2pi with SSE.
PR target/89021
* config/i386/sse.md (sse_cvtps2pi): Add SSE emulation.
(sse_cvttps2pi): Likewise.
---
gcc/config/i386/sse.md | 30 ++
1 file changed, 18 insertions(+), 12 deletions(-)
diff --git
Emulate MMX mmx_pextrw with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_pextrw): Add SSE emulation.
---
gcc/config/i386/mmx.md | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/gcc/config/i386/m
Emulate MMX mulv4hi3 with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_mulv4hi3): Also allow
TARGET_MMX_WITH_SSE.
(mulv4hi3): New.
(*mmx_mulv4hi3): Also allow TARGET_MMX_WITH_SSE. Add SSE
support.
---
Emulate MMX sse_cvtpi2ps with SSE2 cvtdq2ps, preserving upper 64 bits of
destination XMM register. Only SSE register source operand is allowed.
PR target/89021
* config/i386/sse.md (sse_cvtpi2ps): Changed to
define_insn_and_split. Also allow TARGET_MMX_WITH_SSE. Add
Emulate MMX mmx_andnot3 with SSE. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/mmx.md (mmx_andnot3): Also allow
TARGET_MMX_WITH_SSE. Add SSE support.
---
gcc/config/i386/mmx.md | 18 +++---
1 file changed, 11 insertions(+), 7 del
Emulate MMX ashr3/3 with SSE. Only SSE register
source operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_ashr3): Also allow
TARGET_MMX_WITH_SSE. Add SSE emulation.
(mmx_3): Likewise.
(ashr3): New.
(3): Likewise.
---
gcc/config/i386/mmx
Emulate MMX vec_dupv2si with SSE. Add the "Yw" constraint to allow
broadcast from integer register for AVX512BW with TARGET_AVX512VL.
Only SSE register source operand is allowed.
PR target/89021
* config/i386/constraints.md (Yw): New constraint.
* config/i386/mmx.md (*vec_
Emulate MMX 3 with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/mmx.md (any_logic:mmx_3): Also allow
TARGET_MMX_WITH_SSE.
(any_logic:3): New.
(any_logic:*mmx_3): Also allow TARGET_MMX_WITH_SSE.
Add SSE support.
---
Emulate MMX mmx_eq/mmx_gt3 with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_eq3): Also allow
TARGET_MMX_WITH_SSE.
(*mmx_eq3): Also allow TARGET_MMX_WITH_SSE. Add SSE
support.
(mmx_gt3): Likewise.
---
On x86-64, since __m64 is returned and passed in XMM registers, we can
emulate MMX intrinsics with SSE instructions. To support it, we added
#define TARGET_MMX_WITH_SSE (TARGET_64BIT && TARGET_SSE2)
;; Define instruction set of MMX instructions
(define_attr "mmx_isa" "base,native,x64,x64_noavx,x
Emulate MMX pmaddwd with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_pmaddwd): Also allow TARGET_MMX_WITH_SSE.
(*mmx_pmaddwd): Also allow TARGET_MMX_WITH_SSE. Add SSE support.
---
gcc/config/i386/mmx.md | 25 +++
Emulate MMX punpcklXX/punpckhXX with SSE punpcklXX. For MMX punpckhXX,
move bits 64:127 to bits 0:63 in SSE register. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/i386-protos.h (ix86_split_mmx_punpck): New
prototype.
* config/i386/i38
Emulate MMX mulv4hi3 with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_smulv4hi3_highpart): Also allow
TARGET_MMX_WITH_SSE.
(*mmx_smulv4hi3_highpart): Also allow TARGET_MMX_WITH_SSE. Add
SSE support.
---
gcc/c
Emulate MMX packsswb/packssdw/packuswb with SSE packsswb/packssdw/packuswb
plus moving bits 64:95 to bits 32:63 in SSE register. Only SSE register
source operand is allowed.
2019-02-08 H.J. Lu
Uros Bizjak
PR target/89021
* config/i386/i386-protos.h (ix86_move_vec
Emulate MMX plusminus/sat_plusminus with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/mmx.md (MMXMODEI8): Require TARGET_SSE2 for V1DI.
(plusminus:mmx_3): Check
TARGET_MMX_WITH_SSE.
(sat_plusminus:mmx_3): Likewise.
In 64-bit mode, SSE2 can be used to emulate MMX instructions without
3DNOW. We can use SSE2 to support MMX register modes.
PR target/89021
* config/i386/i386-c.c (ix86_target_macros_internal): Define
__MMX_WITH_SSE__ for TARGET_MMX_WITH_SSE.
* config/i386/i386.c (i
I have now committed the patch as r268992. Janne and Richard, thanks
for the review and the comments.
Am 18.02.19 um 13:50 schrieb Richard Biener:
On Sun, Feb 17, 2019 at 7:19 PM Thomas Koenig wrote:
Regression tests turned up a few ICEs (now fixed), plus two
very invalid test cases, which I
On 2/18/19 10:41 AM, Alexander Monakov wrote:
> On Mon, 18 Feb 2019, Aaron Sawdey wrote:
>
>> The code in emit_case_dispatch_table() will very clearly always emit
>> branch/label/jumptable_data/barrier
>> so this does need to be handled. So, yes tablejump always looks like this,
>> and also ye
On 2/18/19 5:31 AM, Paolo Carlini wrote:
Hi Jason,
On 18/02/19 10:20, Jason Merrill wrote:
On 2/17/19 6:58 AM, Paolo Carlini wrote:
Hi,
here, when we don't see an initializer we believe we are surely
dealing with a case of C++17 template argument deduction for class
templates, but, in fact,
On Mon, Feb 18, 2019 at 10:48:35AM +0200, Janne Blomqvist wrote:
> I wonder if we shouldn't exorcise all the varargs stuff, it seems to
> cause more problems than benefits? But not in stage4 if we can avoid
> it..
On the Power ABIs at least, unprototyped functions (a K&R thing for C) are
handled t
Ping: https://gcc.gnu.org/ml/gcc-patches/2019-02/msg00361.html
On 2/6/19 5:28 PM, Martin Sebor wrote:
Recent libgcc builds have been triggering -Wbuiltin-declaration-mismatch
due to the declaration of the __clear_cache built-in being incompatible
with how GCC declares it internally. The attache
On Mon, 18 Feb 2019, Aaron Sawdey wrote:
> The code in emit_case_dispatch_table() will very clearly always emit
> branch/label/jumptable_data/barrier
> so this does need to be handled. So, yes tablejump always looks like this,
> and also yes it seems to be
> ripe ground for logic bugs, we have 8
The code in emit_case_dispatch_table() will very clearly always emit
branch/label/jumptable_data/barrier
so this does need to be handled. So, yes tablejump always looks like this, and
also yes it seems to be
ripe ground for logic bugs, we have 88308, 88347, 88423 all related to it.
In the long t
On Mon, Feb 18, 2019 at 6:37 AM Uros Bizjak wrote:
>
> On Mon, Feb 18, 2019 at 3:22 PM H.J. Lu wrote:
>
> > > > > > > > > > > > On x86-64, since __m64 is returned and passed in XMM
> > > > > > > > > > > > registers, we can
> > > > > > > > > > > > emulate MMX intrinsics with SSE instructions. To
Handle stack pointer with SUBS/ADDS instructions.
In general the stack pointer was not handled for many SUBS/ADDS patterns in
aarch64.md.
Both the "extended register" and "immediate" forms allow the stack pointer to be
used as the source register, while no form allows the stack pointer for the
des
On Mon, Feb 18, 2019 at 3:22 PM H.J. Lu wrote:
> > > > > > > > > > > On x86-64, since __m64 is returned and passed in XMM
> > > > > > > > > > > registers, we can
> > > > > > > > > > > emulate MMX intrinsics with SSE instructions. To support
> > > > > > > > > > > it, we added
> > > > > > > > > >
1 - 100 of 129 matches
Mail list logo
