Ping?
On Wed, Aug 09, 2017 at 08:58:31PM +0930, Alan Modra wrote:
> PR rtl-optimization/81747
> * cse.c (cse_extended_basic_block): Don't attempt to record
> equivalences for degenerate conditional jumps that branch
> to their fall-through.
>
> diff --git a/gcc/cse.c b/gcc
On Wed, Aug 16, 2017 at 01:46:12AM +, Joseph Myers wrote:
> ENOPATCH
2017-08-15 Michael Meissner
PR libquadmath/81848
* configure.ac (powerpc*-linux*): Use attribute mode KC to create
complex __float128 on PowerPC instead of attribute mode TC.
* quadmth.h (_
ENOPATCH
--
Joseph S. Myers
jos...@codesourcery.com
Committed as obvious.
* config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Delete
dead code.
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 5e79933..f9aa13b 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -3238,17 +3238
On 08/13/2017 10:35 AM, Thomas Koenig wrote:
the attached patch fixes the PR by adding a dependency check
for the case of concatenation operators.
Regression-tested. OK for trunk?
Ping?
Regards
Thomas
OK,
Thanks for patch.
Jerry
I'm working on some changes to finally make __float128 default for PowerPC VSX
targets (power7..power9). I am reworking my PowerPC changes, but in using a
previous version of my code, I needed to do some minor tweaks to allow
libquadmath to build on PowerPC when __float128 becomes on by default.
On Wed, 16 Aug 2017, Oleg Endo wrote:
> This is an older issue. Please also add a reference to PR 67712 in
> your commit. Can you also apply it to GCC 6 branch please?
I can't reproduce the problem with GCC 6 branch; the glibc testsuite
builds fine without out-of-memory issues, as does the tes
On Tue, 2017-08-15 at 21:15 +, Joseph Myers wrote:
> GCC mainline built for sh4-linux-gnu runs out of memory building a
> glibc test, which calls strncmp with very large constant size
> argument, resulting in the SH inline strncmp expansion trying to
> inline a fully unrolled expansion of strnc
Repost with requested changes. I've extracted the logic that omits
frame saves from rs6000_frame_related to a new function, because it's
easier to document that way. The logic has been simplified a little
too: fixed_reg_p doesn't need to be called there.
PR target/80938
* config/
On 07/13/2017 02:52 AM, Richard Sandiford wrote:
> strict_volatile_bitfield_p returns false for any mode that isn't
> a scalar integer. This patch moves the check to the caller and
> makes strict_volatile_bitfield_p take the mode as a scalar_int_mode.
> The handling of a true return can then also
On 07/13/2017 02:51 AM, Richard Sandiford wrote:
> cstore patterns always have a scalar integer result, which has the
> value 0 for "false" and STORE_FLAG_VALUE for "true". This patch
> makes that explicit using scalar_int_mode.
>
> 2017-07-13 Richard Sandiford
> Alan Hayward
>
On 07/13/2017 02:51 AM, Richard Sandiford wrote:
> This patch adds asserting as_a conversions
> to contexts in which the input is known to be a scalar integer mode.
>
> In expand_divmod, op1 is always a scalar_int_mode if
> op1_is_constant (but might not be otherwise).
>
> In expand_binop, the p
Hi,
I forgot to mention that I didn't include a test case. Carl's upcoming patch
will cause
this to be well tested with the existing test suite, so I think that's not
needed. Let me
know if you disagree.
Thanks,
Bill
> On Aug 15, 2017, at 4:14 PM, Bill Schmidt wrote:
>
> Hi,
>
> One of Ca
GCC mainline built for sh4-linux-gnu runs out of memory building a
glibc test, which calls strncmp with very large constant size
argument, resulting in the SH inline strncmp expansion trying to
inline a fully unrolled expansion of strncmp for that size.
This patch limits that fully unrolled expans
Hi,
One of Carl Love's proposed built-in function patches exposed a bug in the Power
code that recognizes specific permute control vector patterns for a permute, and
changes the permute to a more specific and more efficient instruction. The
patterns for p8_vmrgew_v4si and p8_vmrgow are generated
On Tue, Aug 15, 2017 at 4:59 PM, Richard Biener
wrote:
> So I'd try the "easy" way of expanding if (__builtin_cpu_supports ("sse4.1"))
> as the sse4.1 sequence is just a single instruction. The interesting part
> of the story will be to make sure we can emit that even if ! TARGET_ROUND ...
>
> U
On 07/13/2017 02:50 AM, Richard Sandiford wrote:
> This patch adds a SCALAR_INT_TYPE_MODE macro that asserts
> that the type has a scalar integer mode and returns it as
> a scalar_int_mode.
>
> 2017-07-13 Richard Sandiford
> Alan Hayward
> David Sherwood
>
> gcc/
>
On 07/13/2017 02:49 AM, Richard Sandiford wrote:
> The postreload move2add optimisations are specific to scalar
> integers. This patch adds an explicit check to the main guarding
> "if" and propagates the information through subroutines.
>
> gcc/
> 2017-07-13 Richard Sandiford
> Alan
On 07/13/2017 02:48 AM, Richard Sandiford wrote:
> This patch adds is_a checks to various places
> that were explicitly or implicitly restricted to integers already,
> in cases where adding an explicit is_a is useful
> for later patches.
>
> In simplify_if_then_else, the:
>
> GET_MODE (XEXP (
On 07/13/2017 02:48 AM, Richard Sandiford wrote:
> This patch adds is_a checks to various places that
> were optimising subregs or extractions in ways that only made sense
> for scalar integers. Often the subreg transformations were looking
> for extends, truncates or shifts and trying to remove
On Aug 15, 2017, at 6:35 AM, Martin Liška wrote:
>
> Simple fix for the PR where we wrongly combine extra_objs.
> Ready to install the patch?
Ok.
> PR target/81753
> * config.gcc: Respect previously set extra_objs in case
> of darwin target.
Richard Biener writes:
> On Tue, Aug 15, 2017 at 11:28 AM, Bin Cheng wrote:
>> Hi,
>> This patch fixes PR81832. Root cause for the ICE is:
>> 1) Loop has distributed inner loop.
>> 2) The guarding function call IFN_LOOP_DIST_CALL happens to be in loop's
>> header.
>> 3) IFN_LOOP_DIST_CALL
ping
From: Wilco Dijkstra
Sent: 31 July 2017 16:57
To: GCC Patches; James Greenhalgh
Cc: nd
Subject: [PATCH][AArch64] PR71951: Fix unwinding with -fomit-frame-pointer
As described in PR71951, if libgcc is built with -fomit-frame-pointer,
unwinding crashes, for example while doing a backtrac
ping
From: Wilco Dijkstra
Sent: 26 July 2017 14:46
To: GCC Patches; James Greenhalgh
Cc: nd
Subject: [PATCH][AArch64] Remove '*' from movsi/di/ti patterns
Remove the remaining uses of '*' from the movsi/di/ti patterns.
Using '*' in alternatives is typically incorrect at it tells the regi
ping
From: Wilco Dijkstra
Sent: 17 January 2017 15:14
To: Richard Earnshaw; GCC Patches; James Greenhalgh
Cc: nd
Subject: Re: [PATCH v3][AArch64] Fix symbol offset limit
Here is v3 of the patch - tree_fits_uhwi_p was necessary to ensure the size of a
declaration is an integer. So the questio
ping
From: Wilco Dijkstra
Sent: 25 July 2017 14:58
To: GCC Patches; James Greenhalgh; Jeff Law
Cc: nd
Subject: [PATCH][AArch64] Simplify frame layout for stack probing
This patch makes some changes to the frame layout in order to simplify
stack probing. We want to use the save of LR as
ping
This patch further improves aarch64_legitimate_constant_p. Allow all
integer, floating point and vector constants. Allow label references
and non-anchor symbols with an immediate offset. This allows such
constants to be rematerialized, resulting in smaller code and fewer stack
ping
From: Wilco Dijkstra
Sent: 04 August 2017 13:41
To: GCC Patches; James Greenhalgh
Cc: nd
Subject: [PATCH][AArch64] Remove aarch64_frame_pointer_required
To implement -fomit-leaf-frame-pointer, there are 2 places where we need
to check whether we have to use a frame chain (since register
ping
From: Wilco Dijkstra
Sent: 20 July 2017 13:49
To: GCC Patches; James Greenhalgh
Cc: nd
Subject: [PATCH][AArch64] Improve addressing of TI/TFmode
In https://gcc.gnu.org/ml/gcc-patches/2017-06/msg01125.html Jiong
pointed out some addressing inefficiencies due to a recent change in
ping
From: Wilco Dijkstra
Sent: 04 August 2017 13:26
To: GCC Patches; James Greenhalgh
Cc: nd
Subject: [PATCH][AArch64] Introduce emit_frame_chain
The current frame code combines the separate concepts of a frame chain
(saving old FP,LR in a record and pointing new FP to it) and a frame
poi
ping
From: Wilco Dijkstra
Sent: 07 August 2017 15:13
To: GCC Patches; James Greenhalgh
Cc: nd; Richard Earnshaw
Subject: [PATCH][AArch64] Simplify aarch64_can_eliminate
Simplify aarch64_can_eliminate - if we need a frame pointer, we must
eliminate to HARD_FRAME_POINTER_REGNUM. Rather than
ping
From: Wilco Dijkstra
Sent: 04 August 2017 16:46
To: GCC Patches; James Greenhalgh
Cc: nd
Subject: [PATCH][AArch64] PR60580: Fix frame pointer option magic
To fix PR60580 simplify the logic in aarch64_override_options_after_change_1 ().
If the frame pointer is enabled, set it to a speci
On 08/15/2017 07:30 AM, Andrew Burgess wrote:
* Claudiu Zissulescu [2017-07-24 10:42:54
+0200]:
From: claziss
Add support for -G option to ARC backend.
gcc/
2017-04-24 Claudiu Zissulescu
* config.gcc: Use g.opt for arc.
* config/arc/arc.c (LEGITIMATE_SCALED_ADDRESS_P):
On Tue, Aug 15, 2017 at 4:43 PM, Richard Biener
wrote:
> On Tue, Aug 15, 2017 at 4:21 PM, Richard Biener
> wrote:
>> On Tue, Aug 15, 2017 at 3:52 PM, Martin Jambor wrote:
>>> Hi Joseph,
>>>
>>> On Thu, May 26, 2016 at 09:02:02PM +, Joseph Myers wrote:
On Thu, 26 May 2016, Jan Hubicka wr
Hi!
On Tue, Aug 15, 2017 at 03:35:36PM +0200, Martin Liška wrote:
> Simple fix for the PR where we wrongly combine extra_objs.
>
> Ready to install the patch?
Looks fine to me. This code is also for x86, but you could well
call this obvious and/or trivial :-) (Testing on x86 wouldn't
hurt of c
On Tue, Aug 15, 2017 at 4:21 PM, Richard Biener
wrote:
> On Tue, Aug 15, 2017 at 3:52 PM, Martin Jambor wrote:
>> Hi Joseph,
>>
>> On Thu, May 26, 2016 at 09:02:02PM +, Joseph Myers wrote:
>>> On Thu, 26 May 2016, Jan Hubicka wrote:
>>>
>>> > > > +ffp-int-builtin-inexact
>>> > > > +Common Rep
On Tue, Aug 15, 2017 at 3:52 PM, Martin Jambor wrote:
> Hi Joseph,
>
> On Thu, May 26, 2016 at 09:02:02PM +, Joseph Myers wrote:
>> On Thu, 26 May 2016, Jan Hubicka wrote:
>>
>> > > > +ffp-int-builtin-inexact
>> > > > +Common Report Var(flag_fp_int_builtin_inexact) Optimization
>> > > > +Allow
On Tue, 15 Aug 2017, Martin Jambor wrote:
> I am not sure what to do about this, to me it seems that the
> -ffp-int-builtin-inexact simply has a wrong default value, at least
> for x86_64, as it was added in order not to slow code down but does
> exactly that (all of the slowdown of course disappe
Richard Biener wrote:
> > We also change the association of
> >
> > x / (y * C) -> (x / C) / y
> >
> > If C is a constant.
>
> Why's that profitable?
It enables (x * C1) / (y * C2) -> (x * C1/C2) / y for example.
Also 1/y is now available to the reciprocal optimization, see
https://gcc.gnu.o
On Thu, Aug 10, 2017 at 4:10 PM, Jackson Woodruff
wrote:
> Hi all,
>
> The patch implements the some of the division optimizations discussed in
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71026 .
>
> We now reassociate (as discussed in the bug report):
>
> x / (y * y) -> x * (1 / y) * (1 /
On Thu, Aug 10, 2017 at 4:09 PM, Jackson Woodruff
wrote:
> Hi all,
>
> The patch implements the division opitmizations discussed in
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71026 .
>
> The implemented change differs slightly from the
> proposed one in that we re-associate:
>
> C / x comp
Hi Joseph,
On Thu, May 26, 2016 at 09:02:02PM +, Joseph Myers wrote:
> On Thu, 26 May 2016, Jan Hubicka wrote:
>
> > > > +ffp-int-builtin-inexact
> > > > +Common Report Var(flag_fp_int_builtin_inexact) Optimization
> > > > +Allow built-in functions ceil, floor, round, trunc to raise
> > > >
On Tue, Aug 1, 2017 at 10:56 AM, Tsimbalist, Igor V
wrote:
> Part#1. Add generic part for Intel CET enabling.
>
> The spec is available at
>
> https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf
>
> High-level design.
> --
>
* Claudiu Zissulescu [2017-07-24 10:42:55
+0200]:
> From: claziss
>
> Short branches cannot be used to jump between hot/cold
> sections. Update the hook.
>
> gcc/
> 2017-04-26 Claudiu Zissulescu
>
> * config/arc/arc.c (arc_can_follow_jump): Check for short
> branches.
This lo
Hi.
Simple fix for the PR where we wrongly combine extra_objs.
Ready to install the patch?
Thanks,
Martin
gcc/ChangeLog:
2017-08-15 Martin Liska
PR target/81753
* config.gcc: Respect previously set extra_objs in case
of darwin target.
---
gcc/config.gcc | 2 +-
1 fi
* Claudiu Zissulescu [2017-07-24 10:42:54
+0200]:
> From: claziss
>
> Add support for -G option to ARC backend.
>
> gcc/
> 2017-04-24 Claudiu Zissulescu
>
> * config.gcc: Use g.opt for arc.
> * config/arc/arc.c (LEGITIMATE_SCALED_ADDRESS_P): Deleted,
> functionality move
On Tue, 15 Aug 2017, Ian Lance Taylor wrote:
> On Tue, Aug 15, 2017 at 5:51 AM, Richard Biener wrote:
> > On Tue, 15 Aug 2017, Richard Biener wrote:
> >
> >> On Mon, 14 Aug 2017, Ian Lance Taylor wrote:
> >>
> >> > On Mon, Aug 14, 2017 at 6:17 AM, Richard Biener
> >> > wrote:
> >> > > On Fri, 4
* Claudiu Zissulescu [2017-07-24 10:42:53
+0200]:
> From: Claudiu Zissulescu
>
> Add alignment check for short load/store instructions used for sdata,
> as they request 32-bit aligned short immediate. Use sdata symbol
> alignment information and emit scalled loads/stores whenever is
> possibl
On Tue, Aug 15, 2017 at 5:51 AM, Richard Biener wrote:
> On Tue, 15 Aug 2017, Richard Biener wrote:
>
>> On Mon, 14 Aug 2017, Ian Lance Taylor wrote:
>>
>> > On Mon, Aug 14, 2017 at 6:17 AM, Richard Biener wrote:
>> > > On Fri, 4 Aug 2017, Richard Biener wrote:
>> > >
>> > >> On Fri, 28 Jul 2017,
On Tue, 15 Aug 2017, Richard Biener wrote:
> On Mon, 14 Aug 2017, Ian Lance Taylor wrote:
>
> > On Mon, Aug 14, 2017 at 6:17 AM, Richard Biener wrote:
> > > On Fri, 4 Aug 2017, Richard Biener wrote:
> > >
> > >> On Fri, 28 Jul 2017, Jason Merrill wrote:
> > >>
> > >> > On 07/28/2017 05:55 PM, Ja
On Tue, Aug 15, 2017 at 1:30 AM, Richard Biener wrote:
> On Mon, 14 Aug 2017, Ian Lance Taylor wrote:
>
>> It seems to me that if you keep any section of an SHT_GROUP, you need
>> to keep all the sections. Otherwise the section indexes in the group
>> will be left dangling.
>
> Note that all sect
Hi.
As shown in the PR, remove_prefix function is written wrongly. It does not
distinguish
in between a node in linked list and pprefix->plist. So I decide to rewrite it.
Apart from that, I identified discrepancy in between do_add_prefix and
prefix_from_string
where the later one appends always
On 08/10/2017 03:39 PM, Jan Hubicka wrote:
>>> - /* If callee has no option attributes, then it is ok to inline. */
>>> - if (!callee_tree)
>>> + /* If callee has no option attributes (or default),
>>> + then it is ok to inline. */
>>> + if (!callee_tree || callee_tree
On 08/14/2017 10:32 AM, Richard Biener wrote:
> Hmm, but the existing "lowering" part is called from the
> switch-conversion pass. So
> I'm not sure a new file is good.
Good, I'm not against having that in a single file. So new version of the patch
does that.
Patch can bootstrap on ppc64le-redha
On Mon, Aug 14, 2017 at 2:48 PM, Richard Sandiford
wrote:
> We weren't checking whether the phi in a conditional reduction was
> used by the condition itself (which isn't a case we handle).
>
> Tested on aarch64-linux-gnu and x86_64-linux-gnu. OK to install?
Ok.
Richard.
> Thanks,
> Richard
>
On Mon, Aug 14, 2017 at 5:56 PM, Nathan Sidwell wrote:
> The thread at https://gcc.gnu.org/ml/gcc/2017-08/msg00090.html discusses the
> driver behaviour when OOM kills cc1plus or whatever.
>
> This patch changes the driver so that if the inferior dies via INT, TERM,
> QUIT or KILL signals, it emi
On Sat, Aug 12, 2017 at 11:09 AM, Pierre-Marie de Rodat
wrote:
> On 08/11/2017 11:29 PM, Jason Merrill wrote:
>>
>> OK.
>
>
> Committed. Thank you for your sustained review effort, Jason. :-)
The way you use decl_ultimate_origin conflicts with the early LTO
debug patches which
make dwarf2out_abst
On Tue, Aug 15, 2017 at 11:28 AM, Bin Cheng wrote:
> Hi,
> This patch fixes PR81832. Root cause for the ICE is:
> 1) Loop has distributed inner loop.
> 2) The guarding function call IFN_LOOP_DIST_CALL happens to be in loop's
> header.
> 3) IFN_LOOP_DIST_CALL (int loop's header) is duplicat
Hi,
This patch fixes PR81832. Root cause for the ICE is:
1) Loop has distributed inner loop.
2) The guarding function call IFN_LOOP_DIST_CALL happens to be in loop's
header.
3) IFN_LOOP_DIST_CALL (int loop's header) is duplicated by pass_ch_vect thus
not eliminated.
Given pass_ch_vect
On Mon, 14 Aug 2017, Ian Lance Taylor wrote:
> On Mon, Aug 14, 2017 at 6:17 AM, Richard Biener wrote:
> > On Fri, 4 Aug 2017, Richard Biener wrote:
> >
> >> On Fri, 28 Jul 2017, Jason Merrill wrote:
> >>
> >> > On 07/28/2017 05:55 PM, Jason Merrill wrote:
> >> > > On Fri, Jul 28, 2017 at 8:54 AM,
Hi!
On Fri, Aug 11, 2017 at 12:40:11PM +0930, Alan Modra wrote:
> It is possible when using out-of-line register saves or store multiple
> to save some registers unnecessarily, for example one reg in the block
> saved might be unused. We don't need to emit eh_frame info for those
> registers as t
This PR uncovers a missed-optimization with looking up CONSTRUCTORs
resulting from match-and-simplify simplification. Those appear in
"GENERIC" form while VN internally uses exploded form.
Thus make vn_lookup_simplify_result mediate between the two -- with
the additional complication of vn_nary_
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