Re: [testsuite] Add missing dg-require-effective-target alloca to gcc testsuite

On 23/03/17 18:25, Mike Stump wrote: On Mar 23, 2017, at 8:46 AM, Tom de Vries wrote: I've run the gcc testsuite for target nvptx-none and ran into "test for excess errors" FAILs due to: ... sorry, unimplemented: target cannot support alloca. We'd encourage ports to support alloca. :-) O

Re: [PATCH][PR c++/80038][6/7 Regression] Destroy temps for _Cilk_spawn calling in the child

On 2017-03-24 05:26 +0800, Xi Ruoyao wrote: > The patch has 500+ lines so I attach it.  ChangeLog is pasted here: Damn it... I attached the draft of patch where some useless functions had not been removed. This time the attachment is correct. > 2017-03-24  Xi Ruoyao   > > PR c++/80038 >

[PATCH][PR c++/80038][6/7 Regression] Destroy temps for _Cilk_spawn calling in the child

Hi, After r227423, GCC begun to destroy temps for cilkplus spawned functions in the parent, instead of in the child.  This violated Intel Cilk specs and broke some valid code such as NumericMonoid

Re: [PATCH] Fix profiledbootstrap ada checking failure (PR debug/79255)

On Thu, Mar 23, 2017 at 4:44 PM, Jakub Jelinek wrote: > The following C testcase shows how profiledbootstrap fails with checking > compiler. We have a (nested) FUNCTION_DECL inside of BLOCK_VARS of an > inline function, when it gets inlined, it is moved into > BLOCK_NONLOCALIZED_VARS. And, decls

Re: C++ PATCH to fix ICE in replace_placeholders_r (PR c++/79937)

On Thu, Mar 23, 2017 at 4:34 PM, Marek Polacek wrote: > On Tue, Mar 14, 2017 at 02:34:30PM -0400, Jason Merrill wrote: >> On Tue, Mar 14, 2017 at 2:33 PM, Jason Merrill wrote: >> > On Tue, Mar 7, 2017 at 12:10 PM, Marek Polacek wrote: >> >> In this testcase we have >> >> C c = bar (X{1}); >> >>

[PATCH] Fix profiledbootstrap ada checking failure (PR debug/79255)

Hi! The following C testcase shows how profiledbootstrap fails with checking compiler. We have a (nested) FUNCTION_DECL inside of BLOCK_VARS of an inline function, when it gets inlined, it is moved into BLOCK_NONLOCALIZED_VARS. And, decls_for_scope calls process_scope_var with NULL decl and non-

[PATCH] avoid cselib rtx_equal_for_cselib_1 infinite recursion (PR debug/80025)

Hi! On Thu, Mar 23, 2017 at 03:00:04PM +0100, Jakub Jelinek wrote: > On Tue, Mar 21, 2017 at 07:43:51PM -0300, Alexandre Oliva wrote: > > When two VALUEs are recorded in the cselib equivalence table such that > > they are equivalent to each other XORed with the same expression, if > > we started a

[C++ PATCH] Fix -fsanitize={null,alignment} of references (PR c++/79572)

Hi! Since late C++ folding has been committed, we don't sanitize some reference bindings to NULL. Earlier we had always NOP_EXPR to REFERENCE_TYPE say from INTEGER_CST or whatever else, but cp_fold can now turn that right into INTEGER_CST with REFERENCE_TYPE. The following patch sanitizes even t

Re: C++ PATCH to fix ICE in replace_placeholders_r (PR c++/79937)

On Tue, Mar 14, 2017 at 02:34:30PM -0400, Jason Merrill wrote: > On Tue, Mar 14, 2017 at 2:33 PM, Jason Merrill wrote: > > On Tue, Mar 7, 2017 at 12:10 PM, Marek Polacek wrote: > >> In this testcase we have > >> C c = bar (X{1}); > >> which store_init_value sees as > >> c = TARGET_EXPR >> .n=(&)

Re: [CHKP] Fix for PR79990

2017-03-23 17:18 GMT+03:00 Alexander Ivchenko : > Hi, > > The patch below attempts to fix the PR. I checked that it did not > break any of mpx.exp tests, but I did not run the full testing yet. > Would like to know whether this approach is generally correct or not. > > The issue is that we have the

[C++ Patch/RFC] PR 80145

Hi, this ICE on invalid code isn't a regression, thus a patch probably doesn't qualify for Stage 4, but IMHO I made good progress on it and I'm sending what I have now anyway... The ICE happens during error recovery after a sensible diagnostic for the first declaration in: auto* foo() { retu

[PATCH] Fix PR80158

Hi, https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80158 reports an ICE in SLSR while building 416.gamess on x86_64. This is a latent (but previously harmless) bug that was exposed by the fix for PR80054. When replacing any statement with a strength reduction, SLSR updates the candidate statement S

C++ PATCH for c++/80150, ICE with overloaded variadic deduction

This bug is related to 69056, where I implemented deducing a pack that starts with explicitly specified arguments. In that patch I added a sanity check to make sure that when we do that we always start from a pack marked incomplete. But this test demonstrates a case where that check is wrong; if

Re: [Patch] Inline Variables for the Standard Library (p0607r0)

On 23/03/17 13:47 -0400, Tim Song wrote: On Thu, Mar 23, 2017 at 1:45 PM, Jonathan Wakely wrote: + // NOTE: This makes use of the fact that we know how moveable + // is implemented on pair, and also vector. If the implementation + // changes this test may begin to fail. Maybe drop this commen

[PATCH] Fix Debug Mode test failures

This fixes some recent testsuite FAILures with Debug Mode. * testsuite/23_containers/array/tuple_interface/ tuple_element_debug_neg.cc: Adjust dg-error. * testsuite/23_containers/list/operations/78389.cc: Fix less-than to define a valid strict weak ordering.

Re: [libstdc++,doc] Strip links to ANSI (web shop)

On 23/03/17 15:01 +, Jonathan Wakely wrote: On 18/03/17 19:44 +0100, Gerald Pfeifer wrote: On Wed, 15 Feb 2017, Jonathan Wakely wrote: The C++14 standard is: http://webstore.ansi.org/RecordDetail.aspx?sku=ISO%2fIEC+14882%3a2014 Thanks, Jonathan! What do you think? Should we make the FA

Re: [PATCH] Implement LWG 2686, hash

On 12/03/17 13:16 +0100, Daniel Krügler wrote: The following is an *untested* patch suggestion, please verify. Notes: My interpretation is that hash should be defined outside of the _GLIBCXX_COMPATIBILITY_CXX0X block, please double-check that course of action. That's right. I noticed that th

Re: [Patch] Inline Variables for the Standard Library (p0607r0)

On Thu, Mar 23, 2017 at 1:45 PM, Jonathan Wakely wrote: > + // NOTE: This makes use of the fact that we know how moveable > + // is implemented on pair, and also vector. If the implementation > + // changes this test may begin to fail. Maybe drop this comment?

Re: [Patch] Inline Variables for the Standard Library (p0607r0)

On 12/03/17 01:04 +0100, Daniel Krügler wrote: 2017-03-11 23:14 GMT+01:00 Daniel Krügler : 2017-03-11 23:09 GMT+01:00 Tim Song : On Sat, Mar 11, 2017 at 3:37 PM, Daniel Krügler wrote: 2017-03-11 21:23 GMT+01:00 Tim Song : On Sat, Mar 11, 2017 at 1:32 PM, Daniel Krügler wrote: This patch ap

Re: [testsuite] Add missing dg-require-effective-target alloca to gcc testsuite

On Mar 23, 2017, at 8:46 AM, Tom de Vries wrote: > > I've run the gcc testsuite for target nvptx-none and ran into "test for > excess errors" FAILs due to: > ... > sorry, unimplemented: target cannot support alloca. We'd encourage ports to support alloca. :-) > OK for trunk for stage1? Ok.

[PATCH,testsuite] Skip pic-3,4.c and pie-3,4.c for mips*-*-linux-*.

Hi, The pic-3,4.c and pie-3,4.c tests are failing for some configurations of mips*-*-linux-*. This is because PIC is always on for MIPS Linux by default, except when the compiler is built with --with-mips-plt, in which case PIC is on by default only for the n64 ABI, because in this case -mplt "ha

Re: [PATCH, GCC/testsuite/ARM, stage4] Compile atomic_loaddi_11 for Cortex-R5

My apologize, this works for both -march of -mcpu not cortex-r4 in RUNTESTFLAGS. ChangeLog entry is unchanged: *** gcc/testsuite/ChangeLog *** 2017-03-22 Thomas Preud'homme Sorry, I forgot about -march. Hold on. On 23/03/17 16:51, Thomas Preudhomme wrote: Please find attached an updated pa

Re: [PATCH 4/5] tree-inline: implement SIMT privatization, part 3

On Thu, Mar 23, 2017 at 08:00:11PM +0300, Alexander Monakov wrote: > On Thu, 23 Mar 2017, Jakub Jelinek wrote: > > And then clear it. That doesn't look like the right thing. > > > > So either you need some bool variable whether you've actually allocated > > the vector in the current expand_call_i

Re: [PATCH 4/5] tree-inline: implement SIMT privatization, part 3

On Thu, 23 Mar 2017, Jakub Jelinek wrote: > And then clear it. That doesn't look like the right thing. > > So either you need some bool variable whether you've actually allocated > the vector in the current expand_call_inline and use that instead of > if (id->dst_simt_vars), or maybe you should c

Re: [PATCH, GCC/testsuite/ARM, stage4] Compile atomic_loaddi_11 for Cortex-R5

Sorry, I forgot about -march. Hold on. On 23/03/17 16:51, Thomas Preudhomme wrote: Please find attached an updated patch. ChangeLog entry unchanged: *** gcc/testsuite/ChangeLog *** 2017-03-22 Thomas Preud'homme Mmmh I probably need to add a dg-skip-if in there. Will respin the patch. Best

Re: [PATCH, GCC/testsuite/ARM, stage4] Compile atomic_loaddi_11 for Cortex-R5

Please find attached an updated patch. ChangeLog entry unchanged: *** gcc/testsuite/ChangeLog *** 2017-03-22 Thomas Preud'homme Mmmh I probably need to add a dg-skip-if in there. Will respin the patch. Best regards, Thomas On 23/03/17 16:10, Richard Earnshaw (lists) wrote: On 23/03/17 16:

Re: [testsuite] Add missing dg-require-effective-target alloca to gcc testsuite

On 23/03/17 17:24, Thomas Schwinge wrote: Hi Tom! On Thu, 23 Mar 2017 16:46:19 +0100, Tom de Vries wrote: I've run the gcc testsuite for target nvptx-none and ran into "test for excess errors" FAILs due to: ... sorry, unimplemented: target cannot support alloca. ... This patch marks those tes

Re: [patch v2] Get rid of stack trampolines for nested functions (1/4)

On Sep 04 2016, Eric Botcazou wrote: > Index: calls.c > === > --- calls.c (revision 239944) > +++ calls.c (working copy) > @@ -183,17 +183,76 @@ static void restore_fixed_argument_area (rtx, rtx, > > rtx > prepare_call_addres

Re: [testsuite] Add missing dg-require-effective-target alloca to gcc testsuite

Hi Tom! On Thu, 23 Mar 2017 16:46:19 +0100, Tom de Vries wrote: > I've run the gcc testsuite for target nvptx-none and ran into "test for > excess errors" FAILs due to: > ... > sorry, unimplemented: target cannot support alloca. > ... > > This patch marks those testcases as requiring alloca. T

Re: [PATCH 4/5] tree-inline: implement SIMT privatization, part 3

On Thu, Mar 23, 2017 at 07:15:52PM +0300, Alexander Monakov wrote: > * tree-inline.h (struct copy_body_data): New field dst_simt_vars. > * tree-inline.c (expand_call_inline): Handle SIMT privatization. > (copy_decl_for_dup_finish): Ditto. > --- > gcc/tree-inline.c | 65 > +++

Re: [PATCH, GCC/testsuite/ARM, stage4] Compile atomic_loaddi_11 for Cortex-R5

Mmmh I probably need to add a dg-skip-if in there. Will respin the patch. Best regards, Thomas On 23/03/17 16:10, Richard Earnshaw (lists) wrote: On 23/03/17 16:02, Thomas Preudhomme wrote: Hi, gcc.target/arm/atomic_loaddi_11.c testcase contributed in r246365 does not test the changed code s

Re: [PATCH 4/5] tree-inline: implement SIMT privatization, part 3

On Thu, 23 Mar 2017, Jakub Jelinek wrote: > > Sorry for missing the IR stability issue. This code relies on dst_simt_vars > > being a set and thus having no duplicate entries (so the implicit lookup > > when > > adding an element is needed). > > > > However, I think I was overly cautious: lookin

Re: [PATCH, GCC/testsuite/ARM, stage4] Compile atomic_loaddi_11 for Cortex-R5

On 23/03/17 16:02, Thomas Preudhomme wrote: > Hi, > > gcc.target/arm/atomic_loaddi_11.c testcase contributed in r246365 does > not test the changed code since ARMv7-R does not have division > instructions in ARM state. This patch changes it to target Cortex-R5 > processor instead which does have d

Re: [PATCH, GCC/LTO, stage4, ping3] Fix PR69866: LTO with def for weak alias in regular object file

Ping? Best regards, Thomas On 16/03/17 14:05, Thomas Preudhomme wrote: Ping? Is this ok for stage4? Best regards, Thomas On 09/03/17 09:43, Thomas Preudhomme wrote: Ping? Best regards, Thomas On 02/03/17 14:51, Thomas Preudhomme wrote: Hi, This patch fixes an assert failure when link

[PATCH, GCC/testsuite/ARM, stage4] Compile atomic_loaddi_11 for Cortex-R5

Hi, gcc.target/arm/atomic_loaddi_11.c testcase contributed in r246365 does not test the changed code since ARMv7-R does not have division instructions in ARM state. This patch changes it to target Cortex-R5 processor instead which does have division instructions in ARM state. ChangeLog entry is

[testsuite] Add missing dg-require-effective-target alloca to gcc testsuite

Hi, I've run the gcc testsuite for target nvptx-none and ran into "test for excess errors" FAILs due to: ... sorry, unimplemented: target cannot support alloca. ... This patch marks those testcases as requiring alloca. OK for trunk for stage1? Thanks, - Tom 2017-03-23 Tom de Vries * gcc

Re: [PATCH] fwprop: Prevent infinite looping (PR79405)

On Thu, Mar 23, 2017 at 04:16:56PM +0100, Richard Biener wrote: > On Thu, Mar 23, 2017 at 3:58 PM, Segher Boessenkool > wrote: > > The algorithm fwprop uses never reconsiders a possible propagation, > > although it could succeed if the def (in the def-use to propagate) > > has changed. This cause

Re: [PATCH] fwprop: Prevent infinite looping (PR79405)

On Thu, Mar 23, 2017 at 3:58 PM, Segher Boessenkool wrote: > The algorithm fwprop uses never reconsiders a possible propagation, > although it could succeed if the def (in the def-use to propagate) > has changed. This causes fwprop to do infinite propagations, like > in the scenario in the PR, wh

Re: [libstdc++,doc] Strip links to ANSI (web shop)

On 18/03/17 19:44 +0100, Gerald Pfeifer wrote: On Wed, 15 Feb 2017, Jonathan Wakely wrote: The C++14 standard is: http://webstore.ansi.org/RecordDetail.aspx?sku=ISO%2fIEC+14882%3a2014 Thanks, Jonathan! What do you think? Should we make the FAQ link to the info in the manual, instead of just

[PATCH] fwprop: Prevent infinite looping (PR79405)

The algorithm fwprop uses never reconsiders a possible propagation, although it could succeed if the def (in the def-use to propagate) has changed. This causes fwprop to do infinite propagations, like in the scenario in the PR, where we end up with effectively B = A A = B D = A where only pr

[CHKP] Fix for PR79990

Hi, The patch below attempts to fix the PR. I checked that it did not break any of mpx.exp tests, but I did not run the full testing yet. Would like to know whether this approach is generally correct or not. The issue is that we have the hard reg vector variable: typedef int U __attribute__ ((ve

Re: [PR80025] avoid cselib rtx_equal infinite recursion on XOR

On Tue, Mar 21, 2017 at 07:43:51PM -0300, Alexandre Oliva wrote: > When two VALUEs are recorded in the cselib equivalence table such that > they are equivalent to each other XORed with the same expression, if > we started a cselib equivalence test between say the odd one and the > even one, we'd en

C/C++ PATCH to drop references to C_RID_YYCODE

C_RID_YYCODE was deleted a long time ago: 2003-02-18 Geoffrey Keating * cp-tree.h (rid_to_yy): Delete. (C_RID_YYCODE): Delete. (finish_file): Delete redundant declaration. so let's 86 the references to it. Applying to trunk. 2017-03-23 Marek Polacek * c-t

Re: [PATCH] Fix memory leak in identify_jump_threads()

On Thu, Mar 23, 2017 at 12:20 PM, Markus Trippelsdorf wrote: > Valgrind shows: > > ==553== 391,488 bytes in 24 blocks are possibly lost in loss record 4,339 of > 4,342 > ==553==at 0x4030C15: calloc (vg_replace_malloc.c:711) > ==553==by 0x1607CA0: xcalloc (xmalloc.c:162) > ==553==by 0x

Re: [PATCH 4/5] tree-inline: implement SIMT privatization, part 3

On Thu, Mar 23, 2017 at 02:13:45PM +0300, Alexander Monakov wrote: > On Thu, 23 Mar 2017, Jakub Jelinek wrote: > > On Wed, Mar 22, 2017 at 06:46:34PM +0300, Alexander Monakov wrote: > > > @@ -4730,6 +4746,25 @@ expand_call_inline (basic_block bb, gimple *stmt, > > > copy_body_data *id) > > >if

[PATCH] Fix memory leak in identify_jump_threads()

Valgrind shows: ==553== 391,488 bytes in 24 blocks are possibly lost in loss record 4,339 of 4,342 ==553==at 0x4030C15: calloc (vg_replace_malloc.c:711) ==553==by 0x1607CA0: xcalloc (xmalloc.c:162) ==553==by 0x1004A81: data_alloc (hash-table.h:263) ==553==by 0x1004A81: alloc_entri

Re: [PATCH 3/5] omp-offload: implement SIMT privatization, part 2

On Thu, Mar 23, 2017 at 01:53:37PM +0300, Alexander Monakov wrote: > On Thu, 23 Mar 2017, Jakub Jelinek wrote: > > > + if (vf != 1) > > > + continue; > > > + unlink_stmt_vdef (stmt); > > > > This is weird. AFAIK unlink_stmt_vdef just replaces the uses of the vdef > > of that stmt wi

Re: [PATCH 4/5] tree-inline: implement SIMT privatization, part 3

On Thu, 23 Mar 2017, Jakub Jelinek wrote: > On Wed, Mar 22, 2017 at 06:46:34PM +0300, Alexander Monakov wrote: > > @@ -4730,6 +4746,25 @@ expand_call_inline (basic_block bb, gimple *stmt, > > copy_body_data *id) > >if (cfun->gimple_df) > > pt_solution_reset (&cfun->gimple_df->escaped); >

Re: [PATCH 3/5] omp-offload: implement SIMT privatization, part 2

On Thu, 23 Mar 2017, Jakub Jelinek wrote: > > + if (vf != 1) > > + continue; > > + unlink_stmt_vdef (stmt); > > This is weird. AFAIK unlink_stmt_vdef just replaces the uses of the vdef > of that stmt with the vuse, but it still keeps the vdef (and vuse) around > on the stmt, t

Re: [PATCH 5/5] address-taken: optimize SIMT privatized variables

On Wed, Mar 22, 2017 at 06:46:35PM +0300, Alexander Monakov wrote: > This patch implements promotion of SIMT private variables if GOMP_SIMT_ENTER > is the only remaining statement where their address is taken, by handling it > similar to ASAN_MARK. > > To avoid rebuilding GOMP_SIMT_ENTER statement

Re: [wwwdocs] gcc-8/porting_to.html

Ack. Please find updated patch as per suggestions. Best regards, Thomas On 23/03/17 06:47, Gerald Pfeifer wrote: Hi Thomas, On Wed, 22 Mar 2017, Thomas Preudhomme wrote: Is this ok for wwwdocs once [1] is committed in GCC 8 cycle? + GCC on Microsoft Windows can now be configured via +

Re: [PATCH 4/5] tree-inline: implement SIMT privatization, part 3

On Wed, Mar 22, 2017 at 06:46:34PM +0300, Alexander Monakov wrote: > @@ -4730,6 +4746,25 @@ expand_call_inline (basic_block bb, gimple *stmt, > copy_body_data *id) >if (cfun->gimple_df) > pt_solution_reset (&cfun->gimple_df->escaped); > > + /* Add new automatic variables to IFN_GOMP_SI

Re: [PATCH 3/5] omp-offload: implement SIMT privatization, part 2

On Wed, Mar 22, 2017 at 06:46:33PM +0300, Alexander Monakov wrote: > @@ -1669,6 +1672,93 @@ make_pass_oacc_device_lower (gcc::context *ctxt) >return new pass_oacc_device_lower (ctxt); > } > > + > + I'd avoid the empty line after ^L. > @@ -1694,6 +1785,20 @@ execute_omp_device_lower () >

Re: [PATCH 2/5] omp-low: implement SIMT privatization, part 1

On Wed, Mar 22, 2017 at 06:46:32PM +0300, Alexander Monakov wrote: > This patch adjusts privatization in OpenMP SIMD loops lowered for SIMT > targets. > At lowering time, private variables receive "omp simt private" attribute, get > mentioned in argument list of GOMP_SIMT_ENTER function, and get a

Re: [PATCH v3] Fix PR79908 (and PR80136)

On Wed, Mar 22, 2017 at 4:43 PM, Bill Schmidt wrote: > Hi, > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79908 shows a case where > pass_stdarg ICEs attempting to gimplify a COMPLEX_EXPR with side > effects as an lvalue. This occurs when the LHS of a VA_ARG has been > cast away. The previous

RE: [wwwdocs] ARC's gcc7.x release notes

On Wed, 22 Mar 2017, Claudiu Zissulescu wrote: > That's great news, thank you Gerald for the quick review. I still have > one question, as I never worked with wwwdocs, do I need to perform extra > operations (like updating a ChangeLog kind of file) before committing my > patch to cvs trunk? No

Re: [PATCH][ARM] PR target/71436: Restrict *load_multiple pattern till after LRA

On 07/02/17 14:49, Kyrill Tkachov wrote: On 18/01/17 09:49, Kyrill Tkachov wrote: On 19/12/16 14:53, Jakub Jelinek wrote: On Thu, Dec 15, 2016 at 10:00:14AM +, Richard Earnshaw (lists) wrote: sorry, pasted the wrong bit of code. That should read when we generate: (insn 55 19 67 3 (para

[wwwdocs] Remove two company links

My link checker spotted some redirects, and so I noticed these two old links (2002 and 2000), and since we haven't had such in any later announcements (and generally avoid them), I applied the below. Of course we have, and will keep, deep links such as Nick's blog. Gerald Index: news/dfa.html ==