[gcc r15-132] docs: rtl: document GET_MODE_INNER

https://gcc.gnu.org/g:301b95494098024317c2f4603f759fadc8a868ca commit r15-132-g301b95494098024317c2f4603f759fadc8a868ca Author: Vineet Gupta Date: Thu Feb 17 13:49:45 2022 -0800 docs: rtl: document GET_MODE_INNER gcc/ChangeLog * doc/rtl.texi: Add entry for GET_MODE_INN

[gcc r15-133] RISC-V: miscll comment fixes [NFC]

https://gcc.gnu.org/g:467ca4a195e26dba77e7f62cc1a3d45a4e541c72 commit r15-133-g467ca4a195e26dba77e7f62cc1a3d45a4e541c72 Author: Vineet Gupta Date: Tue Mar 1 03:45:19 2022 -0800 RISC-V: miscll comment fixes [NFC] gcc/ChangeLog: * config/riscv/riscv.cc: Comment updates.

[gcc r15-492] RISC-V: avoid LUI based const materialization ... [part of PR/106265]

https://gcc.gnu.org/g:4bfc4585c9935fbde75ccf04e44a15d24f42cde9 commit r15-492-g4bfc4585c9935fbde75ccf04e44a15d24f42cde9 Author: Vineet Gupta Date: Mon May 13 11:45:55 2024 -0700 RISC-V: avoid LUI based const materialization ... [part of PR/106265] ... if the constant can be repres

[gcc r15-2236] RISC-V: Fix snafu in SI mode splitters patch

https://gcc.gnu.org/g:806927111cf388a2d8cd54072269601f677767cf commit r15-2236-g806927111cf388a2d8cd54072269601f677767cf Author: Vineet Gupta Date: Tue Jul 23 15:12:11 2024 -0700 RISC-V: Fix snafu in SI mode splitters patch SPEC2017 perlbench for RISC-V was broke as runtime output

[gcc r14-9711] RISC-V: testsuite: ensure vtype is call clobbered

https://gcc.gnu.org/g:c1424628dc95829408882f01cbf0dd61566dc312 commit r14-9711-gc1424628dc95829408882f01cbf0dd61566dc312 Author: Vineet Gupta Date: Wed Mar 27 14:55:04 2024 -0700 RISC-V: testsuite: ensure vtype is call clobbered Per classic Vector calling convention ABI, vtype is

[gcc r15-2941] RISC-V: use fclass insns to implement isfinite, isnormal and isinf builtins

https://gcc.gnu.org/g:b0d041f0d4cace06433bf18ae53c40376f2088a7 commit r15-2941-gb0d041f0d4cace06433bf18ae53c40376f2088a7 Author: Vineet Gupta Date: Thu Aug 15 09:24:27 2024 -0700 RISC-V: use fclass insns to implement isfinite,isnormal and isinf builtins Currently these builtins us

[gcc r15-757] RISC-V: avoid LUI based const mat in prologue/epilogue expansion [PR/105733]

https://gcc.gnu.org/g:f9cfc192ed0127edb7e79818917dd2859fce4d44 commit r15-757-gf9cfc192ed0127edb7e79818917dd2859fce4d44 Author: Vineet Gupta Date: Mon May 13 11:46:03 2024 -0700 RISC-V: avoid LUI based const mat in prologue/epilogue expansion [PR/105733] If the constant used for s

[gcc r15-758] RISC-V: avoid LUI based const mat in alloca epilogue expansion

https://gcc.gnu.org/g:9926c40a902edbc665919d508ef0c36f362f9c41 commit r15-758-g9926c40a902edbc665919d508ef0c36f362f9c41 Author: Vineet Gupta Date: Wed Mar 6 15:44:27 2024 -0800 RISC-V: avoid LUI based const mat in alloca epilogue expansion This is continuing on the prev patch in f

[gcc r15-4808] RISC-V: fix const interleaved stepped vector with a scalar pattern

https://gcc.gnu.org/g:1905b59fdc58ce67e508b99dff105afebaaa9bb1 commit r15-4808-g1905b59fdc58ce67e508b99dff105afebaaa9bb1 Author: Vineet Gupta Date: Thu Oct 24 15:15:40 2024 -0700 RISC-V: fix const interleaved stepped vector with a scalar pattern When bisecting for ICE in PR/117353

[gcc r15-5925] sched1: parameterize pressure scheduling spilling aggressiveness [PR/114729]

https://gcc.gnu.org/g:7bef3482f27ce13ba7e6c4f43943f28a49e63a40 commit r15-5925-g7bef3482f27ce13ba7e6c4f43943f28a49e63a40 Author: Vineet Gupta Date: Wed Dec 4 10:42:37 2024 -0800 sched1: parameterize pressure scheduling spilling aggressiveness [PR/114729] sched1 computes ECC (Exces

[gcc r15-5926] sched1: debug/model: dump predecessor list and BB num [NFC]

https://gcc.gnu.org/g:5598aa81c937be031dc856a38c250b256953f988 commit r15-5926-g5598aa81c937be031dc856a38c250b256953f988 Author: Vineet Gupta Date: Wed Dec 4 10:49:33 2024 -0800 sched1: debug/model: dump predecessor list and BB num [NFC] This is broken out of predecessor promotion

[gcc r15-6673] RISC-V: vector absolute difference expander [PR117722]

https://gcc.gnu.org/g:b755c151fde4ad736405bb2e13a7de0420161179 commit r15-6673-gb755c151fde4ad736405bb2e13a7de0420161179 Author: Vineet Gupta Date: Tue Jan 7 14:28:25 2025 -0800 RISC-V: vector absolute difference expander [PR117722] This improves codegen for x264 sum of absolute d

[gcc r15-7239] RISC-V: Add another test for FRM elimination bug [PR118646]

https://gcc.gnu.org/g:019fe9c4d4c7cc9e325b5460d277ebaec108a838 commit r15-7239-g019fe9c4d4c7cc9e325b5460d277ebaec108a838 Author: Vineet Gupta Date: Fri Jan 24 13:56:28 2025 -0800 RISC-V: Add another test for FRM elimination bug [PR118646] The issue is same as PR118103 and fixed by

[gcc r15-6872] RISC-V: fix thinko in riscv_register_move_cost ()

https://gcc.gnu.org/g:7102620067eebfbfb895dccd5ddd26870178c83f commit r15-6872-g7102620067eebfbfb895dccd5ddd26870178c83f Author: Vineet Gupta Date: Sat Jan 11 11:13:19 2025 -0800 RISC-V: fix thinko in riscv_register_move_cost () This seeming benign mistake caused a massive SPEC201

[gcc r15-7490] RISC-V: Vector pesudoinsns with x0 operand to use imm 0

https://gcc.gnu.org/g:3880271e94b7598b4f5d98c615b7fcee6d4c commit r15-7490-g3880271e94b7598b4f5d98c615b7fcee6d4c Author: Vineet Gupta Date: Wed Feb 5 16:46:48 2025 +0530 RISC-V: Vector pesudoinsns with x0 operand to use imm 0 A couple of Vector pseudoinstructions use x0 sc

[gcc r15-9492] RISC-V: vsetvl: elide abnormal edges from LCM computations [PR119533]

https://gcc.gnu.org/g:edb4867412895100b3addc525bc0dba0ea90c7f9 commit r15-9492-gedb4867412895100b3addc525bc0dba0ea90c7f9 Author: Vineet Gupta Date: Tue Apr 15 09:29:08 2025 -0700 RISC-V: vsetvl: elide abnormal edges from LCM computations [PR119533] vsetvl phase4 uses LCM guided in

[gcc r15-8895] RISC-V: disable the abd expander for gcc-15 release [PR119224]

https://gcc.gnu.org/g:cb6070c79dd9334e7cfff40bacd21da4f337cc33 commit r15-8895-gcb6070c79dd9334e7cfff40bacd21da4f337cc33 Author: Vineet Gupta Date: Mon Mar 24 10:36:52 2025 -0700 RISC-V: disable the abd expander for gcc-15 release [PR119224] It seems the new expander triggers a la