[gcc r15-3697] RISC-V: Fix signed SAT_ADD test case for int64_t

https://gcc.gnu.org/g:1d1687513400c1b805bf5924f732c21dbf166ae8 commit r15-3697-g1d1687513400c1b805bf5924f732c21dbf166ae8 Author: Pan Li Date: Fri Sep 13 09:16:48 2024 +0800 RISC-V: Fix signed SAT_ADD test case for int64_t The int8_t test for signed SAT_ADD is sat_s_add-1.c, the sa

[gcc r15-3694] c++: alias of decltype(lambda) is opaque [PR116714, PR107390]

https://gcc.gnu.org/g:82c2acd0bc4411524a8248fcdce219927d921a71 commit r15-3694-g82c2acd0bc4411524a8248fcdce219927d921a71 Author: Patrick Palka Date: Wed Sep 18 13:50:43 2024 -0400 c++: alias of decltype(lambda) is opaque [PR116714, PR107390] Here for using type = declty

[gcc r15-3695] [PATCH] configure: fix typos

https://gcc.gnu.org/g:cc62b2c3da118f08f71d2ae9c08bafb55b35767a commit r15-3695-gcc62b2c3da118f08f71d2ae9c08bafb55b35767a Author: Andrew Kreimer Date: Wed Sep 18 11:50:58 2024 -0600 [PATCH] configure: fix typos / * configure.ac: Fix typos. * configure: Rebui

[gcc r15-3699] testsuite/gcc.dg/pr84877.c: Add machinery to stabilize stack aligmnent

https://gcc.gnu.org/g:b1ea710b1bcdda233f96538c5404228d2b244e01 commit r15-3699-gb1ea710b1bcdda233f96538c5404228d2b244e01 Author: Hans-Peter Nilsson Date: Thu Sep 5 17:02:23 2024 +0200 testsuite/gcc.dg/pr84877.c: Add machinery to stabilize stack aligmnent This test awkwardly "blink

[gcc r15-3690] contrib: Set check-params-in-docs.py to skip tables of values of a param

https://gcc.gnu.org/g:4b7e6d5faa137f18a36d8c6323a8640e61ee48f1 commit r15-3690-g4b7e6d5faa137f18a36d8c6323a8640e61ee48f1 Author: Filip Kastl Date: Wed Sep 18 16:38:30 2024 +0200 contrib: Set check-params-in-docs.py to skip tables of values of a param Currently check-params-in-docs

[gcc r15-3691] [PATCH v3] RISC-V: Fixed incorrect semantic description in DF to DI pattern in the Zfa extension on

https://gcc.gnu.org/g:85fcf740342e308da4776a45a4cd726987725a6a commit r15-3691-g85fcf740342e308da4776a45a4cd726987725a6a Author: Jin Ma Date: Wed Sep 18 08:56:23 2024 -0600 [PATCH v3] RISC-V: Fixed incorrect semantic description in DF to DI pattern in the Zfa extension on rv32. g

[gcc r15-3680] tree-optimization/116585 - SSA corruption with split_constant_offset

https://gcc.gnu.org/g:1d0cb3b5fca69b81e69cfdb4aea0eebc1ac04750 commit r15-3680-g1d0cb3b5fca69b81e69cfdb4aea0eebc1ac04750 Author: Richard Biener Date: Wed Sep 18 09:52:55 2024 +0200 tree-optimization/116585 - SSA corruption with split_constant_offset split_constant_offset when look

[gcc r15-3687] [PATCH] RISC-V: Fix th.extu operands exceeding range on rv32.

https://gcc.gnu.org/g:ec34a4481b63bb5028b2a8c61322a7a3d362b27c commit r15-3687-gec34a4481b63bb5028b2a8c61322a7a3d362b27c Author: Xianmiao Qu Date: Wed Sep 18 07:28:44 2024 -0600 [PATCH] RISC-V: Fix th.extu operands exceeding range on rv32. The Combine Pass may generate zero_extrac

[gcc r15-3688] [PATCH 1/2] RISC-V: Fix the outer_code when calculating the cost of SET expression.

https://gcc.gnu.org/g:ad5bfc2b7044ba962396de0dabcad1cd54234689 commit r15-3688-gad5bfc2b7044ba962396de0dabcad1cd54234689 Author: Xianmiao Qu Date: Wed Sep 18 07:35:12 2024 -0600 [PATCH 1/2] RISC-V: Fix the outer_code when calculating the cost of SET expression. I think it is a ty

[gcc r15-3689] Fail vectorization when not using SLP and --param vect-force-slp == 1

https://gcc.gnu.org/g:de1389e24e8dc98b65bc8d40976172214ac4ecc0 commit r15-3689-gde1389e24e8dc98b65bc8d40976172214ac4ecc0 Author: Richard Biener Date: Sun Sep 8 11:21:19 2024 +0200 Fail vectorization when not using SLP and --param vect-force-slp == 1 The following adds --param vect

[gcc r15-3692] hppa: Add peephole2 optimizations for REG+D loads and stores

https://gcc.gnu.org/g:4b03750f8cda0a8745b10639a8ac7df71aced0cc commit r15-3692-g4b03750f8cda0a8745b10639a8ac7df71aced0cc Author: John David Anglin Date: Wed Sep 18 11:02:32 2024 -0400 hppa: Add peephole2 optimizations for REG+D loads and stores The PA 1.x architecture only support

[gcc r15-3693] jit: Ensure ssize_t is defined

https://gcc.gnu.org/g:fe1ed68000d5e9d41ed48ef1202fd21c8b8c9ff8 commit r15-3693-gfe1ed68000d5e9d41ed48ef1202fd21c8b8c9ff8 Author: Francois-Xavier Coudert Date: Sat May 11 17:08:05 2024 +0200 jit: Ensure ssize_t is defined On some targets it seems that ssize_t is not defined by any

[gcc r14-10679] tree-optimization/116258 - fix i386 testcase

https://gcc.gnu.org/g:198b13e248e7adfea2d28c4e66ac9f5006b8f825 commit r14-10679-g198b13e248e7adfea2d28c4e66ac9f5006b8f825 Author: Richard Biener Date: Thu Aug 8 09:35:42 2024 +0200 tree-optimization/116258 - fix i386 testcase With -march=cascadelake we use vpermilps instead of shu

[gcc r14-10680] aarch64/testsuite: Add testcases for recently fixed PRs

https://gcc.gnu.org/g:090926ba817bee6de7ee210efeea5d43d5335868 commit r14-10680-g090926ba817bee6de7ee210efeea5d43d5335868 Author: Andrew Pinski Date: Wed Aug 7 09:36:38 2024 -0700 aarch64/testsuite: Add testcases for recently fixed PRs The commit for PR 116258, added a x86_64 spec

[gcc r14-10677] middle-end/115641 - invalid address construction

https://gcc.gnu.org/g:98dc0471d5409701ae700cd7aba8716fdc500401 commit r14-10677-g98dc0471d5409701ae700cd7aba8716fdc500401 Author: Richard Biener Date: Thu Jul 18 13:35:33 2024 +0200 middle-end/115641 - invalid address construction fold_truth_andor_1 via make_bit_field_ref builds a

[gcc r14-10678] tree-optimization/116258 - do not lower PAREN_EXPR of vectors

https://gcc.gnu.org/g:05db1bea8c1d61d8d9cdb8ede5e305766869d136 commit r14-10678-g05db1bea8c1d61d8d9cdb8ede5e305766869d136 Author: Richard Biener Date: Wed Aug 7 13:54:53 2024 +0200 tree-optimization/116258 - do not lower PAREN_EXPR of vectors The following avoids lowering of PAREN

[gcc r14-10683] fold: Fix `a * 1j` if a has side effects [PR116454]

https://gcc.gnu.org/g:12c00048d9f3598e57b98ec7723f7356bd255d04 commit r14-10683-g12c00048d9f3598e57b98ec7723f7356bd255d04 Author: Andrew Pinski Date: Wed Aug 21 17:41:38 2024 -0700 fold: Fix `a * 1j` if a has side effects [PR116454] The problem here was a missing save_expr around

[gcc r14-10681] tree-optimization/116274 - overzealous SLP vectorization

https://gcc.gnu.org/g:d5d4f3bae5a9478dc2189e53da933175a6d7b197 commit r14-10681-gd5d4f3bae5a9478dc2189e53da933175a6d7b197 Author: Richard Biener Date: Thu Aug 8 11:36:43 2024 +0200 tree-optimization/116274 - overzealous SLP vectorization The following tries to address that the vec

[gcc r14-10682] tree-optimization/116380 - bogus SSA update with loop distribution

https://gcc.gnu.org/g:8f8a7e1f1904e389e736c0265b4f515f3ce13659 commit r14-10682-g8f8a7e1f1904e389e736c0265b4f515f3ce13659 Author: Richard Biener Date: Wed Aug 21 13:56:40 2024 +0200 tree-optimization/116380 - bogus SSA update with loop distribution When updating LC PHIs after copy

[gcc r14-10684] tree-optimization/116610 - wrong SLP induction bias for mask peeling

https://gcc.gnu.org/g:cacc976a71027e7da8e3438b60da76ecdf990d38 commit r14-10684-gcacc976a71027e7da8e3438b60da76ecdf990d38 Author: Richard Biener Date: Thu Sep 5 11:18:57 2024 +0200 tree-optimization/116610 - wrong SLP induction bias for mask peeling The following fixes a mistake w

[gcc r14-10685] middle-end/115426 - wrong gimplification of "rm" asm output operand

https://gcc.gnu.org/g:5b264a4b95b8f27c3c73892892d5c2030d3c8ea7 commit r14-10685-g5b264a4b95b8f27c3c73892892d5c2030d3c8ea7 Author: Richard Biener Date: Tue Jun 11 13:11:08 2024 +0200 middle-end/115426 - wrong gimplification of "rm" asm output operand When the operand is gimplified

[gcc r14-10686] Fix vect/pr115278.cc for targets where uint32_t is distinct from unsigned.

https://gcc.gnu.org/g:a308afb455d648d54430355cb07345a338501348 commit r14-10686-ga308afb455d648d54430355cb07345a338501348 Author: Joern Rennecke Date: Wed Aug 7 02:48:45 2024 +0100 Fix vect/pr115278.cc for targets where uint32_t is distinct from unsigned. gcc/testsuite/

[gcc r13-9044] doc: Add more alias option and reorder Intel CPU -march documentation

https://gcc.gnu.org/g:de1d625849a7760da5d5a3a08601d8ac890c6100 commit r13-9044-gde1d625849a7760da5d5a3a08601d8ac890c6100 Author: Haochen Jiang Date: Wed Sep 18 11:20:15 2024 +0800 doc: Add more alias option and reorder Intel CPU -march documentation This patch is backported from G

[gcc(refs/users/aoliva/heads/testme)] fold truth-and only in ifcombine

https://gcc.gnu.org/g:15a55a94711d51d95fb6b5ba763903d75e85324e commit 15a55a94711d51d95fb6b5ba763903d75e85324e Author: Alexandre Oliva Date: Tue Sep 17 20:15:35 2024 -0300 fold truth-and only in ifcombine Diff: --- gcc/gimple-fold.cc| 2 ++ gcc/tree-ssa-ifcombine.cc | 24 +++

[gcc r15-3683] match.pd: Check trunc_mod vector obtap before folding.

https://gcc.gnu.org/g:6f3b6a451771cd54c98768e7db3c5d58aab2b6aa commit r15-3683-g6f3b6a451771cd54c98768e7db3c5d58aab2b6aa Author: Jennifer Schmitz Date: Thu Sep 5 08:10:02 2024 -0700 match.pd: Check trunc_mod vector obtap before folding. In the pattern X - (X / Y) * Y to X % Y, thi

[gcc r15-3685] c++: -Wdangling-reference diagnostic

https://gcc.gnu.org/g:5c8f9f4d4cebabf85e68c5bdbe2d4ee6646edc7c commit r15-3685-g5c8f9f4d4cebabf85e68c5bdbe2d4ee6646edc7c Author: Jason Merrill Date: Mon Sep 16 13:29:05 2024 +0200 c++: -Wdangling-reference diagnostic The -Wdangling-reference diagnostic talks about the full-express

[gcc r15-3684] c++: -Wdangling-reference and empty class [PR115361]

https://gcc.gnu.org/g:8733d5d3873977d6ca82d71b28728650f988e9c8 commit r15-3684-g8733d5d3873977d6ca82d71b28728650f988e9c8 Author: Jason Merrill Date: Sun Sep 15 13:50:04 2024 +0200 c++: -Wdangling-reference and empty class [PR115361] We can't have a dangling reference to an empty c

[gcc r13-9033] tree-optimization/115197 - fix ICE w/ constant in LC PHI and loop distribution

https://gcc.gnu.org/g:062168c8bd4dbca659a5c6cc581f40e409f7d2ad commit r13-9033-g062168c8bd4dbca659a5c6cc581f40e409f7d2ad Author: Richard Biener Date: Thu May 23 14:36:39 2024 +0200 tree-optimization/115197 - fix ICE w/ constant in LC PHI and loop distribution Forgot a check for a

[gcc r13-9034] tree-optimization/115278 - fix DSE in if-conversion wrt volatiles

https://gcc.gnu.org/g:22c9080c88cd133e048cd9dcacd2fa13d8fd267f commit r13-9034-g22c9080c88cd133e048cd9dcacd2fa13d8fd267f Author: Richard Biener Date: Fri May 31 10:14:25 2024 +0200 tree-optimization/115278 - fix DSE in if-conversion wrt volatiles The following adds the missing gua

[gcc r13-9035] Fix vect/pr115278.cc for targets where uint32_t is distinct from unsigned.

https://gcc.gnu.org/g:c4525852c20f10c2027dd8aa4ed9f28df1a9a4be commit r13-9035-gc4525852c20f10c2027dd8aa4ed9f28df1a9a4be Author: Joern Rennecke Date: Wed Aug 7 02:48:45 2024 +0100 Fix vect/pr115278.cc for targets where uint32_t is distinct from unsigned. gcc/testsuite/

[gcc r13-9037] tree-optimization/115669 - fix SLP reduction association

https://gcc.gnu.org/g:e630a20d8367eb2e1929edcaaa03ffe2951b0851 commit r13-9037-ge630a20d8367eb2e1929edcaaa03ffe2951b0851 Author: Richard Biener Date: Thu Jun 27 11:26:08 2024 +0200 tree-optimization/115669 - fix SLP reduction association The following avoids associating a reductio

[gcc r13-9036] tree-optimization/115646 - ICE with pow shrink-wrapping from bitfield

https://gcc.gnu.org/g:120f25440da533b4c16268a21feb1d864bb1a843 commit r13-9036-g120f25440da533b4c16268a21feb1d864bb1a843 Author: Richard Biener Date: Tue Jun 25 16:13:02 2024 +0200 tree-optimization/115646 - ICE with pow shrink-wrapping from bitfield The following makes analysis a

[gcc r13-9039] tree-optimization/115701 - factor out maybe_duplicate_ssa_info_at_copy

https://gcc.gnu.org/g:0dee54fabeb1d7bdf74cdeee080c7e5201008d6e commit r13-9039-g0dee54fabeb1d7bdf74cdeee080c7e5201008d6e Author: Richard Biener Date: Sun Jun 30 11:28:11 2024 +0200 tree-optimization/115701 - factor out maybe_duplicate_ssa_info_at_copy The following factors out the

[gcc r13-9040] tree-optimization/115701 - fix maybe_duplicate_ssa_info_at_copy

https://gcc.gnu.org/g:29c236c57f272944b1f9fffbe248689fb86e91f4 commit r13-9040-g29c236c57f272944b1f9fffbe248689fb86e91f4 Author: Richard Biener Date: Sun Jun 30 11:34:43 2024 +0200 tree-optimization/115701 - fix maybe_duplicate_ssa_info_at_copy The following restricts copying of p

[gcc r13-9041] tree-optimization/115841 - reduction epilogue placement issue

https://gcc.gnu.org/g:e87c0c7f7ab1e7acd0ffbac0b15e020275f97ca8 commit r13-9041-ge87c0c7f7ab1e7acd0ffbac0b15e020275f97ca8 Author: Richard Biener Date: Tue Jul 16 11:53:17 2024 +0200 tree-optimization/115841 - reduction epilogue placement issue When emitting the compensation to the

[gcc r13-9038] tree-optimization/115694 - ICE with complex store rewrite

https://gcc.gnu.org/g:07c12b394dfb424404019b745b5e4a9e938f6693 commit r13-9038-g07c12b394dfb424404019b745b5e4a9e938f6693 Author: Richard Biener Date: Sun Jun 30 13:07:14 2024 +0200 tree-optimization/115694 - ICE with complex store rewrite The following adds a missed check when for

[gcc r13-9042] tree-optimization/116057 - wrong code with CCP and vector CTORs

https://gcc.gnu.org/g:ef25f1dd600cc9351c80e3e018d7170e16a2c6ff commit r13-9042-gef25f1dd600cc9351c80e3e018d7170e16a2c6ff Author: Richard Biener Date: Wed Jul 24 13:16:35 2024 +0200 tree-optimization/116057 - wrong code with CCP and vector CTORs The following fixes an issue with CC

[gcc r15-3682] reload1.cc: rtl-optimization/116326 - Use RELOAD_ELIMINABLE_REGS.

https://gcc.gnu.org/g:5bfb91c14f98f6750281217f737b3d95c4e73584 commit r15-3682-g5bfb91c14f98f6750281217f737b3d95c4e73584 Author: Georg-Johann Lay Date: Fri Sep 6 11:23:06 2024 +0200 reload1.cc: rtl-optimization/116326 - Use RELOAD_ELIMINABLE_REGS. The new macro is required because

[gcc r12-10716] doc: Add more alias option and reorder Intel CPU -march documentation

https://gcc.gnu.org/g:8483527158024d200b3a9e4edecbe188fa22fdaa commit r12-10716-g8483527158024d200b3a9e4edecbe188fa22fdaa Author: Haochen Jiang Date: Wed Sep 18 11:20:15 2024 +0800 doc: Add more alias option and reorder Intel CPU -march documentation This patch is backported from

[gcc r15-3700] i386: Add missing avx512f-mask-type.h include

https://gcc.gnu.org/g:2b7b8d3bb52a23aa8b1d6e9a2d57c83db2078f73 commit r15-3700-g2b7b8d3bb52a23aa8b1d6e9a2d57c83db2078f73 Author: Haochen Jiang Date: Sat Sep 14 15:55:53 2024 +0800 i386: Add missing avx512f-mask-type.h include Since commit r15-3594, we fixed the bugs in MASK_TYPE f

[gcc r15-3701] i386: Enhance AVX10.2 convert tests

https://gcc.gnu.org/g:89e62d42f366cd835022f0ba00ba1d10305ae0ce commit r15-3701-g89e62d42f366cd835022f0ba00ba1d10305ae0ce Author: Haochen Jiang Date: Thu Sep 5 11:27:33 2024 +0800 i386: Enhance AVX10.2 convert tests For AVX10.2 convert tests, all of them are missing mask tests

[gcc r15-3681] AVR: doc/install.texi - Update avr specific installation notes.

https://gcc.gnu.org/g:cdeebc71c48db922b14d34c361e15660c1e31fc1 commit r15-3681-gcdeebc71c48db922b14d34c361e15660c1e31fc1 Author: Georg-Johann Lay Date: Tue Sep 17 11:26:19 2024 +0200 AVR: doc/install.texi - Update avr specific installation notes. gcc/ * doc/install.tex

[gcc r15-3686] [PATCH] RISC-V: Allow zero operand for DI variants of vssubu.vx

https://gcc.gnu.org/g:0756f335fb6e455641850a76e68f892f1f82ada2 commit r15-3686-g0756f335fb6e455641850a76e68f892f1f82ada2 Author: Bohan Lei Date: Wed Sep 18 07:20:23 2024 -0600 [PATCH] RISC-V: Allow zero operand for DI variants of vssubu.vx The RISC-V vector machine description rel

[gcc r14-10687] tree-optimization/116460 - ICE with DCE in forwprop

https://gcc.gnu.org/g:bdc5937df68a197032e800fc27361037d016cbf1 commit r14-10687-gbdc5937df68a197032e800fc27361037d016cbf1 Author: Richard Biener Date: Mon Aug 26 13:50:00 2024 +0200 tree-optimization/116460 - ICE with DCE in forwprop The following avoids removing stmts with defs t

[gcc r15-3696] libstdc++: add braces

https://gcc.gnu.org/g:aa338bdd46a4946e9d5ac0923ce9bf9bc621c852 commit r15-3696-gaa338bdd46a4946e9d5ac0923ce9bf9bc621c852 Author: Jason Merrill Date: Sun Sep 15 11:48:46 2024 +0200 libstdc++: add braces GCC compiles with -fno-exceptions, so __throw_exception_again is a no-op, a

[gcc r15-3702] doc: Add more alias option and reorder Intel CPU -march documentation

https://gcc.gnu.org/g:877fb9bdb06d18df51c6043f74dde66fe6f46b78 commit r15-3702-g877fb9bdb06d18df51c6043f74dde66fe6f46b78 Author: Haochen Jiang Date: Wed Sep 18 11:20:15 2024 +0800 doc: Add more alias option and reorder Intel CPU -march documentation Since r15-3539, there are reque

[gcc r15-3704] i386: Add ssemov2, sseicvt2 for some load instructions that use memory on operand2

https://gcc.gnu.org/g:1cf1bf7899985df31e1ebccb5d6f1ca762991dcf commit r15-3704-g1cf1bf7899985df31e1ebccb5d6f1ca762991dcf Author: Hu, Lin1 Date: Wed Sep 11 10:10:40 2024 +0800 i386: Add ssemov2, sseicvt2 for some load instructions that use memory on operand2 The memory attr of som

[gcc(refs/users/aoliva/heads/testme)] rework truth_andor folding into tree-ssa-ifcombine

https://gcc.gnu.org/g:d041471d649c47763535d673ad689654d3630223 commit d041471d649c47763535d673ad689654d3630223 Author: Alexandre Oliva Date: Tue Sep 17 20:15:22 2024 -0300 rework truth_andor folding into tree-ssa-ifcombine Diff: --- gcc/fold-const.cc | 1048 +-

[gcc(refs/users/aoliva/heads/testme)] check for mergeable loads, choose insertion points accordingly

https://gcc.gnu.org/g:6ce741d00f03f73e1fb3e797e85707aef9cfd832 commit 6ce741d00f03f73e1fb3e797e85707aef9cfd832 Author: Alexandre Oliva Date: Tue Sep 17 20:15:28 2024 -0300 check for mergeable loads, choose insertion points accordingly Diff: --- gcc/gimple-fold.cc | 253 ++

[gcc/aoliva/heads/testme] (46 commits) support noncontiguous ifcombine

The branch 'aoliva/heads/testme' was updated to point to: a29037a8f9c7... support noncontiguous ifcombine It previously pointed to: 8a7e9581280c... support noncontiguous ifcombine Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST): --

[gcc/aoliva/heads/testbase] (38 commits) c++: fix constexpr cast from void* diag issue [PR116741]

The branch 'aoliva/heads/testbase' was updated to point to: d6d8445c8550... c++: fix constexpr cast from void* diag issue [PR116741] It previously pointed to: b56bd542942b... testsuite: a few more hostedlib adjustments Diff: Summary of changes (added commits): ---

[gcc(refs/users/aoliva/heads/testme)] relax ifcombine to accept vuses

https://gcc.gnu.org/g:575a4da1213668119e0e60326a7b18f7c1a342d6 commit 575a4da1213668119e0e60326a7b18f7c1a342d6 Author: Alexandre Oliva Date: Tue Sep 17 20:15:46 2024 -0300 relax ifcombine to accept vuses Diff: --- gcc/config/i386/t-i386 | 2 ++ gcc/testsuite/gcc.dg/field-m

[gcc(refs/users/aoliva/heads/testme)] support noncontiguous ifcombine

https://gcc.gnu.org/g:a29037a8f9c752e41a906f0eac66ff3792e98bcc commit a29037a8f9c752e41a906f0eac66ff3792e98bcc Author: Alexandre Oliva Date: Tue Sep 17 20:15:55 2024 -0300 support noncontiguous ifcombine Diff: --- gcc/tree-ssa-ifcombine.cc | 33 ++--- 1 file c

[gcc(refs/users/aoliva/heads/testme)] refactor ifcombine

https://gcc.gnu.org/g:3ed1ed8f0533f3f3f4372a2280c4e1c29304cd78 commit 3ed1ed8f0533f3f3f4372a2280c4e1c29304cd78 Author: Alexandre Oliva Date: Thu Sep 19 02:43:51 2024 -0300 refactor ifcombine Diff: --- gcc/tree-ssa-ifcombine.cc | 181 +++--- 1 file

[gcc(refs/users/aoliva/heads/testme)] support noncontiguous ifcombine

https://gcc.gnu.org/g:b0b68cbc1ed13ee0c61e0e2d768d997e8a1dfaa8 commit b0b68cbc1ed13ee0c61e0e2d768d997e8a1dfaa8 Author: Alexandre Oliva Date: Tue Sep 17 20:15:50 2024 -0300 support noncontiguous ifcombine Diff: --- gcc/tree-ssa-ifcombine.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 d