[gcc r15-3358] i386: Support vectorized BF16 sqrt with AVX10.2 instruction

https://gcc.gnu.org/g:e19f65b0be1e91ff86689feb7695080dad4c9197 commit r15-3358-ge19f65b0be1e91ff86689feb7695080dad4c9197 Author: Levy Hsu Date: Mon Sep 2 10:24:48 2024 +0800 i386: Support vectorized BF16 sqrt with AVX10.2 instruction gcc/ChangeLog: * config/i386/s

[gcc r15-3348] RISC-V: Add testcases for form 3 of unsigned vector .SAT_ADD IMM

https://gcc.gnu.org/g:72f3e9021e55f14e90773cf2966805a318f44842 commit r15-3348-g72f3e9021e55f14e90773cf2966805a318f44842 Author: Pan Li Date: Fri Aug 30 08:36:45 2024 +0800 RISC-V: Add testcases for form 3 of unsigned vector .SAT_ADD IMM This patch would like to add test cases for

[gcc r15-3360] [committed][PR rtl-optimization/116544] Fix test for promoted subregs

https://gcc.gnu.org/g:0562976d62e095f3a00c799288dee4e5b20114e2 commit r15-3360-g0562976d62e095f3a00c799288dee4e5b20114e2 Author: Jeff Law Date: Sun Sep 1 22:16:04 2024 -0600 [committed][PR rtl-optimization/116544] Fix test for promoted subregs This is a small bug in the ext-dce co

[gcc r15-3349] RISC-V: Add testcases for form 4 of unsigned vector .SAT_ADD IMM

https://gcc.gnu.org/g:56ed1dfa79c436b769f3266258d34d160b4330d9 commit r15-3349-g56ed1dfa79c436b769f3266258d34d160b4330d9 Author: Pan Li Date: Fri Aug 30 11:01:37 2024 +0800 RISC-V: Add testcases for form 4 of unsigned vector .SAT_ADD IMM This patch would like to add test cases for

[gcc r15-3347] RISC-V: Refactor gen zero_extend rtx for SAT_* when expand SImode in RV64

https://gcc.gnu.org/g:e96d4bf6a6e8b8a5ea1b81a79f4efa07dee77af1 commit r15-3347-ge96d4bf6a6e8b8a5ea1b81a79f4efa07dee77af1 Author: Pan Li Date: Fri Aug 30 14:07:12 2024 +0800 RISC-V: Refactor gen zero_extend rtx for SAT_* when expand SImode in RV64 In previous, we have some speciall

[gcc r15-3359] i386: Support vec_cmp for V8BF/V16BF/V32BF in AVX10.2

https://gcc.gnu.org/g:f77435aa3911c437cba71991509eee57b333b3ce commit r15-3359-gf77435aa3911c437cba71991509eee57b333b3ce Author: Levy Hsu Date: Mon Sep 2 10:24:49 2024 +0800 i386: Support vec_cmp for V8BF/V16BF/V32BF in AVX10.2 gcc/ChangeLog: * config/i386/i386-ex

[gcc r15-3356] i386: Support vectorized BF16 FMA with AVX10.2 instructions

https://gcc.gnu.org/g:6d294fb8ac9baf2624446deaa4c995b7a7719823 commit r15-3356-g6d294fb8ac9baf2624446deaa4c995b7a7719823 Author: Levy Hsu Date: Mon Sep 2 10:24:46 2024 +0800 i386: Support vectorized BF16 FMA with AVX10.2 instructions gcc/ChangeLog: * config/i386/s

[gcc r14-10625] Check avx upper register for parallel.

https://gcc.gnu.org/g:ba9a3f105ea552a22d08f2d54dfdbef16af7c99e commit r14-10625-gba9a3f105ea552a22d08f2d54dfdbef16af7c99e Author: liuhongt Date: Thu Aug 29 11:39:20 2024 +0800 Check avx upper register for parallel. For function arguments/return, when it's BLK mode, it's put in a

[gcc r15-3353] i386: Optimize ordered and nonequal

https://gcc.gnu.org/g:86f5031c804220274a9bbebd26b8ebf47a2207ac commit r15-3353-g86f5031c804220274a9bbebd26b8ebf47a2207ac Author: Hu, Lin1 Date: Mon Sep 2 10:24:31 2024 +0800 i386: Optimize ordered and nonequal Currently, when we input !__builtin_isunordered (a, b) && (a != b), gcc

[gcc r13-8999] Check avx upper register for parallel.

https://gcc.gnu.org/g:5e049ada87842947adaca5c607516396889f64d6 commit r13-8999-g5e049ada87842947adaca5c607516396889f64d6 Author: liuhongt Date: Thu Aug 29 11:39:20 2024 +0800 Check avx upper register for parallel. For function arguments/return, when it's BLK mode, it's put in a

[gcc r15-3357] i386: Support vectorized BF16 smaxmin with AVX10.2 instructions

https://gcc.gnu.org/g:29ef601973d7b79338694e59581d4c24bcd07f69 commit r15-3357-g29ef601973d7b79338694e59581d4c24bcd07f69 Author: Levy Hsu Date: Mon Sep 2 10:24:47 2024 +0800 i386: Support vectorized BF16 smaxmin with AVX10.2 instructions gcc/ChangeLog: * config/i3

[gcc r15-3351] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 3

https://gcc.gnu.org/g:5239902210a16b22d59d2cf8b535d615922a5c00 commit r15-3351-g5239902210a16b22d59d2cf8b535d615922a5c00 Author: Pan Li Date: Sun Aug 18 14:08:21 2024 +0800 RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 3 This patch would like to add test c

[gcc r15-3361] [PATCH] RISC-V: Optimize the cost of the DFmode register move for RV32.

https://gcc.gnu.org/g:eca320bfe340beec9267bdb6021c7b387111 commit r15-3361-geca320bfe340beec9267bdb6021c7b387111 Author: Xianmiao Qu Date: Sun Sep 1 22:28:13 2024 -0600 [PATCH] RISC-V: Optimize the cost of the DFmode register move for RV32. Currently, in RV32, even with th

[gcc r15-3354] i386: Optimize generate insn for AVX10.2 compare

https://gcc.gnu.org/g:3b1decef83003db9cf8667977c293435c0f3d024 commit r15-3354-g3b1decef83003db9cf8667977c293435c0f3d024 Author: Hu, Lin1 Date: Mon Sep 2 10:24:36 2024 +0800 i386: Optimize generate insn for AVX10.2 compare gcc/ChangeLog: * config/i386/i386-expand.

[gcc r15-3362] lower SLP load permutation to interleaving

https://gcc.gnu.org/g:464067a242150628ceb0d47daf2297f29a31743c commit r15-3362-g464067a242150628ceb0d47daf2297f29a31743c Author: Richard Biener Date: Mon May 13 14:57:01 2024 +0200 lower SLP load permutation to interleaving The following emulates classical interleaving for SLP loa

[gcc r15-3363] load and store-lanes with SLP

https://gcc.gnu.org/g:9aaedfc4146c5e4b8412913a6ca4092a2731c35c commit r15-3363-g9aaedfc4146c5e4b8412913a6ca4092a2731c35c Author: Richard Biener Date: Fri Jul 5 10:35:08 2024 +0200 load and store-lanes with SLP The following is a prototype for how to represent load/store-lanes

[gcc r12-10694] Check avx upper register for parallel.

https://gcc.gnu.org/g:6585b06303d8fd9da907f443fc0da9faed303712 commit r12-10694-g6585b06303d8fd9da907f443fc0da9faed303712 Author: liuhongt Date: Thu Aug 29 11:39:20 2024 +0800 Check avx upper register for parallel. For function arguments/return, when it's BLK mode, it's put in a

[gcc r15-3350] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2

https://gcc.gnu.org/g:ea81e21d5398bdacf883533fd738fc45ea8d6dd9 commit r15-3350-gea81e21d5398bdacf883533fd738fc45ea8d6dd9 Author: Pan Li Date: Sun Aug 18 12:49:47 2024 +0800 RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2 This patch would like to add test c

[gcc r15-3355] i386: Support vectorized BF16 add/sub/mul/div with AVX10.2 instructions

https://gcc.gnu.org/g:f82fa0da4d9e1fdaf5e4edd70364d5781534ce11 commit r15-3355-gf82fa0da4d9e1fdaf5e4edd70364d5781534ce11 Author: Levy Hsu Date: Mon Sep 2 10:24:45 2024 +0800 i386: Support vectorized BF16 add/sub/mul/div with AVX10.2 instructions AVX10.2 introduces several non-exce

[gcc r15-3352] i386: Auto vectorize sdot_prod, usdot_prod, udot_prod with AVX10.2 instructions

https://gcc.gnu.org/g:b1f9fbb6da1a3ced57c3668cecc9f9449e1b237e commit r15-3352-gb1f9fbb6da1a3ced57c3668cecc9f9449e1b237e Author: Haochen Jiang Date: Mon Sep 2 10:24:29 2024 +0800 i386: Auto vectorize sdot_prod, usdot_prod, udot_prod with AVX10.2 instructions gcc/ChangeLog: