[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RISC-V][PR target/116282] Stabilize pattern conditions

https://gcc.gnu.org/g:36ad5c69a273cb36accd27e70423c81cbd7fbcf9 commit 36ad5c69a273cb36accd27e70423c81cbd7fbcf9 Author: Jeff Law Date: Sat Aug 17 09:52:55 2024 -0600 [RISC-V][PR target/116282] Stabilize pattern conditions So as expected the core problem with target/116282 is that t

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix ICE for vector single-width integer multiply-add intrinsics

https://gcc.gnu.org/g:310cb65e2e93e90d5258c60733e1b70f0c8a7e88 commit 310cb65e2e93e90d5258c60733e1b70f0c8a7e88 Author: Jin Ma Date: Sat Aug 17 10:18:03 2024 -0600 RISC-V: Fix ICE for vector single-width integer multiply-add intrinsics When rs1 is the immediate 0, the following ICE

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] t-rtems: add rv32imf architecture to the RTEMS multilib for RISC-V

https://gcc.gnu.org/g:c59b5f7b505aae5c1d342a309b6603db2a7c9f19 commit c59b5f7b505aae5c1d342a309b6603db2a7c9f19 Author: Kevin Kirspel Date: Sat Aug 17 14:37:18 2024 -0600 t-rtems: add rv32imf architecture to the RTEMS multilib for RISC-V The attach patch is specific to the RTEMS RI

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] Avoid right shifting signed value on ext-dce.cc

https://gcc.gnu.org/g:821e603d560221ec4ab517ce1eb1b0152d9c1eac commit 821e603d560221ec4ab517ce1eb1b0152d9c1eac Author: Jeff Law Date: Sat Aug 17 15:10:38 2024 -0600 [committed] Avoid right shifting signed value on ext-dce.cc This is analogous to a prior patch to ext-dce which fixe

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 2

https://gcc.gnu.org/g:370eaa82697d65d92d5a6270978e18b777bdcfbe commit 370eaa82697d65d92d5a6270978e18b777bdcfbe Author: Pan Li Date: Sat Aug 17 18:04:00 2024 +0800 RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 2 This patch would like to add test cases for the unsigned s

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Make sure high bits of usadd operands is clean for non-Xmode [PR116278]

https://gcc.gnu.org/g:22f0e0f7d321251423a640c5f2b82987917b6d81 commit 22f0e0f7d321251423a640c5f2b82987917b6d81 Author: Pan Li Date: Fri Aug 9 10:26:32 2024 +0800 RISC-V: Make sure high bits of usadd operands is clean for non-Xmode [PR116278] For QI/HImode of .SAT_ADD, the operan

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 3

https://gcc.gnu.org/g:2c215f2b3022907b79a4a5caa855ee5f88f129e5 commit 2c215f2b3022907b79a4a5caa855ee5f88f129e5 Author: Pan Li Date: Sat Aug 17 19:27:11 2024 +0800 RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 3 This patch would like to add test cases for the unsigned s

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PR rtl-optimization/115876] Avoid ubsan in ext-dce.cc

https://gcc.gnu.org/g:540c6b796fe3b6efb51a788cae511ef15b62801c commit 540c6b796fe3b6efb51a788cae511ef15b62801c Author: Jeff Law Date: Sun Aug 18 16:55:52 2024 -0600 [PR rtl-optimization/115876] Avoid ubsan in ext-dce.cc This fixes two general ubsan issues in ext-dce, both related

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Implement the quad and oct .SAT_TRUNC for scalar

https://gcc.gnu.org/g:3cbfc97902cc85ef0591c77bbdb3427447db1a59 commit 3cbfc97902cc85ef0591c77bbdb3427447db1a59 Author: Pan Li Date: Tue Jul 23 11:18:48 2024 +0800 RISC-V: Implement the quad and oct .SAT_TRUNC for scalar This patch would like to implement the quad and oct .SAT_TRUN

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