[gcc(refs/users/meissner/heads/work176)] Add support for -mcpu=future

https://gcc.gnu.org/g:1a0f5719564e2e806b11c8584fcd2386ae0bf36a commit 1a0f5719564e2e806b11c8584fcd2386ae0bf36a Author: Michael Meissner Date: Sat Aug 17 03:24:08 2024 -0400 Add support for -mcpu=future This patch adds the support that can be used in developing GCC support for

[gcc(refs/users/meissner/heads/work176)] Add -mcpu=future tuning support.

https://gcc.gnu.org/g:862273d6a23970f491a9dbab153e92f18110ad62 commit 862273d6a23970f491a9dbab153e92f18110ad62 Author: Michael Meissner Date: Sat Aug 17 03:24:57 2024 -0400 Add -mcpu=future tuning support. This patch makes -mtune=future use the same tuning decision as -mtune=powe

[gcc(refs/users/meissner/heads/work176)] Update ChangeLog.*

https://gcc.gnu.org/g:04913bc20cb2a9519f94631ccb3458c057b5c567 commit 04913bc20cb2a9519f94631ccb3458c057b5c567 Author: Michael Meissner Date: Sat Aug 17 05:40:54 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.meissner | 49 + 1 file

[gcc r15-2963] AVR: target/116390 - Fix an avrtiny asm out template.

https://gcc.gnu.org/g:4065d163151b07b274241377e71dad028576db88 commit r15-2963-g4065d163151b07b274241377e71dad028576db88 Author: Georg-Johann Lay Date: Sat Aug 17 12:49:42 2024 +0200 AVR: target/116390 - Fix an avrtiny asm out template. PR target/116390 gcc/

[gcc r15-2964] doc: Tweak link to gm2 list archive

https://gcc.gnu.org/g:b9f08459c483086b956e7b3e396759fc42460b4c commit r15-2964-gb9f08459c483086b956e7b3e396759fc42460b4c Author: Gerald Pfeifer Date: Sat Aug 17 13:26:36 2024 +0200 doc: Tweak link to gm2 list archive Without the trailing slash we incur a "301 Moved Permanently".

[gcc r15-2965] libstdc++: Tweak links to installation docs

https://gcc.gnu.org/g:16b92be67623f3bfa3b68dbdcf5fe7c060e91180 commit r15-2965-g16b92be67623f3bfa3b68dbdcf5fe7c060e91180 Author: Gerald Pfeifer Date: Sat Aug 17 13:47:09 2024 +0200 libstdc++: Tweak links to installation docs libstdc++v-3: * doc/xml/manual/prerequisites

[gcc r15-2966] doc: Tweak PIM4 link

https://gcc.gnu.org/g:2af578434b21ac224d720808486ceeb023cd89c0 commit r15-2966-g2af578434b21ac224d720808486ceeb023cd89c0 Author: Gerald Pfeifer Date: Sat Aug 17 14:04:31 2024 +0200 doc: Tweak PIM4 link gcc: * doc/gm2.texi (What is GNU Modula-2): Tweak PIM4 link. Diff:

[gcc r14-10597] AVR: target/116390 - Fix an avrtiny asm out template.

https://gcc.gnu.org/g:f3d9c120a1959c5b094001516c1e5cb4ba6f4080 commit r14-10597-gf3d9c120a1959c5b094001516c1e5cb4ba6f4080 Author: Georg-Johann Lay Date: Sat Aug 17 12:49:42 2024 +0200 AVR: target/116390 - Fix an avrtiny asm out template. PR target/116390 gcc/

[gcc r15-2967] libstdc++: Update references to gcc.gnu.org/onlinedocs

https://gcc.gnu.org/g:e68ab0f16072af97f0898fa0a14e72fcda442775 commit r15-2967-ge68ab0f16072af97f0898fa0a14e72fcda442775 Author: Gerald Pfeifer Date: Sat Aug 17 15:21:21 2024 +0200 libstdc++: Update references to gcc.gnu.org/onlinedocs libstdc++-v3: * doc/xml/manual/ab

[gcc r15-2968] RISC-V: Add auto-vect pattern for vector rotate shift

https://gcc.gnu.org/g:54b228d80c54d32ab49cee6148cfd1364b2bc817 commit r15-2968-g54b228d80c54d32ab49cee6148cfd1364b2bc817 Author: Feng Wang Date: Sat Aug 17 08:40:42 2024 -0600 RISC-V: Add auto-vect pattern for vector rotate shift This patch add the vector rotate shift pattern for

[gcc r15-2969] RISC-V: Bugfix incorrect operand for vwsll auto-vect

https://gcc.gnu.org/g:06ae7bc1345a31a5f23dc86b348a1bef59bb3cc1 commit r15-2969-g06ae7bc1345a31a5f23dc86b348a1bef59bb3cc1 Author: Pan Li Date: Sat Aug 17 09:25:58 2024 -0600 RISC-V: Bugfix incorrect operand for vwsll auto-vect This patch would like to fix one ICE when rv64gcv_zvbb

[gcc r15-2970] RISC-V: Bugfix for RVV rounding intrinsic ICE in function checker

https://gcc.gnu.org/g:3f51684ac05f065a87c53d9506400cbe97af6b79 commit r15-2970-g3f51684ac05f065a87c53d9506400cbe97af6b79 Author: Jin Ma Date: Sat Aug 17 09:29:11 2024 -0600 RISC-V: Bugfix for RVV rounding intrinsic ICE in function checker When compiling an interface for rounding o

[gcc r15-2971] [RISC-V][PR target/116282] Stabilize pattern conditions

https://gcc.gnu.org/g:7aed8dedeb9613925930447bf2457c3fd9972d91 commit r15-2971-g7aed8dedeb9613925930447bf2457c3fd9972d91 Author: Jeff Law Date: Sat Aug 17 09:52:55 2024 -0600 [RISC-V][PR target/116282] Stabilize pattern conditions So as expected the core problem with target/116282

[gcc r15-2972] RISC-V: Fix ICE for vector single-width integer multiply-add intrinsics

https://gcc.gnu.org/g:6d734ba485547329599f12bea63842a4fba8d72c commit r15-2972-g6d734ba485547329599f12bea63842a4fba8d72c Author: Jin Ma Date: Sat Aug 17 10:18:03 2024 -0600 RISC-V: Fix ICE for vector single-width integer multiply-add intrinsics When rs1 is the immediate 0, the fol

[gcc r15-2973] Adjust v850 rotate expander to allow more cases for V850E3V5

https://gcc.gnu.org/g:abfc140579682598cd178eb9d0b0160bbfafc633 commit r15-2973-gabfc140579682598cd178eb9d0b0160bbfafc633 Author: Jeff Law Date: Sat Aug 17 10:30:48 2024 -0600 Adjust v850 rotate expander to allow more cases for V850E3V5 The recent if-conversion changes tripped a fa

[gcc r15-2974] t-rtems: add rv32imf architecture to the RTEMS multilib for RISC-V

https://gcc.gnu.org/g:efcfd1d2ad8779b5c1b41b7f702516ca1da46925 commit r15-2974-gefcfd1d2ad8779b5c1b41b7f702516ca1da46925 Author: Kevin Kirspel Date: Sat Aug 17 14:37:18 2024 -0600 t-rtems: add rv32imf architecture to the RTEMS multilib for RISC-V The attach patch is specific to th

[gcc r15-2975] [committed] Avoid right shifting signed value on ext-dce.cc

https://gcc.gnu.org/g:61e179b1b363454926504fac13b554ad7f1b0f72 commit r15-2975-g61e179b1b363454926504fac13b554ad7f1b0f72 Author: Jeff Law Date: Sat Aug 17 15:10:38 2024 -0600 [committed] Avoid right shifting signed value on ext-dce.cc This is analogous to a prior patch to ext-dce

[gcc r15-2977] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 2

https://gcc.gnu.org/g:6fbdbad97d451cc220a5654c8b97b9911485ef4a commit r15-2977-g6fbdbad97d451cc220a5654c8b97b9911485ef4a Author: Pan Li Date: Sat Aug 17 18:04:00 2024 +0800 RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 2 This patch would like to add test cases for the

[gcc r15-2978] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 3

https://gcc.gnu.org/g:8d0efcf5581abf2560701f4143a0c2ccb261d1f7 commit r15-2978-g8d0efcf5581abf2560701f4143a0c2ccb261d1f7 Author: Pan Li Date: Sat Aug 17 19:27:11 2024 +0800 RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 3 This patch would like to add test cases for the

[gcc r15-2979] RISC-V: Make sure high bits of usadd operands is clean for non-Xmode [PR116278]

https://gcc.gnu.org/g:e8f31f4f58f0fcf1716fc1d9ee003fbcdda600c3 commit r15-2979-ge8f31f4f58f0fcf1716fc1d9ee003fbcdda600c3 Author: Pan Li Date: Fri Aug 9 10:26:32 2024 +0800 RISC-V: Make sure high bits of usadd operands is clean for non-Xmode [PR116278] For QI/HImode of .SAT_ADD,

[gcc r15-2980] RISC-V: Implement the quad and oct .SAT_TRUNC for scalar

https://gcc.gnu.org/g:a183b255be8ec8f434c3c39f3f4e01d6bd5566f8 commit r15-2980-ga183b255be8ec8f434c3c39f3f4e01d6bd5566f8 Author: Pan Li Date: Tue Jul 23 11:18:48 2024 +0800 RISC-V: Implement the quad and oct .SAT_TRUNC for scalar This patch would like to implement the quad and oct