[gcc r14-9589] tree-optimization/113727 - bogus SRA with BIT_FIELD_REF

https://gcc.gnu.org/g:9d6ff6f1ea2ae7fc32ec9fbd0554fb06238ed045 commit r14-9589-g9d6ff6f1ea2ae7fc32ec9fbd0554fb06238ed045 Author: Richard Biener Date: Tue Mar 19 14:50:06 2024 +0100 tree-optimization/113727 - bogus SRA with BIT_FIELD_REF When SRA analyzes BIT_FIELD_REFs it handles

[gcc r14-9590] tree-optimization/111736 - avoid address sanitizing of __seg_gs

https://gcc.gnu.org/g:134ef2a8cac1a5cc718739bd7d3b3472947c80d6 commit r14-9590-g134ef2a8cac1a5cc718739bd7d3b3472947c80d6 Author: Richard Biener Date: Thu Mar 21 08:30:39 2024 +0100 tree-optimization/111736 - avoid address sanitizing of __seg_gs The following more thoroughly avoids

[gcc r13-8474] rs6000: Don't ICE when compiling the __builtin_vsx_splat_2di [PR113950]

https://gcc.gnu.org/g:27eb6e81e6e578da9f9947d3f96c0fa58971fe7f commit r13-8474-g27eb6e81e6e578da9f9947d3f96c0fa58971fe7f Author: Jeevitha Date: Wed Mar 20 23:34:46 2024 -0500 rs6000: Don't ICE when compiling the __builtin_vsx_splat_2di [PR113950] When we expand the __builtin_vsx_s

[gcc r14-9591] Fix runtime error for nonlinear iv vectorization(step_mult).

https://gcc.gnu.org/g:ac2f8c2a367151fc0410f904339c475a953cffc8 commit r14-9591-gac2f8c2a367151fc0410f904339c475a953cffc8 Author: liuhongt Date: Thu Mar 21 13:15:23 2024 +0800 Fix runtime error for nonlinear iv vectorization(step_mult). wi::from_mpz doesn't take a sign argument, we

[gcc r13-8475] Fix runtime error for nonlinear iv vectorization(step_mult).

https://gcc.gnu.org/g:199b021a38f30b681e0dbecd2d0296beabd50b13 commit r13-8475-g199b021a38f30b681e0dbecd2d0296beabd50b13 Author: liuhongt Date: Thu Mar 21 13:15:23 2024 +0800 Fix runtime error for nonlinear iv vectorization(step_mult). wi::from_mpz doesn't take a sign argument, we

[gcc r13-8476] tree-optimization/111736 - avoid address sanitizing of __seg_gs

https://gcc.gnu.org/g:6d5eb47849bcf9aecefacf7d7e4767750b1ec83b commit r13-8476-g6d5eb47849bcf9aecefacf7d7e4767750b1ec83b Author: Richard Biener Date: Thu Mar 21 08:30:39 2024 +0100 tree-optimization/111736 - avoid address sanitizing of __seg_gs The following more thoroughly avoids

[gcc r13-8477] debug/112718 - reset all type units with -ffat-lto-objects

https://gcc.gnu.org/g:dd1948d467dc25b9b462b173ec40b95f6aa51356 commit r13-8477-gdd1948d467dc25b9b462b173ec40b95f6aa51356 Author: Richard Biener Date: Mon Jan 22 15:42:59 2024 +0100 debug/112718 - reset all type units with -ffat-lto-objects When mixing -flto, -ffat-lto-objects and

[gcc r13-8479] tree-optimization/114027 - conditional reduction chain

https://gcc.gnu.org/g:bd276b5340563182f7d95c383196fdd6fb7e6a1d commit r13-8479-gbd276b5340563182f7d95c383196fdd6fb7e6a1d Author: Richard Biener Date: Thu Feb 22 10:50:12 2024 +0100 tree-optimization/114027 - conditional reduction chain When we classify a conditional reduction chai

[gcc r13-8481] middle-end/114070 - VEC_COND_EXPR folding

https://gcc.gnu.org/g:a3ff14ac4804be400a52dcf630f0de2d57cae835 commit r13-8481-ga3ff14ac4804be400a52dcf630f0de2d57cae835 Author: Richard Biener Date: Thu Feb 29 09:22:19 2024 +0100 middle-end/114070 - VEC_COND_EXPR folding The following amends the PR114070 fix to optimistically al

[gcc r13-8482] tree-optimization/114203 - wrong CLZ niter computation

https://gcc.gnu.org/g:a729b1227bc8c84cd91a3b8c9c9d11bc43d415de commit r13-8482-ga729b1227bc8c84cd91a3b8c9c9d11bc43d415de Author: Richard Biener Date: Mon Mar 4 10:38:31 2024 +0100 tree-optimization/114203 - wrong CLZ niter computation For precision less than int we apply the adjus

[gcc r13-8478] tree-optimization/113910 - huge compile time during PTA

https://gcc.gnu.org/g:9a19811ea1e9b3024c0f41b074d71679088bb2d7 commit r13-8478-g9a19811ea1e9b3024c0f41b074d71679088bb2d7 Author: Richard Biener Date: Wed Feb 14 12:33:13 2024 +0100 tree-optimization/113910 - huge compile time during PTA For the testcase in PR113910 we spend a lot

[gcc r13-8480] middle-end/114070 - folding breaking VEC_COND expansion

https://gcc.gnu.org/g:a9a425df628ab80374cc6a132d39e470bc78c8bc commit r13-8480-ga9a425df628ab80374cc6a132d39e470bc78c8bc Author: Richard Biener Date: Fri Feb 23 16:06:05 2024 +0100 middle-end/114070 - folding breaking VEC_COND expansion The following properly guards the simplifica

[gcc r14-9592] libgcc: Fix up bitint division [PR114397]

https://gcc.gnu.org/g:59b6cece54f33ac4994834d01e18269856576556 commit r14-9592-g59b6cece54f33ac4994834d01e18269856576556 Author: Jakub Jelinek Date: Thu Mar 21 13:07:50 2024 +0100 libgcc: Fix up bitint division [PR114397] The Knuth's division algorithm relies on the number of divi

[gcc r14-9593] amdgcn: Clean up device memory in gcn-run

https://gcc.gnu.org/g:c3fb8a4d150586459a9fa177cb2aeeac5e4c0464 commit r14-9593-gc3fb8a4d150586459a9fa177cb2aeeac5e4c0464 Author: Andrew Stubbs Date: Wed Mar 20 12:49:24 2024 + amdgcn: Clean up device memory in gcn-run gcc/ChangeLog: * config/gcn/gcn-run.cc (ma

[gcc r14-9594] amdgcn: Ensure gfx11 is running in cumode

https://gcc.gnu.org/g:69dc2dc7e0e853856b84b1bcc89d0241d8a570aa commit r14-9594-g69dc2dc7e0e853856b84b1bcc89d0241d8a570aa Author: Andrew Stubbs Date: Mon Mar 4 15:48:47 2024 + amdgcn: Ensure gfx11 is running in cumode CUmode "on" is the setting for compatibility with GCN and CD

[gcc r14-9595] amdgcn: Comment correction

https://gcc.gnu.org/g:a2fe34e0b993d5fb879d75ddb42b24b45c4b7242 commit r14-9595-ga2fe34e0b993d5fb879d75ddb42b24b45c4b7242 Author: Andrew Stubbs Date: Mon Mar 4 15:52:00 2024 + amdgcn: Comment correction The location of the marker was changed, but the comment wasn't updated.

[gcc r13-8483] middle-end/113622 - allow .VEC_SET and .VEC_EXTRACT for global hard regs

https://gcc.gnu.org/g:d4c0800aab864bb95260e12342d18695c6ebbec8 commit r13-8483-gd4c0800aab864bb95260e12342d18695c6ebbec8 Author: Richard Biener Date: Mon Jan 29 09:47:31 2024 +0100 middle-end/113622 - allow .VEC_SET and .VEC_EXTRACT for global hard regs The following expands .VEC_

[gcc r13-8484] tree-optimization/113670 - gather/scatter to/from hard registers

https://gcc.gnu.org/g:ac664905b837095b15099e44e83471672eee7aa9 commit r13-8484-gac664905b837095b15099e44e83471672eee7aa9 Author: Richard Biener Date: Wed Jan 31 09:09:50 2024 +0100 tree-optimization/113670 - gather/scatter to/from hard registers The following makes sure we're not

[gcc r13-8486] tree-optimization/114231 - use patterns for BB SLP discovery root stmts

https://gcc.gnu.org/g:04fffbaa87997ac893a9aa68b674c938ba3ecddb commit r13-8486-g04fffbaa87997ac893a9aa68b674c938ba3ecddb Author: Richard Biener Date: Tue Mar 5 10:55:56 2024 +0100 tree-optimization/114231 - use patterns for BB SLP discovery root stmts The following makes sure to u

[gcc r13-8485] tree-optimization/112793 - SLP of constant/external code-generated twice

https://gcc.gnu.org/g:42d5985e9884299c8d837ad1588fb47b211b4baf commit r13-8485-g42d5985e9884299c8d837ad1588fb47b211b4baf Author: Richard Biener Date: Wed Dec 13 14:23:31 2023 +0100 tree-optimization/112793 - SLP of constant/external code-generated twice The following makes the att

[gcc r14-9596] c++: explicit inst of template method not generated [PR110323]

https://gcc.gnu.org/g:081f8937cb82da311c224da04b0c6cbd57a8fb5d commit r14-9596-g081f8937cb82da311c224da04b0c6cbd57a8fb5d Author: Marek Polacek Date: Thu Mar 7 20:41:23 2024 -0500 c++: explicit inst of template method not generated [PR110323] Consider constexpr int VAL =

[gcc r14-9597] Fortran: improve array component description in runtime error message [PR30802]

https://gcc.gnu.org/g:509352069d6f166d396f4b4a86e71ea521f2ca78 commit r14-9597-g509352069d6f166d396f4b4a86e71ea521f2ca78 Author: Harald Anlauf Date: Wed Mar 20 20:59:24 2024 +0100 Fortran: improve array component description in runtime error message [PR30802] Runtime error messag

[gcc r14-9598] PR modula2/114418 missing import of TSIZE from system causes ICE

https://gcc.gnu.org/g:ba744d50ac0360f7992a42494db766f6548913e3 commit r14-9598-gba744d50ac0360f7992a42494db766f6548913e3 Author: Gaius Mulley Date: Thu Mar 21 18:30:23 2024 + PR modula2/114418 missing import of TSIZE from system causes ICE This patch detects whether the symbol

[gcc r14-9599] PR modula2/113836 gm2 does not dump gimple or quadruples to file

https://gcc.gnu.org/g:48d49200510198cafcab55601cd8e5f8eb541f01 commit r14-9599-g48d49200510198cafcab55601cd8e5f8eb541f01 Author: Gaius Mulley Date: Thu Mar 21 19:38:03 2024 + PR modula2/113836 gm2 does not dump gimple or quadruples to file This patch provides the localized mod

[gcc r14-9600] analyzer: fix ignored constraints involving casts [PR113619]

https://gcc.gnu.org/g:7a5a4a4467b2e18ff4fe24f565e120280d3e6ba7 commit r14-9600-g7a5a4a4467b2e18ff4fe24f565e120280d3e6ba7 Author: David Malcolm Date: Thu Mar 21 17:48:38 2024 -0400 analyzer: fix ignored constraints involving casts [PR113619] gcc/analyzer/ChangeLog: PR a

[gcc r14-9602] PR modula2/114422 Attempting to declare a set of unknown type causes ICE

https://gcc.gnu.org/g:1542e8a44cc35e63233d3557afbf501c5ff84c55 commit r14-9602-g1542e8a44cc35e63233d3557afbf501c5ff84c55 Author: Gaius Mulley Date: Fri Mar 22 01:47:31 2024 + PR modula2/114422 Attempting to declare a set of unknown type causes ICE This patch corrects an error

[gcc r14-9603] Move pr114396.c from gcc.target/i386 to gcc.c-torture/execute.

https://gcc.gnu.org/g:9a6c7aa1b011b77fcd9b19f7b8d7ff0fc823cdb2 commit r14-9603-g9a6c7aa1b011b77fcd9b19f7b8d7ff0fc823cdb2 Author: liuhongt Date: Fri Mar 22 10:09:43 2024 +0800 Move pr114396.c from gcc.target/i386 to gcc.c-torture/execute. Also fixed a typo in the testcase.

[gcc r13-8488] Move pr114396.c from gcc.target/i386 to gcc.c-torture/execute.

https://gcc.gnu.org/g:e6a3d1f5bcfd954b614155d96c97bde8ac230e2e commit r13-8488-ge6a3d1f5bcfd954b614155d96c97bde8ac230e2e Author: liuhongt Date: Fri Mar 22 10:09:43 2024 +0800 Move pr114396.c from gcc.target/i386 to gcc.c-torture/execute. Also fixed a typo in the testcase.

[gcc r14-9604] RISC-V: Bugfix ICE for __attribute__((target("arch=+v"))

https://gcc.gnu.org/g:d3c24e9e55a7cf18df313a8b32b6de4b3ba81013 commit r14-9604-gd3c24e9e55a7cf18df313a8b32b6de4b3ba81013 Author: Pan Li Date: Mon Mar 18 11:21:29 2024 +0800 RISC-V: Bugfix ICE for __attribute__((target("arch=+v")) This patch would like to fix one ICE for __attribut

[gcc r14-9605] RISC-V: Bugfix function target attribute pollution

https://gcc.gnu.org/g:9941f0295a14659e25260458efd2e46a68ad0342 commit r14-9605-g9941f0295a14659e25260458efd2e46a68ad0342 Author: Pan Li Date: Tue Mar 19 09:43:24 2024 +0800 RISC-V: Bugfix function target attribute pollution This patch depends on below ICE fix. https://gcc

[gcc r14-9606] [committed] Fix RISC-V missing stack tie

https://gcc.gnu.org/g:c65046ff2ef0a9a46e59bc0b3369b2d226f6a239 commit r14-9606-gc65046ff2ef0a9a46e59bc0b3369b2d226f6a239 Author: Jeff Law Date: Thu Mar 21 20:41:59 2024 -0600 [committed] Fix RISC-V missing stack tie As some of you know, Raphael has been working on stack-clash supp

[gcc(refs/users/meissner/heads/work163-dmf)] Add support for XVRL instruction.

https://gcc.gnu.org/g:6ff874d066d523bd6b71e2f944f5740f651ed022 commit 6ff874d066d523bd6b71e2f944f5740f651ed022 Author: Michael Meissner Date: Thu Mar 21 23:39:11 2024 -0400 Add support for XVRL instruction. 2024-03-21 Michael Meissner gcc/ * config/rs6

[gcc(refs/users/meissner/heads/work163-dmf)] Revert all changes

https://gcc.gnu.org/g:d49aa664ce768f629c858158eca406991a66da85 commit d49aa664ce768f629c858158eca406991a66da85 Author: Michael Meissner Date: Thu Mar 21 23:40:14 2024 -0400 Revert all changes Diff: --- gcc/config/rs6000/altivec.md | 11 --- 1 file changed, 11 deletions(-) diff -

[gcc(refs/users/meissner/heads/work163-dmf)] Add support for XVRL instruction.

https://gcc.gnu.org/g:145bc7b00c10cf6e59897aba7f61c3a24c85ca0b commit 145bc7b00c10cf6e59897aba7f61c3a24c85ca0b Author: Michael Meissner Date: Thu Mar 21 23:49:02 2024 -0400 Add support for XVRL instruction. 2024-03-21 Michael Meissner gcc/ * config/rs6

[gcc(refs/users/meissner/heads/work163-dmf)] Revert all changes

https://gcc.gnu.org/g:889e9e1165b5f84cf84820ca9b1926548941aded commit 889e9e1165b5f84cf84820ca9b1926548941aded Author: Michael Meissner Date: Thu Mar 21 23:59:52 2024 -0400 Revert all changes Diff: --- gcc/config/rs6000/altivec.md | 14 - gcc/config/rs6000/constrain

[gcc(refs/users/meissner/heads/work163-dmf)] Add wD constraint.

https://gcc.gnu.org/g:935c71424570d5e85a85edb9a1516c3ef578a6f8 commit 935c71424570d5e85a85edb9a1516c3ef578a6f8 Author: Michael Meissner Date: Fri Mar 22 00:14:19 2024 -0400 Add wD constraint. This patch adds a new constraint ('wD') that matches the accumulator registers that

[gcc(refs/users/meissner/heads/work163-dmf)] Revert all changes

https://gcc.gnu.org/g:8ed4af0366a9b0d8670b96dfba25b85d3ba9b65c commit 8ed4af0366a9b0d8670b96dfba25b85d3ba9b65c Author: Michael Meissner Date: Fri Mar 22 00:16:08 2024 -0400 Revert all changes Diff: --- gcc/config/rs6000/constraints.md | 3 --- gcc/config/rs6000/mma.md | 54 +++

[gcc(refs/users/meissner/heads/work163-dmf)] Use vector pair load/store for memcpy with -mcpu=future

https://gcc.gnu.org/g:e9f36e1c173a1967318ccfc2341e46b526d6f0aa commit e9f36e1c173a1967318ccfc2341e46b526d6f0aa Author: Michael Meissner Date: Fri Mar 22 00:16:39 2024 -0400 Use vector pair load/store for memcpy with -mcpu=future In the development for the power10 processor, GCC di

[gcc(refs/users/meissner/heads/work163-dmf)] Add wD constraint.

https://gcc.gnu.org/g:ca9dad30fef736a655999cb4ab1cbe1d8cdd20f1 commit ca9dad30fef736a655999cb4ab1cbe1d8cdd20f1 Author: Michael Meissner Date: Fri Mar 22 00:19:46 2024 -0400 Add wD constraint. This patch adds a new constraint ('wD') that matches the accumulator registers that

[gcc(refs/users/meissner/heads/work163-dmf)] Revert all changes

https://gcc.gnu.org/g:90b5e76409a32556b7672139d6a2d031d0d5937e commit 90b5e76409a32556b7672139d6a2d031d0d5937e Author: Michael Meissner Date: Fri Mar 22 00:21:34 2024 -0400 Revert all changes Diff: --- gcc/config/rs6000/constraints.md | 3 --- gcc/config/rs6000/mma.md | 54 +++

[gcc(refs/users/meissner/heads/work163-dmf)] Use vector pair load/store for memcpy with -mcpu=future

https://gcc.gnu.org/g:385b09d7c32c2cb7a3d16f738e870d1d0bad6997 commit 385b09d7c32c2cb7a3d16f738e870d1d0bad6997 Author: Michael Meissner Date: Fri Mar 22 00:22:20 2024 -0400 Use vector pair load/store for memcpy with -mcpu=future In the development for the power10 processor, GCC di

[gcc(refs/users/meissner/heads/work163-dmf)] Add wD constraint.

https://gcc.gnu.org/g:1aef3129fb903b6ca80746e0fcffdcf2c86728ee commit 1aef3129fb903b6ca80746e0fcffdcf2c86728ee Author: Michael Meissner Date: Fri Mar 22 00:22:56 2024 -0400 Add wD constraint. This patch adds a new constraint ('wD') that matches the accumulator registers that

[gcc(refs/users/meissner/heads/work163-dmf)] Add support for dense math registers.

https://gcc.gnu.org/g:732fcb3a20b89b6cf405c4f7131c82de6bde8303 commit 732fcb3a20b89b6cf405c4f7131c82de6bde8303 Author: Michael Meissner Date: Fri Mar 22 00:27:47 2024 -0400 Add support for dense math registers. The MMA subsystem added the notion of accumulator registers as an opti

[gcc(refs/users/meissner/heads/work163-dmf)] PowerPC: Switch to dense math names for all MMA operations.

https://gcc.gnu.org/g:f2c0b60fd88b3108e4225a2dceac25832d8537b5 commit f2c0b60fd88b3108e4225a2dceac25832d8537b5 Author: Michael Meissner Date: Fri Mar 22 00:29:03 2024 -0400 PowerPC: Switch to dense math names for all MMA operations. This patch changes the assembler instruction nam

[gcc(refs/users/meissner/heads/work163-dmf)] Add dense math test for new instruction names.

https://gcc.gnu.org/g:cf80b10c5a0b0e109c4d00404e03ed6f3c0606c0 commit cf80b10c5a0b0e109c4d00404e03ed6f3c0606c0 Author: Michael Meissner Date: Fri Mar 22 00:31:11 2024 -0400 Add dense math test for new instruction names. 2024-03-22 Michael Meissner gcc/testsuite/

[gcc(refs/users/meissner/heads/work163-dmf)] PowerPC: Add support for 1, 024 bit DMR registers.

https://gcc.gnu.org/g:365106aa952ceba51092df38086d212802b1fb5a commit 365106aa952ceba51092df38086d212802b1fb5a Author: Michael Meissner Date: Fri Mar 22 00:33:23 2024 -0400 PowerPC: Add support for 1,024 bit DMR registers. This patch is a prelimianry patch to add the full 1,024 bi

[gcc(refs/users/meissner/heads/work163-dmf)] Add support for XVRL instruction.

https://gcc.gnu.org/g:7200cbd8395cb620028eeb6c6ef003f6064615e2 commit 7200cbd8395cb620028eeb6c6ef003f6064615e2 Author: Michael Meissner Date: Fri Mar 22 00:37:34 2024 -0400 Add support for XVRL instruction. 2024-03-22 Michael Meissner gcc/ * config/rs6

[gcc(refs/users/meissner/heads/work163-dmf)] Update ChangeLog.*

https://gcc.gnu.org/g:7bedd90064489ea6db3a28999df34d7e1340dbb2 commit 7bedd90064489ea6db3a28999df34d7e1340dbb2 Author: Michael Meissner Date: Fri Mar 22 00:45:00 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.dmf | 45 + 1 file changed,

[gcc(refs/users/meissner/heads/work163-dmf)] Support load/store vector with right length.

https://gcc.gnu.org/g:57f8bb746fcadd38e99dd9eee715f9ff15ad2822 commit 57f8bb746fcadd38e99dd9eee715f9ff15ad2822 Author: Michael Meissner Date: Fri Mar 22 00:48:43 2024 -0400 Support load/store vector with right length. This patch adds support for new instructions that may be added

[gcc(refs/users/meissner/heads/work163-dmf)] Add saturating subtract built-ins.

https://gcc.gnu.org/g:0376ff1f351466628aa8fd9f304c6e8c6e3cdb82 commit 0376ff1f351466628aa8fd9f304c6e8c6e3cdb82 Author: Michael Meissner Date: Fri Mar 22 00:51:29 2024 -0400 Add saturating subtract built-ins. This patch adds support for a saturating subtract built-in function that

[gcc(refs/users/meissner/heads/work163-dmf)] Add paddis support.

https://gcc.gnu.org/g:f453411169f9aaaf02b04c2c5cf843a608df8173 commit f453411169f9aaaf02b04c2c5cf843a608df8173 Author: Michael Meissner Date: Fri Mar 22 00:56:43 2024 -0400 Add paddis support. 2024-03-22 Michael Meissner gcc/ * config/rs6000/constraint

[gcc(refs/users/meissner/heads/work163-dmf)] Update ChangeLog.*

https://gcc.gnu.org/g:ae0e0f7725093cfc154ea376e6da9ac652624d45 commit ae0e0f7725093cfc154ea376e6da9ac652624d45 Author: Michael Meissner Date: Fri Mar 22 00:58:36 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.dmf | 122 ++ 1 file

[gcc r14-9607] RISC-V: Don't add fractional LMUL types to V_VLS for XTheadVector

https://gcc.gnu.org/g:fd5e5dda8d79d62396f56d4fdd628b4bc5f9fa24 commit r14-9607-gfd5e5dda8d79d62396f56d4fdd628b4bc5f9fa24 Author: Christoph Müllner Date: Thu Mar 21 15:40:49 2024 +0100 RISC-V: Don't add fractional LMUL types to V_VLS for XTheadVector The expansion of `memset` (via