[gcc r15-8032] libgcc: Remove PREDRES and LS64 from AArch64 cpuinfo

https://gcc.gnu.org/g:6e47e6d48844ee578fd384aaa4b8cd62d73b49db commit r15-8032-g6e47e6d48844ee578fd384aaa4b8cd62d73b49db Author: Wilco Dijkstra Date: Mon Feb 24 16:38:02 2025 + libgcc: Remove PREDRES and LS64 from AArch64 cpuinfo Change AArch64 cpuinfo to follow the latest upd

[gcc r15-7871] AArch64: Enable early scheduling for -O3 and higher (PR118351)

https://gcc.gnu.org/g:f870302515d5fcf7355f0108c3ead0038ff326fd commit r15-7871-gf870302515d5fcf7355f0108c3ead0038ff326fd Author: Wilco Dijkstra Date: Mon Mar 3 16:47:32 2025 + AArch64: Enable early scheduling for -O3 and higher (PR118351) Enable the early scheduler on AArch64

[gcc r15-6922] AArch64: Add FULLY_PIPELINED_FMA to tune baseline

https://gcc.gnu.org/g:2713f6bb90765de81954275a30c62432d30e1d68 commit r15-6922-g2713f6bb90765de81954275a30c62432d30e1d68 Author: Wilco Dijkstra Date: Thu Nov 14 14:34:17 2024 + AArch64: Add FULLY_PIPELINED_FMA to tune baseline Add FULLY_PIPELINED_FMA to tune baseline - this is

[gcc r15-6923] AArch64: Update neoverse512tvb tuning

https://gcc.gnu.org/g:4ce502f31f95ec19e7d347d43afcd015895f135d commit r15-6923-g4ce502f31f95ec19e7d347d43afcd015895f135d Author: Wilco Dijkstra Date: Fri Jan 10 19:48:02 2025 + AArch64: Update neoverse512tvb tuning Fix the neoverse512tvb tuning to be like Neoverse V1/V2 and ad

[gcc r15-6921] AArch64: Deprecate -mabi=ilp32

https://gcc.gnu.org/g:625ea3c6ea1811388d030eddff57cd46c209d49a commit r15-6921-g625ea3c6ea1811388d030eddff57cd46c209d49a Author: Wilco Dijkstra Date: Thu Jan 9 19:41:14 2025 + AArch64: Deprecate -mabi=ilp32 ILP32 was originally intended to make porting to AArch64 easier. Supp

[gcc r15-6802] libatomic: Cleanup AArch64 ifunc selection

https://gcc.gnu.org/g:81bcf412c1c221bc2557666a6ca8381dac1de097 commit r15-6802-g81bcf412c1c221bc2557666a6ca8381dac1de097 Author: Wilco Dijkstra Date: Fri Jan 10 18:01:58 2025 + libatomic: Cleanup AArch64 ifunc selection Simplify and cleanup ifunc selection logic. Since LRCPC3

[gcc r15-6661] AArch64: Switch off early scheduling

https://gcc.gnu.org/g:c5db3f50bdf34ea96fd193a2a66d686401053bd2 commit r15-6661-gc5db3f50bdf34ea96fd193a2a66d686401053bd2 Author: Wilco Dijkstra Date: Fri Nov 1 14:40:26 2024 + AArch64: Switch off early scheduling The early scheduler takes up ~33% of the total build time, howev

[gcc r15-6660] AArch64: Block combine_and_move from creating FP literal loads

https://gcc.gnu.org/g:45d306a835cb3f865a897dc7c04efbe1f9f46c28 commit r15-6660-g45d306a835cb3f865a897dc7c04efbe1f9f46c28 Author: Wilco Dijkstra Date: Fri Nov 1 14:44:56 2024 + AArch64: Block combine_and_move from creating FP literal loads The IRA combine_and_move pass runs if

[gcc r14-11101] arm: Fix LDRD register overlap [PR117675]

https://gcc.gnu.org/g:9366c328518766d896155388726055624716c0af commit r14-11101-g9366c328518766d896155388726055624716c0af Author: Wilco Dijkstra Date: Tue Dec 10 14:22:48 2024 + arm: Fix LDRD register overlap [PR117675] The register indexed variants of LDRD have complex regist

[gcc r15-6087] AArch64: Add baseline tune

https://gcc.gnu.org/g:132025a5fe6a9ba59d62126ecba21887f7ac0f98 commit r15-6087-g132025a5fe6a9ba59d62126ecba21887f7ac0f98 Author: Wilco Dijkstra Date: Thu Nov 14 14:28:10 2024 + AArch64: Add baseline tune Cleanup the extra tune defines by introducing AARCH64_EXTRA_TUNE_BASE as

[gcc r15-6088] arm: Fix LDRD register overlap [PR117675]

https://gcc.gnu.org/g:21fbfae2e55e1a153820acc6fbd922e66f67e65b commit r15-6088-g21fbfae2e55e1a153820acc6fbd922e66f67e65b Author: Wilco Dijkstra Date: Tue Dec 10 14:22:48 2024 + arm: Fix LDRD register overlap [PR117675] The register indexed variants of LDRD have complex registe

[gcc r15-6086] AArch64: Cleanup alignment macros

https://gcc.gnu.org/g:bf6efbbad14e46f97bcc36c531000d8d4740c863 commit r15-6086-gbf6efbbad14e46f97bcc36c531000d8d4740c863 Author: Wilco Dijkstra Date: Tue Oct 1 16:51:14 2024 + AArch64: Cleanup alignment macros Change the AARCH64_EXPAND_ALIGNMENT macro into proper function call

[gcc r15-6085] AArch64: Use LDP/STP for large struct types

https://gcc.gnu.org/g:27d9b6d312678c7b9b09104eb0f48dc46e0f8ca2 commit r15-6085-g27d9b6d312678c7b9b09104eb0f48dc46e0f8ca2 Author: Wilco Dijkstra Date: Fri May 10 17:13:40 2024 + AArch64: Use LDP/STP for large struct types Use LDP/STP for large struct types as they have useful i

[gcc r15-5173] AArch64: Cleanup fusion defines

https://gcc.gnu.org/g:deb0e2f61908bdc57b481995fa9e7c5083839a25 commit r15-5173-gdeb0e2f61908bdc57b481995fa9e7c5083839a25 Author: Wilco Dijkstra Date: Wed Oct 2 16:34:41 2024 + AArch64: Cleanup fusion defines Cleanup the fusion defines by introducing AARCH64_FUSE_BASE as a comm

[gcc r15-5174] AArch64: Remove duplicated addr_cost tables

https://gcc.gnu.org/g:95305c800b1b3263534fdf67b63609772ecbb78d commit r15-5174-g95305c800b1b3263534fdf67b63609772ecbb78d Author: Wilco Dijkstra Date: Mon Oct 7 15:42:49 2024 + AArch64: Remove duplicated addr_cost tables Remove duplicated addr_cost tables - use generic_armv9_a_

[gcc r15-4678] AArch64: Add more accurate constraint [PR117292]

https://gcc.gnu.org/g:7c17058eac3834fb03ec9e518235e4192557b97d commit r15-4678-g7c17058eac3834fb03ec9e518235e4192557b97d Author: Wilco Dijkstra Date: Fri Oct 25 14:53:58 2024 + AArch64: Add more accurate constraint [PR117292] As shown in the PR, reload may only check the const

[gcc r15-4572] AArch64: Remove redundant check in aarch64_simd_mov

https://gcc.gnu.org/g:2ac01a4efceacb9f2f9433db636545885296da0a commit r15-4572-g2ac01a4efceacb9f2f9433db636545885296da0a Author: Wilco Dijkstra Date: Thu Oct 17 14:33:44 2024 + AArch64: Remove redundant check in aarch64_simd_mov The split condition in aarch64_simd_mov uses aa

[gcc r15-4571] AArch64: Fix copysign patterns

https://gcc.gnu.org/g:7c7c895c2f34d2a5c0cd2139c5e76c13c6c030c9 commit r15-4571-g7c7c895c2f34d2a5c0cd2139c5e76c13c6c030c9 Author: Wilco Dijkstra Date: Tue Oct 15 16:22:23 2024 + AArch64: Fix copysign patterns The current copysign pattern has a mismatch in the predicates and co

[gcc r15-4568] AArch64: Improve SIMD immediate generation (2/3)

https://gcc.gnu.org/g:756890d66cf4971fc11187ccdf5893681aa661a1 commit r15-4568-g756890d66cf4971fc11187ccdf5893681aa661a1 Author: Wilco Dijkstra Date: Tue Oct 8 15:55:25 2024 + AArch64: Improve SIMD immediate generation (2/3) Allow use of SVE immediates when generating AdvSIMD

[gcc r15-4569] AArch64: Add support for SIMD xor immediate (3/3)

https://gcc.gnu.org/g:22a37534c640ca5ff2f0e947dfe60df59fb6bba1 commit r15-4569-g22a37534c640ca5ff2f0e947dfe60df59fb6bba1 Author: Wilco Dijkstra Date: Mon Oct 14 16:53:44 2024 + AArch64: Add support for SIMD xor immediate (3/3) Add support for SVE xor immediate when generating

[gcc r15-4567] AArch64: Improve SIMD immediate generation (1/3)

https://gcc.gnu.org/g:bcbf4fa46ae2919cf281322bd39f4810b7c18c9d commit r15-4567-gbcbf4fa46ae2919cf281322bd39f4810b7c18c9d Author: Wilco Dijkstra Date: Tue Oct 8 13:32:09 2024 + AArch64: Improve SIMD immediate generation (1/3) Cleanup the various interfaces related to SIMD immed

[gcc r14-10399] Aarch64, bugfix: Fix NEON bigendian addp intrinsic [PR114890]

https://gcc.gnu.org/g:72753ec82076d15443c32aac88a8c0fa0ab4bc2f commit r14-10399-g72753ec82076d15443c32aac88a8c0fa0ab4bc2f Author: Alfie Richards Date: Thu Jul 4 09:09:19 2024 +0200 Aarch64, bugfix: Fix NEON bigendian addp intrinsic [PR114890] This change removes code that switches

[gcc r14-10398] Arm: Fix ldrd offset range [PR115153]

https://gcc.gnu.org/g:83332e3f808b146ca06dbc6a91d15bd3e5650658 commit r14-10398-g83332e3f808b146ca06dbc6a91d15bd3e5650658 Author: Wilco Dijkstra Date: Fri Jul 5 17:31:25 2024 +0100 Arm: Fix ldrd offset range [PR115153] The valid offset range of LDRD in arm_legitimate_index_p is in

[gcc r15-1865] Arm: Fix ldrd offset range [PR115153]

https://gcc.gnu.org/g:44e5ecfd261afe72aa04eba4bf1a9ec782579cab commit r15-1865-g44e5ecfd261afe72aa04eba4bf1a9ec782579cab Author: Wilco Dijkstra Date: Fri Jul 5 17:31:25 2024 +0100 Arm: Fix ldrd offset range [PR115153] The valid offset range of LDRD in arm_legitimate_index_p is inc

[gcc r12-10603] AArch64: Fix strict-align cpymem/setmem [PR103100]

https://gcc.gnu.org/g:b9d16d8361a9e3a82a2f21e759e760d235d43322 commit r12-10603-gb9d16d8361a9e3a82a2f21e759e760d235d43322 Author: Wilco Dijkstra Date: Wed Oct 25 16:28:04 2023 +0100 AArch64: Fix strict-align cpymem/setmem [PR103100] The cpymemdi/setmemdi implementation doesn't ful

[gcc r14-10383] Arm: Fix disassembly error in Thumb-1 relaxed load/store [PR115188]

https://gcc.gnu.org/g:100d353e545564931efaac90a089a4e8f3d42e6e commit r14-10383-g100d353e545564931efaac90a089a4e8f3d42e6e Author: Wilco Dijkstra Date: Tue Jul 2 17:37:04 2024 +0100 Arm: Fix disassembly error in Thumb-1 relaxed load/store [PR115188] A Thumb-1 memory operand allows

[gcc r15-1786] Arm: Fix disassembly error in Thumb-1 relaxed load/store [PR115188]

https://gcc.gnu.org/g:d04c5537f5ae4a3acd3f5135347d7e2d8c218811 commit r15-1786-gd04c5537f5ae4a3acd3f5135347d7e2d8c218811 Author: Wilco Dijkstra Date: Tue Jul 2 17:37:04 2024 +0100 Arm: Fix disassembly error in Thumb-1 relaxed load/store [PR115188] A Thumb-1 memory operand allows s

[gcc r13-8874] AArch64: Fix strict-align cpymem/setmem [PR103100]

https://gcc.gnu.org/g:5aa9ed0f353f835005c3df8932c7bc6e26f53904 commit r13-8874-g5aa9ed0f353f835005c3df8932c7bc6e26f53904 Author: Wilco Dijkstra Date: Wed Oct 25 16:28:04 2023 +0100 AArch64: Fix strict-align cpymem/setmem [PR103100] The cpymemdi/setmemdi implementation doesn't full

[gcc r14-10338] AArch64: Fix cpu features initialization [PR115342]

https://gcc.gnu.org/g:9421f02916676d27e24fcda918f85e359329ac69 commit r14-10338-g9421f02916676d27e24fcda918f85e359329ac69 Author: Wilco Dijkstra Date: Wed Jun 5 14:04:33 2024 +0100 AArch64: Fix cpu features initialization [PR115342] The CPU features initialization code uses CPUID

[gcc r15-1036] AArch64: Fix cpu features initialization [PR115342]

https://gcc.gnu.org/g:d7cbcfe7c33645eaf95f175f19884d443817857b commit r15-1036-gd7cbcfe7c33645eaf95f175f19884d443817857b Author: Wilco Dijkstra Date: Wed Jun 5 14:04:33 2024 +0100 AArch64: Fix cpu features initialization [PR115342] The CPU features initialization code uses CPUID r

[gcc r15-1035] testsuite: Improve check-function-bodies

https://gcc.gnu.org/g:acdc9df371fbe99e814a3f35a439531e08af79e7 commit r15-1035-gacdc9df371fbe99e814a3f35a439531e08af79e7 Author: Wilco Dijkstra Date: Wed Jun 5 14:05:59 2024 +0100 testsuite: Improve check-function-bodies Improve check-function-bodies by allowing single-character f

[gcc r15-696] AArch64: Improve costing of ctz

https://gcc.gnu.org/g:e14c673ea9ab2eca5de4db91b478f0b5297ef321 commit r15-696-ge14c673ea9ab2eca5de4db91b478f0b5297ef321 Author: Wilco Dijkstra Date: Wed Apr 17 17:18:23 2024 +0100 AArch64: Improve costing of ctz Improve costing of ctz - both TARGET_CSSC and vector cases were not h

[gcc r15-695] AArch64: Fix printing of 2-instruction alternatives

https://gcc.gnu.org/g:804fa0bb92f8073394b3859edb810c3e23375530 commit r15-695-g804fa0bb92f8073394b3859edb810c3e23375530 Author: Wilco Dijkstra Date: Thu Apr 25 17:33:00 2024 +0100 AArch64: Fix printing of 2-instruction alternatives Add missing '\' in 2-instruction movsi/di alterna

[gcc r15-513] AArch64: Use UZP1 instead of INS

https://gcc.gnu.org/g:43fb827f259e6fdea39bc4021950c810be769d58 commit r15-513-g43fb827f259e6fdea39bc4021950c810be769d58 Author: Wilco Dijkstra Date: Wed May 15 13:07:27 2024 +0100 AArch64: Use UZP1 instead of INS Use UZP1 instead of INS when combining low and high halves of vector

[gcc r15-8] AArch64: Cleanup memset expansion

https://gcc.gnu.org/g:6b86f71165de9ee64fb76489c04ce032dd74ac21 commit r15-8-g6b86f71165de9ee64fb76489c04ce032dd74ac21 Author: Wilco Dijkstra Date: Wed Feb 21 23:34:37 2024 + AArch64: Cleanup memset expansion Cleanup memset implementation. Similar to memcpy/memmove, use an off

[gcc r15-7] AArch64: Remove AARCH64_EXTRA_TUNE_NO_LDP_STP_QREGS

https://gcc.gnu.org/g:768fbb56b3285b2a3cf067881e745e0f8caec215 commit r15-7-g768fbb56b3285b2a3cf067881e745e0f8caec215 Author: Wilco Dijkstra Date: Fri Apr 26 15:09:31 2024 +0100 AArch64: Remove AARCH64_EXTRA_TUNE_NO_LDP_STP_QREGS Remove the tune AARCH64_EXTRA_TUNE_NO_LDP_STP_QREGS

[gcc r15-6] libatomic: Cleanup macros in atomic_16.S

https://gcc.gnu.org/g:5716f8daf3f2abc54ececa61350fff0af2e7ce90 commit r15-6-g5716f8daf3f2abc54ececa61350fff0af2e7ce90 Author: Wilco Dijkstra Date: Tue Mar 26 15:42:16 2024 + libatomic: Cleanup macros in atomic_16.S Cleanup the macros to add the libat_ prefixes in atomic_16.S.

[gcc r14-9796] libatomic: Fix build for --disable-gnu-indirect-function [PR113986]

https://gcc.gnu.org/g:27b6d081f68528435066be2234c7329e31e0e84f commit r14-9796-g27b6d081f68528435066be2234c7329e31e0e84f Author: Wilco Dijkstra Date: Tue Mar 26 15:08:02 2024 + libatomic: Fix build for --disable-gnu-indirect-function [PR113986] Fix libatomic build to support -

[gcc r14-9776] libgcc: Add missing HWCAP entries to aarch64/cpuinfo.c

https://gcc.gnu.org/g:8f9e92eec3230d2f1305d414984e89aaebdfe0c6 commit r14-9776-g8f9e92eec3230d2f1305d414984e89aaebdfe0c6 Author: Wilco Dijkstra Date: Wed Mar 27 16:06:13 2024 + libgcc: Add missing HWCAP entries to aarch64/cpuinfo.c A few HWCAP entries are missing from aarch64/

[gcc r14-9394] ARM: Fix builtin-bswap-1.c test [PR113915]

https://gcc.gnu.org/g:5119c7927c70b02ab9768b30f40564480f556432 commit r14-9394-g5119c7927c70b02ab9768b30f40564480f556432 Author: Wilco Dijkstra Date: Fri Mar 8 15:01:15 2024 + ARM: Fix builtin-bswap-1.c test [PR113915] On Thumb-2 the use of CBZ blocks conditional execution, so

[gcc r14-9373] AArch64: memcpy/memset expansions should not emit LDP/STP [PR113618]

https://gcc.gnu.org/g:19b23bf3c32df3cbb96b3d898a1d7142f7bea4a0 commit r14-9373-g19b23bf3c32df3cbb96b3d898a1d7142f7bea4a0 Author: Wilco Dijkstra Date: Wed Feb 21 23:33:58 2024 + AArch64: memcpy/memset expansions should not emit LDP/STP [PR113618] The new RTL introduced for LDP/

[gcc r14-9343] ARM: Fix conditional execution [PR113915]

https://gcc.gnu.org/g:b575f37a342cebb954aa85fa45df0604bfa1ada9 commit r14-9343-gb575f37a342cebb954aa85fa45df0604bfa1ada9 Author: Wilco Dijkstra Date: Wed Mar 6 17:35:16 2024 + ARM: Fix conditional execution [PR113915] By default most patterns can be conditionalized on Arm targ