https://gcc.gnu.org/g:00e1be7b34f8c009938dde2cf9ca4374243a7a9e
commit r16-2395-g00e1be7b34f8c009938dde2cf9ca4374243a7a9e
Author: Jeff Law
Date: Mon Jul 21 15:58:12 2025 -0600
[RISC-V] Add missing insn types to xiangshan.md and mips-p8700.md
This is a trivial patch to add a few mis
https://gcc.gnu.org/g:d80498a7025750445dd21a21888bf8a5df158bb0
commit r15-10028-gd80498a7025750445dd21a21888bf8a5df158bb0
Author: Eric Botcazou
Date: Mon Jul 21 20:27:37 2025 +0200
Ada: Fix wrong tag in style check warnings
This fixes an old issue whereby violations of the style c
https://gcc.gnu.org/g:0b6ae75a304e58463796d1058a39cbe483283dee
commit r16-2394-g0b6ae75a304e58463796d1058a39cbe483283dee
Author: Eric Botcazou
Date: Mon Jul 21 20:27:37 2025 +0200
Ada: Fix wrong tag in style check warnings
This fixes an old issue whereby violations of the style ch
https://gcc.gnu.org/g:7c1d08860796d4c1ff6fc8c5e8e8462e9ee8f7fc
commit r16-2393-g7c1d08860796d4c1ff6fc8c5e8e8462e9ee8f7fc
Author: Robert Dubner
Date: Mon Jul 21 12:58:47 2025 -0400
cobol: Improved linemap and diagnostic handling; PIC validation. [PR120402]
Implementation of PICTURE
https://gcc.gnu.org/g:fa099f248e2462ecd5ab8b0cadd348aaf11bb093
commit r16-2392-gfa099f248e2462ecd5ab8b0cadd348aaf11bb093
Author: Andrew Pinski
Date: Sun Jul 20 11:21:08 2025 -0700
match: Add `cmp - 1` simplification to `-icmp` [PR110949]
I have seen this a few places though the te
https://gcc.gnu.org/g:dfab6593b05a65b5a475e0572e101bd56e3a2282
commit r16-2391-gdfab6593b05a65b5a475e0572e101bd56e3a2282
Author: Luc Grosheintz
Date: Mon Jul 21 13:07:37 2025 +0200
libstdc++: Make the default ctor of mdspan conditionally noexcept.
Previously, the default ctor of m
https://gcc.gnu.org/g:03437196942b03eee4f3f3edfaf201f5bdc37d9e
commit r16-2390-g03437196942b03eee4f3f3edfaf201f5bdc37d9e
Author: Luc Grosheintz
Date: Mon Jul 21 13:07:36 2025 +0200
libstdc++: Strengthen exception guarantee for mdspan methods.
The mdspan::is_{,always}_{unique,strid
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https://gcc.gnu.org/g:b8be49c928c9f81f1faa39d462880fc47a2b7d0c
commit r15-10027-gb8be49c928c9f81f1faa39d462880fc47a2b7d0c
Author: Richard Sandiford
Date: Mon Jul 21 15:41:05 2025 +0100
aarch64: Tweak handling of general SVE permutes [PR121027]
This PR is partly about a code qualit
https://gcc.gnu.org/g:a413f83cad6b0afdbbe26b9481e552abec3f5415
commit r15-10026-ga413f83cad6b0afdbbe26b9481e552abec3f5415
Author: Richard Sandiford
Date: Mon Jul 21 15:41:05 2025 +0100
aarch64: Fix LD1Q and ST1Q failures for big-endian
LD1Q gathers and ST1Q scatters are unusual in
https://gcc.gnu.org/g:24a6fe0effd973f077c7576315a0578c01288a38
commit r15-10024-g24a6fe0effd973f077c7576315a0578c01288a38
Author: Richard Sandiford
Date: Mon Jul 21 15:41:04 2025 +0100
aarch64: Extend HVLA permutations to big-endian
TARGET_VECTORIZE_VEC_PERM_CONST has code to matc
https://gcc.gnu.org/g:79a9996e162194e981ea0d058a134ebddafc30cf
commit r15-10025-g79a9996e162194e981ea0d058a134ebddafc30cf
Author: Richard Sandiford
Date: Mon Jul 21 15:41:04 2025 +0100
testsuite: Add -funwind-tables to sve*/pfalse* tests
The SVE svpfalse folding tests use CFI dire
https://gcc.gnu.org/g:abacc79405dfd8a5148f5a79397574ebae74c2d3
commit r15-10021-gabacc79405dfd8a5148f5a79397574ebae74c2d3
Author: Richard Sandiford
Date: Mon Jul 21 15:41:02 2025 +0100
Make the RTL frontend set REG_NREGS correctly
While working on a new testcase that uses the RTL
https://gcc.gnu.org/g:c2371624f436e078d507ed6877d40812cb2b703f
commit r15-10022-gc2371624f436e078d507ed6877d40812cb2b703f
Author: Richard Sandiford
Date: Mon Jul 21 15:41:02 2025 +0100
aarch64: Some fixes for SVE INDEX constants
When using SVE INDEX to load an Advanced SIMD vector
https://gcc.gnu.org/g:526efb6bfc148e1ca5d1ec7dd101cb18fdca5302
commit r15-10023-g526efb6bfc148e1ca5d1ec7dd101cb18fdca5302
Author: Richard Sandiford
Date: Mon Jul 21 15:41:03 2025 +0100
aarch64: Fix endianness of DFmode vector constants
aarch64_simd_valid_imm tries to decompose a c
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https://gcc.gnu.org/g:0b6038c17cabdbc8b9bfd0d13e2dd6f74db78734
commit r15-10020-g0b6038c17cabdbc8b9bfd0d13e2dd6f74db78734
Author: Richard Sandiford
Date: Mon Jul 21 15:41:01 2025 +0100
ext-dce: Fix subreg_lsb is_constant assumption (2)
This patch fixes another instance of the prob
https://gcc.gnu.org/g:eca9778fc8cabd032bbb68de3765aa45dabbc3e4
commit r15-10018-geca9778fc8cabd032bbb68de3765aa45dabbc3e4
Author: Richard Sandiford
Date: Mon Jul 21 15:41:00 2025 +0100
aarch64: Fix neon-sve-bridge.c failures for big-endian
Lowpart subregs are generally disallowed
https://gcc.gnu.org/g:d88c1b70a51513d11da7aca71a5d19363b5342a2
commit r15-10019-gd88c1b70a51513d11da7aca71a5d19363b5342a2
Author: Richard Sandiford
Date: Mon Jul 21 15:41:01 2025 +0100
aarch64: Fix ZIP1 order in aarch64_expand_vector_init [PR118891]
aarch64_expand_vector_init cont
https://gcc.gnu.org/g:9e8af6864b9fdfae109248a4d162bba9cc008b60
commit r15-10017-g9e8af6864b9fdfae109248a4d162bba9cc008b60
Author: Richard Sandiford
Date: Mon Jul 21 15:41:00 2025 +0100
ext-dce: Fix subreg_lsb is_constant assumption
ext-dce had:
if (SUBREG_P (dst
https://gcc.gnu.org/g:2363ea8392b603bb5fd196a220a76a510e1115f5
commit r15-10016-g2363ea8392b603bb5fd196a220a76a510e1115f5
Author: Richard Sandiford
Date: Mon Jul 21 15:40:59 2025 +0100
vect: Fix VEC_WIDEN_PLUS_HI/LO choice for big-endian [PR118891]
In the tree codes and optabs, th
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https://gcc.gnu.org/g:b441d735c092f5d60c4a9c7167ed9153003d49fa
commit r16-2389-gb441d735c092f5d60c4a9c7167ed9153003d49fa
Author: Andreas Schwab
Date: Wed Jul 16 14:48:51 2025 +0200
[RISC-V] Fix wrong CFA during stack probe
temp1 is used by the probe loop for the step size, but we
https://gcc.gnu.org/g:e184f73d91b437ba46e5eaf1817db6b182097627
commit r16-2387-ge184f73d91b437ba46e5eaf1817db6b182097627
Author: Pan Li
Date: Mon Jul 21 09:20:46 2025 +0800
RISC-V: Allow VLS DImode for sat_op vx DImode pattern
When try to introduce the vaaddu.vx combine for DImode
https://gcc.gnu.org/g:2d90c95f77a000410fdf781adf4c312dcf7d98cf
commit r16-2386-g2d90c95f77a000410fdf781adf4c312dcf7d98cf
Author: Pan Li
Date: Mon Jul 21 09:16:17 2025 +0800
RISC-V: Add test for vec_duplicate + vaaddu.vv combine case 1 with GR2VR
cost 0, 1 and 2 for QI, HI and SI mode
https://gcc.gnu.org/g:04cfb71957473c3c738e2900940a6781a3f0544d
commit r16-2385-g04cfb71957473c3c738e2900940a6781a3f0544d
Author: Pan Li
Date: Mon Jul 21 09:13:27 2025 +0800
RISC-V: Add test for vec_duplicate + vaaddu.vv combine case 0 with GR2VR
cost 0, 2 and 15 for QI, HI and SI mode
https://gcc.gnu.org/g:bd9fc3a53ff91b846b5999a91438f835e1ed64f5
commit r16-2388-gbd9fc3a53ff91b846b5999a91438f835e1ed64f5
Author: Pan Li
Date: Mon Jul 21 09:28:06 2025 +0800
RISC-V: Add test for vec_duplicate + vaaddu.vv combine for DImode
Add asm dump check and run test for vec_du
https://gcc.gnu.org/g:9e2aaaba47cf635169e9051c4e86f39d04c69f1d
commit r16-2384-g9e2aaaba47cf635169e9051c4e86f39d04c69f1d
Author: Pan Li
Date: Mon Jul 21 09:06:52 2025 +0800
RISC-V: Combine vec_duplicate + vaaddu.vv to vaaddu.vx on GR2VR cost for
HI, QI and SI mode
This patch woul
https://gcc.gnu.org/g:d14a5db124777b12fcaeada4236878031d5ca505
commit r16-2383-gd14a5db124777b12fcaeada4236878031d5ca505
Author: Kyrylo Tkachov
Date: Thu Jul 17 03:51:31 2025 -0700
aarch64: Avoid INS-(W|X)ZR instructions when optimising for speed
For inserting zero into a vector l
https://gcc.gnu.org/g:f87b632f98dc6d5cf8ed75d57d15adb8d7ffea6e
commit r16-2382-gf87b632f98dc6d5cf8ed75d57d15adb8d7ffea6e
Author: Kyrylo Tkachov
Date: Thu Jul 17 06:06:16 2025 -0700
aarch64: NFC - Make vec_* rtx costing logic consistent
The rtx costs logic for CONST_VECTOR, VEC_DUP
https://gcc.gnu.org/g:8ca85e95daca7f7c56d297fa7f2328e5385d446c
commit r16-2381-g8ca85e95daca7f7c56d297fa7f2328e5385d446c
Author: Richard Biener
Date: Mon Jul 21 12:48:45 2025 +0200
tree-optimization/121194 - check LC PHIs can be vectorized
With bools we can have the usual mismatch
https://gcc.gnu.org/g:47a7dcd4c027bcc98760043c3416aa354f42b40e
commit r16-2380-g47a7dcd4c027bcc98760043c3416aa354f42b40e
Author: Mikael Morin
Date: Tue Jul 15 19:09:21 2025 +0200
fortran: Fix indentation
gcc/fortran/ChangeLog:
* trans-decl.cc (gfc_trans_deferred_v
https://gcc.gnu.org/g:351fa55c58a036f148d13bca972e687a0bacd113
commit r16-2379-g351fa55c58a036f148d13bca972e687a0bacd113
Author: Andrew Stubbs
Date: Thu Jun 12 16:58:33 2025 +
amdgcn: add DImode offsets for gather/scatter
Add new variant of he gather_load and scatter_store ins
https://gcc.gnu.org/g:bdc4062a0796788e44d5e6ecd753268a8b453cc7
commit r16-2377-gbdc4062a0796788e44d5e6ecd753268a8b453cc7
Author: Andrew Stubbs
Date: Thu Jun 12 16:57:23 2025 +
amdgcn: add more insn patterns using vec_duplicate
These new insns allow more efficient use of scalar
https://gcc.gnu.org/g:f194924984c4eb9c8be5310f78b191b35e576ab8
commit r16-2378-gf194924984c4eb9c8be5310f78b191b35e576ab8
Author: Andrew Stubbs
Date: Thu Jun 12 16:54:01 2025 +
amdgcn: Add ashlvNm, mulvNm macros
I need some extra shift varieties in the mode-independent code, bu
https://gcc.gnu.org/g:a51c146ebce41b5e4326b222f2d9e04bb22d276f
commit r16-2374-ga51c146ebce41b5e4326b222f2d9e04bb22d276f
Author: Stefan Schulze Frielinghaus
Date: Mon Jul 21 13:05:26 2025 +0200
Hard register constraints
Implement hard register constraints of the form {regname} whe
https://gcc.gnu.org/g:cbf17db978c663817e4cd3337bbc80f59fa05bb6
commit r16-2375-gcbf17db978c663817e4cd3337bbc80f59fa05bb6
Author: Stefan Schulze Frielinghaus
Date: Mon Jul 21 13:05:26 2025 +0200
Error handling for hard register constraints
This implements error handling for hard re
https://gcc.gnu.org/g:9791950017c90c6dd2da773fbc2db98021226981
commit r16-2376-g9791950017c90c6dd2da773fbc2db98021226981
Author: Stefan Schulze Frielinghaus
Date: Mon Jul 21 13:05:26 2025 +0200
genoutput: Verify hard register constraints
Since genoutput has no information about ha
https://gcc.gnu.org/g:1eb17c6b20e662b4aa4b33e7e84ceccf6b6c41d8
commit r16-2373-g1eb17c6b20e662b4aa4b33e7e84ceccf6b6c41d8
Author: Richard Biener
Date: Mon Jul 21 10:40:13 2025 +0200
Remove bougs minimum VF compute
The following removes the minimum VF compute from dataref analysis
https://gcc.gnu.org/g:3a7fcf4f54ecffdbad03787d4f734c1fb2291ef5
commit r16-2372-g3a7fcf4f54ecffdbad03787d4f734c1fb2291ef5
Author: Andre Vehreschild
Date: Fri Jun 27 11:42:54 2025 +0200
Fortran: Allow for iterator substitution in array constructors [PR119106]
PR fortran/1191
https://gcc.gnu.org/g:8f41c87654fd819e48c9f6f1ac3d87e35794d310
commit r16-2371-g8f41c87654fd819e48c9f6f1ac3d87e35794d310
Author: Mikael Morin
Date: Mon Jul 21 10:31:35 2025 +0200
fortran: Factor array descriptor references
Save subexpressions of array descriptor references to vari
https://gcc.gnu.org/g:84ee229910f8b73d0fea8be6717cdd8257138d30
commit r16-2370-g84ee229910f8b73d0fea8be6717cdd8257138d30
Author: panciyan
Date: Mon Jul 21 01:41:31 2025 +
RISC-V: Add testcase for unsigned scalar SAT_ADD form 8 and form 9
This patch adds testcase for form8 and
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