[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] Refactor record_function_versions.

https://gcc.gnu.org/g:7363e569418ebe52a606c6e2078e07b475881ba0 commit 7363e569418ebe52a606c6e2078e07b475881ba0 Author: Alfie Richards Date: Thu Mar 27 14:12:06 2025 + Refactor record_function_versions. Renames record_function_versions to add_function_version, and make it e

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/118886] Refine when two insns are signaled as fusion candidates

https://gcc.gnu.org/g:477d40bc7f7a18c70471117c2324e5812b0ab9dc commit 477d40bc7f7a18c70471117c2324e5812b0ab9dc Author: Jeff Law Date: Thu Jul 3 06:44:31 2025 -0600 [RISC-V][PR target/118886] Refine when two insns are signaled as fusion candidates A number of folks have had their

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: testsuite: Skip tests providing -march/-mcpu for ILP32E/ILP64E ABIs

https://gcc.gnu.org/g:7c4170930735d592fa0c4244c3699f129d3910cf commit 7c4170930735d592fa0c4244c3699f129d3910cf Author: Dimitar Dimitrov Date: Fri Jun 20 20:57:15 2025 +0300 RISC-V: testsuite: Skip tests providing -march/-mcpu for ILP32E/ILP64E ABIs Some test cases explicitly set -

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped patterns [PR120356]

https://gcc.gnu.org/g:09f1fddc57b496abc27eb1a3f0cea96d0e22e388 commit 09f1fddc57b496abc27eb1a3f0cea96d0e22e388 Author: Alexey Merzlyakov Date: Wed Jul 2 11:29:00 2025 -0600 [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped patterns [PR120356] It corrects the shift type

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [committed] [PR rtl-optimization/120242] Fix SUBREG_PROMOTED_VAR_P after ext-dce's actions

https://gcc.gnu.org/g:102e91566d6f90ecd52f50c4a340d116dc8b1f1a commit 102e91566d6f90ecd52f50c4a340d116dc8b1f1a Author: Jeff Law Date: Mon Jun 30 14:38:33 2025 -0600 [committed] [PR rtl-optimization/120242] Fix SUBREG_PROMOTED_VAR_P after ext-dce's actions I've gone back and forth

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Correct CFA notes for stack-clash protection [PR120714]

https://gcc.gnu.org/g:76d99d9eb3a5830d0865ca27fa52644479c0e5a0 commit 76d99d9eb3a5830d0865ca27fa52644479c0e5a0 Author: Alexey Merzlyakov Date: Mon Jun 30 13:58:29 2025 -0600 [RISC-V] Correct CFA notes for stack-clash protection [PR120714] Fixes incorrect SP-addresses used in CFA n

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vssubu.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:c20878bc23d6b251877d0c9526f411f88ab5acec commit c20878bc23d6b251877d0c9526f411f88ab5acec Author: Pan Li Date: Fri Jun 27 09:09:08 2025 +0800 RISC-V: Add test for vec_duplicate + vssubu.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check test for

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vssubu.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:de5e9aa67d08dcdd0114608bc50097e3b4d54d91 commit de5e9aa67d08dcdd0114608bc50097e3b4d54d91 Author: Pan Li Date: Fri Jun 27 09:06:38 2025 +0800 RISC-V: Add test for vec_duplicate + vssubu.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check and run

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Reconcile the existing test due to cost model change

https://gcc.gnu.org/g:927d0cb43e27a0639ef0fd1a0115918da6894459 commit 927d0cb43e27a0639ef0fd1a0115918da6894459 Author: Pan Li Date: Fri Jun 27 11:35:18 2025 +0800 RISC-V: Reconcile the existing test due to cost model change The cost model change will make the default cost of vx to

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vssubu.vv to vssubu.vx on GR2VR cost

https://gcc.gnu.org/g:f6f8088e9b30bfba11fb570a540794173bf0c27b commit f6f8088e9b30bfba11fb570a540794173bf0c27b Author: Pan Li Date: Fri Jun 27 09:02:03 2025 +0800 RISC-V: Combine vec_duplicate + vssubu.vv to vssubu.vx on GR2VR cost This patch would like to combine the vec_duplicat

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Ignore -Oz for most rvv testcase [NFC]

https://gcc.gnu.org/g:4c823d938d2c8d1dd66871da31d15ffe4265a8bc commit 4c823d938d2c8d1dd66871da31d15ffe4265a8bc Author: Kito Cheng Date: Mon Jun 30 14:18:07 2025 +0800 RISC-V: Ignore -Oz for most rvv testcase [NFC] Most testcase in rvv folder already ignore -Oz, but some of them

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Primary vector pipeline model for sifive 7 series

https://gcc.gnu.org/g:13b49dd649ba46de1ca5731c7a5dcfe759f6f6e2 commit 13b49dd649ba46de1ca5731c7a5dcfe759f6f6e2 Author: Kito Cheng Date: Thu Jun 19 14:31:42 2025 +0800 RISC-V: Primary vector pipeline model for sifive 7 series This commit introduces a primary vector pipeline model f

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Adding B ext, fp16 and missing scalar instruction type for sifive-7 pipeline model [PR120659

https://gcc.gnu.org/g:71cc3ca6ac57deb06a999e209653c5db913b8037 commit 71cc3ca6ac57deb06a999e209653c5db913b8037 Author: Kito Cheng Date: Tue Jun 17 16:20:19 2025 +0800 RISC-V: Adding B ext, fp16 and missing scalar instruction type for sifive-7 pipeline model [PR120659] gcc/ChangeL

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Vector-scalar negate-multiply-(subtract-)accumulate [PR119100]

https://gcc.gnu.org/g:0be8dc16fba358c197b312b836a135cf75b9020c commit 0be8dc16fba358c197b312b836a135cf75b9020c Author: Paul-Antoine Arras Date: Thu Jun 26 13:20:49 2025 + RISC-V: Vector-scalar negate-multiply-(subtract-)accumulate [PR119100] This pattern enables the combine pa

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Refactor the function bitmap_union_of_preds_with_entry

https://gcc.gnu.org/g:6ce0821aa5ad174979d5fc15db606810b644c8eb commit 6ce0821aa5ad174979d5fc15db606810b644c8eb Author: Jin Ma Date: Sat Jun 28 19:55:00 2025 +0800 RISC-V: Refactor the function bitmap_union_of_preds_with_entry The current implementation of this function is somewhat

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add pipeline-checker script

https://gcc.gnu.org/g:101b601931434bdce9719b871feb85a1597b0292 commit 101b601931434bdce9719b871feb85a1597b0292 Author: Kito Cheng Date: Thu Jun 26 17:21:27 2025 +0800 RISC-V: Add pipeline-checker script Pipeline checker utility for RISC-V architecture that validates processor

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [sanitizer_common] Fix build on ppc64+musl (#120036)

https://gcc.gnu.org/g:822bd8f017e685471178fb1a2c8b21c2a0d642d8 commit 822bd8f017e685471178fb1a2c8b21c2a0d642d8 Author: Jeff Law Date: Fri Jun 27 15:11:41 2025 -0600 [sanitizer_common] Fix build on ppc64+musl (#120036) Cherry picked from LLVM commit 801b519dfd01e21da0be17aa8f8dc2ce

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/119971] Avoid losing shift count masking

https://gcc.gnu.org/g:5ad1aa3f754e62d023f75bb0ec2037f5cdab1448 commit 5ad1aa3f754e62d023f75bb0ec2037f5cdab1448 Author: Jeff Law Date: Fri Jun 27 07:00:15 2025 -0600 [RISC-V][PR target/119971] Avoid losing shift count masking Fix typo spotted by Bernhard Reutner-Fischer.

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: update prepare_ternary_operands to handle vector-scalar case [PR120828]

https://gcc.gnu.org/g:058acd7e8508ec11d4c17c8778912aba63498c4a commit 058acd7e8508ec11d4c17c8778912aba63498c4a Author: Paul-Antoine Arras Date: Wed Jun 25 16:42:00 2025 + RISC-V: update prepare_ternary_operands to handle vector-scalar case [PR120828] This is a followup to 92e

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix build issue

https://gcc.gnu.org/g:14c1c415325a2aa960e350a33fac5dd2eecdb153 commit 14c1c415325a2aa960e350a33fac5dd2eecdb153 Author: Kito Cheng Date: Thu Jun 26 14:35:47 2025 +0800 RISC-V: Fix build issue Apparently I forgot to squash this fix into the previous commit before I push...

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add comment and reorder the the include files in riscv.md [NFC]

https://gcc.gnu.org/g:329a20b72a12c9a1d6524c419371172eb7e96849 commit 329a20b72a12c9a1d6524c419371172eb7e96849 Author: Kito Cheng Date: Thu Jun 26 14:26:57 2025 +0800 RISC-V: Add comment and reorder the the include files in riscv.md [NFC] This patch adds a comment to the riscv.md

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add Profiles RVA/B23S64 support.

https://gcc.gnu.org/g:30bc81d98baf775d237d08068e82f065633404dd commit 30bc81d98baf775d237d08068e82f065633404dd Author: Jiawei Date: Tue Jun 24 17:34:05 2025 +0800 RISC-V: Add Profiles RVA/B23S64 support. This patch adds support for the RISC-V Profiles RVA23S64 and RVB23S64.

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add patterns for vector-scalar multiply-(subtract-)accumulate [PR119100]

https://gcc.gnu.org/g:7579e0cd3b61be067c823f1cea87bbefb5fb9d6f commit 7579e0cd3b61be067c823f1cea87bbefb5fb9d6f Author: Paul-Antoine Arras Date: Tue Jun 24 15:42:50 2025 -0600 RISC-V: Add patterns for vector-scalar multiply-(subtract-)accumulate [PR119100] This pattern enables the

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/118241] Fix data prefetch predicate/constraint for RISC-V

https://gcc.gnu.org/g:a0cca3923d6233d373e4ab2b56fff5c674dd9224 commit a0cca3923d6233d373e4ab2b56fff5c674dd9224 Author: Jeff Law Date: Mon Jun 23 18:27:49 2025 -0600 [RISC-V][PR target/118241] Fix data prefetch predicate/constraint for RISC-V Fix typo in comment spotted by Peter B.

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vsaddu.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:0378e1e4efed98f9c6e111e2e63b546c7c66979c commit 0378e1e4efed98f9c6e111e2e63b546c7c66979c Author: Pan Li Date: Sat Jun 21 10:07:38 2025 +0800 RISC-V: Add test for vec_duplicate + vsaddu.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check test for

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vsaddu.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:26cde1e545b49f7a4bc2a1c5b46198c087be828c commit 26cde1e545b49f7a4bc2a1c5b46198c087be828c Author: Pan Li Date: Sat Jun 21 09:10:07 2025 +0800 RISC-V: Add test for vec_duplicate + vsaddu.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check and run

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vsaddu.vv to vsaddu.vx on GR2VR cost

https://gcc.gnu.org/g:28a7e66cafd789919225b440b38e85bc4cf1d048 commit 28a7e66cafd789919225b440b38e85bc4cf1d048 Author: Pan Li Date: Sat Jun 21 09:00:16 2025 +0800 RISC-V: Combine vec_duplicate + vsaddu.vv to vsaddu.vx on GR2VR cost This patch would like to combine the vec_duplicat

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/119830] Fix RISC-V codegen on 32bit hosts

https://gcc.gnu.org/g:5ccee5646b67e249d44d38a67b36b2bff6129ef3 commit 5ccee5646b67e249d44d38a67b36b2bff6129ef3 Author: Andrew Pinski Date: Sun Jun 22 12:35:19 2025 -0600 [RISC-V][PR target/119830] Fix RISC-V codegen on 32bit hosts So this is Andrew's patch from the PR. We weren't

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/118241] Fix data prefetch predicate/constraint for RISC-V

https://gcc.gnu.org/g:30e7306b74952c673517e5f686faeb8afce8395d commit 30e7306b74952c673517e5f686faeb8afce8395d Author: Jeff Law Date: Sat Jun 21 08:24:58 2025 -0600 [RISC-V][PR target/118241] Fix data prefetch predicate/constraint for RISC-V The RISC-V prefetch support is broken i

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix ICE for expand_select_vldi [PR120652]

https://gcc.gnu.org/g:6c397a7977e26f19757ed1182994af2cfdc3d22f commit 6c397a7977e26f19757ed1182994af2cfdc3d22f Author: Pan Li Date: Thu Jun 19 18:58:17 2025 +0800 RISC-V: Fix ICE for expand_select_vldi [PR120652] The will be one ICE when expand pass, the bt similar as below.

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Force several tests to use rocket tuning

https://gcc.gnu.org/g:4431d2438c05ae2e1c54eb0e6ae4a35c744dc20a commit 4431d2438c05ae2e1c54eb0e6ae4a35c744dc20a Author: Jeff Law Date: Thu Jun 19 20:58:56 2025 -0600 [RISC-V] Force several tests to use rocket tuning My tester has been flagging these regressions since the default co

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Use builtin clz/ctz when count_leading_zeros and count_trailing_zeros is used

https://gcc.gnu.org/g:2ea35c173f5af1599ead63b05eeec1e317fef7bd commit 2ea35c173f5af1599ead63b05eeec1e317fef7bd Author: Sosutha Sethuramapandian Date: Thu Jun 19 20:53:56 2025 -0600 [PATCH] RISC-V: Use builtin clz/ctz when count_leading_zeros and count_trailing_zeros is used longl

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vminu.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:7ec437266df8d719d18f5ddc60ef5207b479cdbc commit 7ec437266df8d719d18f5ddc60ef5207b479cdbc Author: Pan Li Date: Thu Jun 19 10:49:07 2025 +0800 RISC-V: Add test for vec_duplicate + vminu.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check test for v

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vminu.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:1b7fcb4495f2d6dcf999f92781c21ccc2d1b58a0 commit 1b7fcb4495f2d6dcf999f92781c21ccc2d1b58a0 Author: Pan Li Date: Thu Jun 19 10:47:33 2025 +0800 RISC-V: Add test for vec_duplicate + vminu.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check and run t

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vminu.vv to vminu.vx on GR2VR cost

https://gcc.gnu.org/g:34c5807cee5a608e4321facb1ae5f8badd012c83 commit 34c5807cee5a608e4321facb1ae5f8badd012c83 Author: Pan Li Date: Thu Jun 19 10:44:14 2025 +0800 RISC-V: Combine vec_duplicate + vminu.vv to vminu.vx on GR2VR cost This patch would like to combine the vec_duplicate

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add generic tune as default.

https://gcc.gnu.org/g:d2b21c2620e40d2da95a8538c799c278843dff60 commit d2b21c2620e40d2da95a8538c799c278843dff60 Author: Dongyan Chen Date: Wed Jun 18 19:47:28 2025 +0800 RISC-V: Add generic tune as default. According to the discussion in https://gcc.gnu.org/pipermail/gcc-patche

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Use riscv_2x_xlen_mode_p [NFC]

https://gcc.gnu.org/g:3becefcb2e74d5047a15e81563421368a9b03ad0 commit 3becefcb2e74d5047a15e81563421368a9b03ad0 Author: Kito Cheng Date: Tue Jun 17 13:01:01 2025 +0800 RISC-V: Use riscv_2x_xlen_mode_p [NFC] Use riscv_v_ext_mode_p to check the mode size is 2x XLEN, instead of us

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Adding cost model for zilsd

https://gcc.gnu.org/g:f4beb3460b90efefade6daf5c50cf74633b2ce19 commit f4beb3460b90efefade6daf5c50cf74633b2ce19 Author: Kito Cheng Date: Tue Jun 17 12:56:17 2025 +0800 RISC-V: Adding cost model for zilsd Motivation of this patch is we want to use ld/sd if possible when zilsd is

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vmin.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:16a379bb686a4debb877b8cd5598381959183727 commit 16a379bb686a4debb877b8cd5598381959183727 Author: Pan Li Date: Tue Jun 17 10:08:44 2025 +0800 RISC-V: Add test for vec_duplicate + vmin.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check test for ve

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vmin.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:7ad53e8abcaebe37bb355079d5c4d83ce34d4fcd commit 7ad53e8abcaebe37bb355079d5c4d83ce34d4fcd Author: Pan Li Date: Tue Jun 17 10:05:33 2025 +0800 RISC-V: Add test for vec_duplicate + vmin.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check and run te

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vmin.vv to vmin.vx on GR2VR cost

https://gcc.gnu.org/g:b7ccbdc0d5a272597271d88ec3176e0ab11f9fcf commit b7ccbdc0d5a272597271d88ec3176e0ab11f9fcf Author: Pan Li Date: Tue Jun 17 10:00:54 2025 +0800 RISC-V: Combine vec_duplicate + vmin.vv to vmin.vx on GR2VR cost This patch would like to combine the vec_duplicate +

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH v1] RISC-V: Use scratch reg for loop control

https://gcc.gnu.org/g:a97eb08ac396591338b40f81be27ead5a498a1be commit a97eb08ac396591338b40f81be27ead5a498a1be Author: Umesh Kalappa Date: Tue Jun 17 07:23:41 2025 -0600 [PATCH v1] RISC-V: Use scratch reg for loop control By using the scratch register for loop control rather than

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add -fno-pie flags to testcases

https://gcc.gnu.org/g:9fe9f65082c770a91775131ffc69b2ecf47cd9e4 commit 9fe9f65082c770a91775131ffc69b2ecf47cd9e4 Author: Kito Cheng Date: Tue Jun 17 12:52:00 2025 +0800 RISC-V: Add -fno-pie flags to testcases PIE may cause some code gen difference in the testcases, that will cause

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Refine VX combine test case 0 to avoid code duplication

https://gcc.gnu.org/g:5abb21b4d9c59c735355ac0abd4dd05cf441038d commit 5abb21b4d9c59c735355ac0abd4dd05cf441038d Author: Pan Li Date: Sun Jun 15 16:28:38 2025 +0800 RISC-V: Refine VX combine test case 0 to avoid code duplication The case 0 for vx combine def functions are most the s

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Update Profiles string in RV23.

https://gcc.gnu.org/g:9f15440c022ca9a0266445a665f7e07415817d10 commit 9f15440c022ca9a0266445a665f7e07415817d10 Author: Jiawei Date: Mon Jun 16 11:21:29 2025 +0800 RISC-V: Update Profiles string in RV23. Add b-ext in RVA/B23 as independent extension flags and add supm in RVA23.

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vmaxu.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:05bc63f38afa102e6766d9abb52db3174a4e4153 commit 05bc63f38afa102e6766d9abb52db3174a4e4153 Author: Pan Li Date: Sat Jun 14 22:34:36 2025 +0800 RISC-V: Add test for vec_duplicate + vmaxu.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check test for v

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vmaxu.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:a0d1d0c39fd5d9f54ec94a94dc05fa41ddeef0fd commit a0d1d0c39fd5d9f54ec94a94dc05fa41ddeef0fd Author: Pan Li Date: Sat Jun 14 22:32:23 2025 +0800 RISC-V: Add test for vec_duplicate + vmaxu.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check test for

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vmaxu.vv to vmaxu.vx on GR2VR cost

https://gcc.gnu.org/g:4af1a958a3d8a413e3b01a1bfe2d493db3ec1e69 commit 4af1a958a3d8a413e3b01a1bfe2d493db3ec1e69 Author: Pan Li Date: Sat Jun 14 22:29:40 2025 +0800 RISC-V: Combine vec_duplicate + vmaxu.vv to vmaxu.vx on GR2VR cost This patch would like to combine the vec_duplicate

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_dup + vmax.vv combine case 1 with max func 1 and GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:31baabf7b56938c96dbc6b68781c7da932d76706 commit 31baabf7b56938c96dbc6b68781c7da932d76706 Author: Pan Li Date: Thu Jun 12 10:42:39 2025 +0800 RISC-V: Add test for vec_dup + vmax.vv combine case 1 with max func 1 and GR2VR cost 0, 1 and 2 Add asm dump check te

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_dup + vmax.vv combine case 1 with max func 0 and GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:0363f535e1721362c539bc1462bd7296110c4f15 commit 0363f535e1721362c539bc1462bd7296110c4f15 Author: Pan Li Date: Thu Jun 12 10:23:49 2025 +0800 RISC-V: Add test for vec_dup + vmax.vv combine case 1 with max func 0 and GR2VR cost 0, 1 and 2 Add asm dump check te

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_dup + vmax.vv combine case 0 with max func 1 and GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:b0d572cc865bafacf07569608a47702158f0e4b6 commit b0d572cc865bafacf07569608a47702158f0e4b6 Author: Pan Li Date: Thu Jun 12 09:12:09 2025 +0800 RISC-V: Add test for vec_dup + vmax.vv combine case 0 with max func 1 and GR2VR cost 0, 2 and 15 Add asm dump check t

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_dup + vmax.vv combine case 0 with max func 0 and GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:308422b0ad1d1afe26dec32267bcb16717e7956a commit 308422b0ad1d1afe26dec32267bcb16717e7956a Author: Pan Li Date: Wed Jun 11 21:51:08 2025 +0800 RISC-V: Add test for vec_dup + vmax.vv combine case 0 with max func 0 and GR2VR cost 0, 2 and 15 Add asm dump check t

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vmax.vv to vmax.vx on GR2VR cost

https://gcc.gnu.org/g:c545dd72fa764910665fefb0c61f27f6899585dc commit c545dd72fa764910665fefb0c61f27f6899585dc Author: Pan Li Date: Wed Jun 11 21:49:21 2025 +0800 RISC-V: Combine vec_duplicate + vmax.vv to vmax.vx on GR2VR cost This patch would like to combine the vec_duplicate +

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Prevent speculative vsetvl insn scheduling

https://gcc.gnu.org/g:48eaa967b283bc3a176f42bd95b43e9f45a9a5a1 commit 48eaa967b283bc3a176f42bd95b43e9f45a9a5a1 Author: Edwin Lu Date: Tue Jun 10 13:26:42 2025 -0700 RISC-V: Prevent speculative vsetvl insn scheduling The instruction scheduler appears to be speculatively hoisting vs

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add patterns for vector-scalar negate-(multiply-add/sub) [PR119100]

https://gcc.gnu.org/g:ec9f7a560d41c559fe737b3d20ae0fddf6f89d43 commit ec9f7a560d41c559fe737b3d20ae0fddf6f89d43 Author: Paul-Antoine Arras Date: Wed Jun 4 14:51:17 2025 +0200 RISC-V: Add patterns for vector-scalar negate-(multiply-add/sub) [PR119100] This pattern enables the combin

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: testsuite: fix an obvious build error

https://gcc.gnu.org/g:7469cb55ae36b7ef81c434224a295e46dd25dd75 commit 7469cb55ae36b7ef81c434224a295e46dd25dd75 Author: Vineet Gupta Date: Tue May 20 14:15:53 2025 -0700 RISC-V: testsuite: fix an obvious build error For a non-multilib build, I see following errors. | FAIL:

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vremu.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:e72e3b926b29d3f25275571c272d4be5942e88e1 commit e72e3b926b29d3f25275571c272d4be5942e88e1 Author: Pan Li Date: Mon Jun 9 16:35:47 2025 +0800 RISC-V: Add test for vec_duplicate + vremu.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check test for ve

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Regen riscv-ext.texi [NFC]

https://gcc.gnu.org/g:01bbac9924313e607dfbeb7829e47f8ae414d798 commit 01bbac9924313e607dfbeb7829e47f8ae414d798 Author: Kito Cheng Date: Tue Jun 10 10:32:37 2025 +0800 RISC-V: Regen riscv-ext.texi [NFC] Regenerates the `riscv-ext.texi` file in the GCC documentation. gcc/Ch

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vremu.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:1b74e831ce9278a3c373257aad96c5a3c0646a8c commit 1b74e831ce9278a3c373257aad96c5a3c0646a8c Author: Pan Li Date: Mon Jun 9 16:33:52 2025 +0800 RISC-V: Add test for vec_duplicate + vremu.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check test for v

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Reconcile the existing test for vremu.vx combine

https://gcc.gnu.org/g:0cb8e0fe7bb958ead81169ca7734c8d999581809 commit 0cb8e0fe7bb958ead81169ca7734c8d999581809 Author: Pan Li Date: Mon Jun 9 16:28:50 2025 +0800 RISC-V: Reconcile the existing test for vremu.vx combine Some existing vrem related test need some adjust for the a

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vremu.vv to vremu.vx on GR2VR cost

https://gcc.gnu.org/g:3a987c790f382094986211c1160474bee1b9500c commit 3a987c790f382094986211c1160474bee1b9500c Author: Pan Li Date: Mon Jun 9 16:24:34 2025 +0800 RISC-V: Combine vec_duplicate + vremu.vv to vremu.vx on GR2VR cost This patch would like to combine the vec_duplicate +

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Enable more if-conversion on RISC-V

https://gcc.gnu.org/g:dc318d114473b1f82094cfbb06fc8e9c20529eb6 commit dc318d114473b1f82094cfbb06fc8e9c20529eb6 Author: Jeff Law Date: Mon Jun 9 06:55:21 2025 -0600 [RISC-V] Enable more if-conversion on RISC-V Another czero related adjustment. This time in costing of conditional m

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vrem.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:c3c93b381d6f4dd9a7e4e5ccab2dc6a43620e4fa commit c3c93b381d6f4dd9a7e4e5ccab2dc6a43620e4fa Author: Pan Li Date: Sun Jun 8 16:55:34 2025 +0800 RISC-V: Add test for vec_duplicate + vrem.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check test for vec

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vrem.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:19ad8d19e243119071580bbac7cbc6fcbc87291b commit 19ad8d19e243119071580bbac7cbc6fcbc87291b Author: Pan Li Date: Sun Jun 8 16:53:05 2025 +0800 RISC-V: Add test for vec_duplicate + vrem.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check test for ve

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Reconcile the existing test for vrem.vx combine

https://gcc.gnu.org/g:d981ce1e532a19095327f1b0ee1936674a695a24 commit d981ce1e532a19095327f1b0ee1936674a695a24 Author: Pan Li Date: Sun Jun 8 16:50:52 2025 +0800 RISC-V: Reconcile the existing test for vrem.vx combine Some existing vrem related test need some adjust for the as

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vrem.vv to vrem.vx on GR2VR cost

https://gcc.gnu.org/g:0a7f235bca372fbd64f99c906738559c4d73d6b1 commit 0a7f235bca372fbd64f99c906738559c4d73d6b1 Author: Pan Li Date: Sun Jun 8 16:48:33 2025 +0800 RISC-V: Combine vec_duplicate + vrem.vv to vrem.vx on GR2VR cost This patch would like to combine the vec_duplicate + v

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: frm/mode-switch: robustify call_insn backtracking [PR120203]

https://gcc.gnu.org/g:377099337a92d675beaa3cc0b259b42da8a6674c commit 377099337a92d675beaa3cc0b259b42da8a6674c Author: Vineet Gupta Date: Sun Jun 8 14:55:11 2025 -0700 RISC-V: frm/mode-switch: robustify call_insn backtracking [PR120203] As described in prior patches of this series

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: frm/mode-switch: Reduce FRM restores on DYN transition [PR119164]

https://gcc.gnu.org/g:64b1aa9700e3774cd6330145ed0141f5ad32265b commit 64b1aa9700e3774cd6330145ed0141f5ad32265b Author: Vineet Gupta Date: Sun Jun 8 14:55:01 2025 -0700 RISC-V: frm/mode-switch: Reduce FRM restores on DYN transition [PR119164] FRM mode switching state machine has DY

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: frm/mode-switch: remove dubious frm edge insertion before call_insn

https://gcc.gnu.org/g:2d2ea246a56eb095f7d222ca6ead31afeefbb7f1 commit 2d2ea246a56eb095f7d222ca6ead31afeefbb7f1 Author: Vineet Gupta Date: Sun Jun 8 14:54:37 2025 -0700 RISC-V: frm/mode-switch: remove dubious frm edge insertion before call_insn This showed up when debugging the tes

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [to-be-committed][RISC-V] Handle 32bit operands in condition for conditional moves

https://gcc.gnu.org/g:2283c7eebec98d08b1a5b8073c98a57b895bd1f0 commit 2283c7eebec98d08b1a5b8073c98a57b895bd1f0 Author: Jeff Law Date: Sat Jun 7 07:48:46 2025 -0600 [to-be-committed][RISC-V] Handle 32bit operands in condition for conditional moves So here's the next chunk of condi

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: frm/mode-switch: remove TARGET_MODE_CONFLUENCE

https://gcc.gnu.org/g:41313acdf0df8392620b1a4a874ef59860c842d4 commit 41313acdf0df8392620b1a4a874ef59860c842d4 Author: Vineet Gupta Date: Sun Jun 8 14:44:29 2025 -0700 RISC-V: frm/mode-switch: remove TARGET_MODE_CONFLUENCE This is effectively reverting e5d1f538bb7d "(RISC-V: A

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Handle 32bit operands in condition for conditional moves

https://gcc.gnu.org/g:96541e6bbc01c3f87c0499a731c8e78ab78f2eed commit 96541e6bbc01c3f87c0499a731c8e78ab78f2eed Author: Shreya Munnangi Date: Sun Jun 8 08:42:53 2025 -0600 [RISC-V] Handle 32bit operands in condition for conditional moves So here's the next chunk of conditional move

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Improve sequences to generate -1, 1 in some cases.

https://gcc.gnu.org/g:957f90a5a5697594943c954e050f9b7772a53653 commit 957f90a5a5697594943c954e050f9b7772a53653 Author: Jeff Law Date: Thu Jun 5 06:17:25 2025 -0600 [RISC-V] Improve sequences to generate -1, 1 in some cases. This patch has a minor improvement to if-converted sequen

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support Ssu64xl extension.

https://gcc.gnu.org/g:a8537f7d2feae1b0a27a1c59557c4e2a4f2fb6df commit a8537f7d2feae1b0a27a1c59557c4e2a4f2fb6df Author: Jiawei Date: Thu Jun 5 13:59:14 2025 +0800 RISC-V: Support Ssu64xl extension. Support the Ssu64xl extension, which requires UXLEN to be 64. gcc/ChangeLog

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Reconcile the existing test for vdivu.vx combine

https://gcc.gnu.org/g:71cc2009cf41bbefeb8365f93e49397b83408ca6 commit 71cc2009cf41bbefeb8365f93e49397b83408ca6 Author: Pan Li Date: Fri Jun 6 10:03:50 2025 +0800 RISC-V: Reconcile the existing test for vdivu.vx combine Some existing vdiv related test need some adjust for the a

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support Sstvecd extension.

https://gcc.gnu.org/g:8b3cd36ed7b003744ad64969409bda66c2681965 commit 8b3cd36ed7b003744ad64969409bda66c2681965 Author: Jiawei Date: Thu Jun 5 13:52:08 2025 +0800 RISC-V: Support Sstvecd extension. Support the Sstvecd extension, which allows Supervisor Trap Vector Base Address

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vdivu.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:275b04ce6ed9b40cd097aad866d95776a8c9f5fc commit 275b04ce6ed9b40cd097aad866d95776a8c9f5fc Author: Pan Li Date: Fri Jun 6 09:51:10 2025 +0800 RISC-V: Add test for vec_duplicate + vdivu.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check test for ve

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vdivu.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:cffd80f31becf9d5811beb4ae3e0508a1ec07d32 commit cffd80f31becf9d5811beb4ae3e0508a1ec07d32 Author: Pan Li Date: Fri Jun 6 09:49:56 2025 +0800 RISC-V: Add test for vec_duplicate + vdivu.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check test for v

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support Smrnmi extension.

https://gcc.gnu.org/g:a6a08cd21342f5d29f910b4393cfef4484842268 commit a6a08cd21342f5d29f910b4393cfef4484842268 Author: Jiawei Date: Thu Jun 5 11:24:43 2025 +0800 RISC-V: Support Smrnmi extension. Support the Smrnmi extension, which provides new CSRs for Machine mode Non-Maskab

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vidvu.vv to vdivu.vx on GR2VR cost

https://gcc.gnu.org/g:bcdf931b7f9452bcd2ddeff8ee3515710f591d02 commit bcdf931b7f9452bcd2ddeff8ee3515710f591d02 Author: Pan Li Date: Fri Jun 6 09:33:21 2025 +0800 RISC-V: Combine vec_duplicate + vidvu.vv to vdivu.vx on GR2VR cost This patch would like to combine the vec_duplicate +

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support Sm/scsrind extensions.

https://gcc.gnu.org/g:883e1d8636f9d0a3c95a2293f9b65a55a5692aee commit 883e1d8636f9d0a3c95a2293f9b65a55a5692aee Author: Jiawei Date: Thu Jun 5 10:16:19 2025 +0800 RISC-V: Support Sm/scsrind extensions. Support the Sm/scsrind extensions, which provide indirect access to machine-

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support -mcpu for XiangShan Kunminghu cpu.

https://gcc.gnu.org/g:27bee9e37c22a5cab75d1fa237b68f45c8f533a4 commit 27bee9e37c22a5cab75d1fa237b68f45c8f533a4 Author: Jiawei Date: Wed Jun 4 17:56:49 2025 +0800 RISC-V: Support -mcpu for XiangShan Kunminghu cpu. This patch adds support for the XiangShan Kunminghu CPU in GCC, allo

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH v2] RISC-V: Add svbare extension.

https://gcc.gnu.org/g:05a5edf835609fe6167c87b224722bbec930a5a0 commit 05a5edf835609fe6167c87b224722bbec930a5a0 Author: Dongyan Chen Date: Wed Jun 4 07:57:01 2025 -0600 [PATCH v2] RISC-V: Add svbare extension. This patch support svbare extension, which is an extension in RVA23 prof

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Improve signed division by 2^n

https://gcc.gnu.org/g:7e1fbe76b4bd5a47a4757f04d04a907dd24a392e commit 7e1fbe76b4bd5a47a4757f04d04a907dd24a392e Author: Jeff Law Date: Thu Jun 5 16:58:45 2025 -0600 [RISC-V] Improve signed division by 2^n So another class of cases where we can do better than a zicond sequence. Li

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Don't use structured binding in riscv-common.cc

https://gcc.gnu.org/g:8af974e2760cfec87dfc131d21b4638ff18396da commit 8af974e2760cfec87dfc131d21b4638ff18396da Author: Kito Cheng Date: Thu Jun 5 15:23:59 2025 +0800 RISC-V: Don't use structured binding in riscv-common.cc It's new C++ language feature introduced in C++17, which is

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix ICE for gcc.dg/graphite/pr33576.c with rv32gcv

https://gcc.gnu.org/g:7c466824557dd18cb5cdd30de910c3f689595015 commit 7c466824557dd18cb5cdd30de910c3f689595015 Author: Pan Li Date: Thu Jun 5 11:04:33 2025 +0800 RISC-V: Fix ICE for gcc.dg/graphite/pr33576.c with rv32gcv The div of rvv has not such insn v2 = div (vec_dup (x), v1),

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support Sstvala extension.

https://gcc.gnu.org/g:596f77fd35a842bf7d26714600dda5374b22230c commit 596f77fd35a842bf7d26714600dda5374b22230c Author: Jiawei Date: Thu Jun 5 13:46:39 2025 +0800 RISC-V: Support Sstvala extension. Support the Sstvala extension, which provides all needed values in Supervisor Tr

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support Sscounterenw extension.

https://gcc.gnu.org/g:ef7643fdd57919b4cd505f99727717a231044baa commit ef7643fdd57919b4cd505f99727717a231044baa Author: Jiawei Date: Thu Jun 5 13:33:21 2025 +0800 RISC-V: Support Sscounterenw extension. Support the Sscounterenw extension, which allows writeable enables for any

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support Ssccptr extension.

https://gcc.gnu.org/g:bb1262aecd3d3ec74548b6adbf3d2d9cbd311ee0 commit bb1262aecd3d3ec74548b6adbf3d2d9cbd311ee0 Author: Jiawei Date: Thu Jun 5 13:15:02 2025 +0800 RISC-V: Support Ssccptr extension. Support the Ssccptr extension, which allows the main memory to support page tabl

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Update extension defination.

https://gcc.gnu.org/g:3454cdaceaf5581c21425f3fab543d03609432b9 commit 3454cdaceaf5581c21425f3fab543d03609432b9 Author: Jiawei Date: Thu Jun 5 09:38:40 2025 +0800 RISC-V: Update extension defination. Update the defination of RISC-V extensions in riscv-ext.def. gcc/ChangeLo

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Imply zicsr for svade and svadu extensions.

https://gcc.gnu.org/g:ac488b634bed5da6c765c51d88af5166bc99c0f5 commit ac488b634bed5da6c765c51d88af5166bc99c0f5 Author: Dongyan Chen Date: Wed Jun 4 08:03:31 2025 -0600 [PATCH] RISC-V: Imply zicsr for svade and svadu extensions. This patch implies zicsr for svade and svadu extensio

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Leverage get_vector_binary_rtx_cost to avoid code dup [NFC]

https://gcc.gnu.org/g:521f66aafac7bb1bc4e5fc90e6c378759dd100e9 commit 521f66aafac7bb1bc4e5fc90e6c378759dd100e9 Author: Pan Li Date: Wed Jun 4 11:06:52 2025 +0800 RISC-V: Leverage get_vector_binary_rtx_cost to avoid code dup [NFC] Some similar code could be wrapped to func get_vect

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add Shlcofideleg extension.

https://gcc.gnu.org/g:2626c7939d06f44e5331ef83e2df8482172f74cd commit 2626c7939d06f44e5331ef83e2df8482172f74cd Author: Jiawei Date: Tue May 27 14:37:03 2025 +0800 RISC-V: Add Shlcofideleg extension. This patch add the RISC-V Shlcofideleg extension. It supports delegating LCOFI

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Reconcile the existing test for vdiv.vx combine

https://gcc.gnu.org/g:e77de752d5e9084e362a396ee2e25d749300ca46 commit e77de752d5e9084e362a396ee2e25d749300ca46 Author: Pan Li Date: Mon Jun 2 21:21:18 2025 +0800 RISC-V: Reconcile the existing test for vdiv.vx combine Some existing vdiv related test need some adjust for the as

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vdiv.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:d712389ebaa718a05e50defb47e1144be4e37c9c commit d712389ebaa718a05e50defb47e1144be4e37c9c Author: Pan Li Date: Mon Jun 2 17:01:27 2025 +0800 RISC-V: Add test for vec_duplicate + vdiv.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check test for ve

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vdiv.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:0eed1400cd5e3601b8632a412e99efffb067170f commit 0eed1400cd5e3601b8632a412e99efffb067170f Author: Pan Li Date: Mon Jun 2 17:03:02 2025 +0800 RISC-V: Add test for vec_duplicate + vdiv.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check test for vec

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vidv.vv to vdiv.vx on GR2VR cost

https://gcc.gnu.org/g:c89fb8256f5a2dd26a43534c740651134dce041c commit c89fb8256f5a2dd26a43534c740651134dce041c Author: Pan Li Date: Mon Jun 2 16:56:59 2025 +0800 RISC-V: Combine vec_duplicate + vidv.vv to vdiv.vx on GR2VR cost This patch would like to combine the vec_duplicate + v

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Use helper function to get FPR to VR move cost

https://gcc.gnu.org/g:3341d68c0cc74ee80f735507908d7e5346204b3a commit 3341d68c0cc74ee80f735507908d7e5346204b3a Author: Paul-Antoine Arras Date: Wed May 28 12:09:22 2025 +0200 RISC-V: Use helper function to get FPR to VR move cost Since last patch introduced get_fr2vr_cost () to ge

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Add smcntrpmf extension.

https://gcc.gnu.org/g:b9095455dc9ca7f886c669ef8c735ef3d179c89c commit b9095455dc9ca7f886c669ef8c735ef3d179c89c Author: Dongyan Chen Date: Mon Jun 2 13:30:29 2025 -0600 [PATCH] RISC-V: Add smcntrpmf extension. This patch support smcntrpmf extension[1]. To enable GCC to recogniz

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add pattern for vector-scalar multiply-add/sub [PR119100]

https://gcc.gnu.org/g:8db0209785a8157b7bc6e534a00462dd30f3043f commit 8db0209785a8157b7bc6e534a00462dd30f3043f Author: Paul-Antoine Arras Date: Mon May 12 14:42:24 2025 +0200 RISC-V: Add pattern for vector-scalar multiply-add/sub [PR119100] This pattern enables the combine pass (o

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