[gcc(refs/users/meissner/heads/work211-cmodel)] PR target/120681 - allow -mcmodel=large with prefixed addressing

https://gcc.gnu.org/g:135d58ec84186008b82a11f851a8e19326d964d6 commit 135d58ec84186008b82a11f851a8e19326d964d6 Author: Michael Meissner Date: Tue Jun 17 02:45:03 2025 -0400 PR target/120681 - allow -mcmodel=large with prefixed addressing When I implemented the pc-relative support

[gcc(refs/users/meissner/heads/work211-cmodel)] Revert changes

https://gcc.gnu.org/g:198bc68c21dcdadf5534a2b5e4b47b8bdb49f925 commit 198bc68c21dcdadf5534a2b5e4b47b8bdb49f925 Author: Michael Meissner Date: Tue Jun 17 02:39:23 2025 -0400 Revert changes Diff: --- gcc/config/rs6000/rs6000.cc | 10 + gcc/testsuite/gcc.target/power

[gcc(refs/vendors/redhat/heads/gcc-14-branch)] Merge commit 'r14-11849-gcb7784fd04deec1f94c20536709847786f2a90e6' into redhat/gcc-14-branch

https://gcc.gnu.org/g:74a421064f3d0de5d604bc051d9c21c1b9763064 commit 74a421064f3d0de5d604bc051d9c21c1b9763064 Merge: 078cfa03d84e cb7784fd04de Author: Jakub Jelinek Date: Tue Jun 17 08:33:08 2025 +0200 Merge commit 'r14-11849-gcb7784fd04deec1f94c20536709847786f2a90e6' into redhat/gcc-14-

[gcc/redhat/heads/gcc-14-branch] (50 commits) Merge commit 'r14-11849-gcb7784fd04deec1f94c20536709847786f

The branch 'redhat/heads/gcc-14-branch' was updated to point to: 74a421064f3d... Merge commit 'r14-11849-gcb7784fd04deec1f94c20536709847786f It previously pointed to: 078cfa03d84e... Merge commit 'r14-11800-g306cdb4df729079d7bd924e00236931811 Diff: Summary of changes (added commits): ---

[gcc(refs/users/meissner/heads/work211-cmodel)] PR target/120681 - allow -mcmodel=large with prefixed addressing

https://gcc.gnu.org/g:aa83a50e72a3b4b0ce72f6c6b62f3df9da36130c commit aa83a50e72a3b4b0ce72f6c6b62f3df9da36130c Author: Michael Meissner Date: Tue Jun 17 02:20:32 2025 -0400 PR target/120681 - allow -mcmodel=large with prefixed addressing When I implemented the pc-relative support

[gcc(refs/users/meissner/heads/work211-cmodel)] Revert changes

https://gcc.gnu.org/g:552fa024fe9f7cf6bef52337de3270e6c46d commit 552fa024fe9f7cf6bef52337de3270e6c46d Author: Michael Meissner Date: Tue Jun 17 02:17:32 2025 -0400 Revert changes Diff: --- gcc/config/rs6000/rs6000.cc | 10 + gcc/testsuite/gcc.target/power

[gcc r16-1535] c++, coroutines: Handle unevaluated contexts.

https://gcc.gnu.org/g:e2bff264e8b92426b13aacec3087cb97971ec9b9 commit r16-1535-ge2bff264e8b92426b13aacec3087cb97971ec9b9 Author: Iain Sandoe Date: Sun Jun 8 14:28:01 2025 +0100 c++, coroutines: Handle unevaluated contexts. From [expr.await]/2 We should not accept co_await, co_

[gcc r16-1534] c++, coroutines: Avoid UNKNOWN_LOCATION synthesizing code [PR120273].

https://gcc.gnu.org/g:3b95be7bd1882add4b1e22f6b70bc130cd465eca commit r16-1534-g3b95be7bd1882add4b1e22f6b70bc130cd465eca Author: Iain Sandoe Date: Tue Jun 3 13:07:27 2025 +0100 c++, coroutines: Avoid UNKNOWN_LOCATION synthesizing code [PR120273]. Some of the lookup code is expecti

[gcc r16-1533] RISC-V: Add -fno-pie flags to testcases

https://gcc.gnu.org/g:6a17361496afbef5a095b9d5f26642cc8465fa31 commit r16-1533-g6a17361496afbef5a095b9d5f26642cc8465fa31 Author: Kito Cheng Date: Tue Jun 17 12:52:00 2025 +0800 RISC-V: Add -fno-pie flags to testcases PIE may cause some code gen difference in the testcases, that wi

[gcc(refs/users/meissner/heads/work211-cmodel)] Revert changes

https://gcc.gnu.org/g:3b9b27a01de8d63e2d8fbcb0a775b0474f697f79 commit 3b9b27a01de8d63e2d8fbcb0a775b0474f697f79 Author: Michael Meissner Date: Tue Jun 17 00:38:53 2025 -0400 Revert changes Diff: --- gcc/config/rs6000/rs6000.cc | 10 ++ gcc/testsuite/gcc.target/powe

[gcc(refs/users/meissner/heads/work211-cmodel)] Update ChangeLog.*

https://gcc.gnu.org/g:f74d1190ea127023395b58f9b316c630d7bc45a7 commit f74d1190ea127023395b58f9b316c630d7bc45a7 Author: Michael Meissner Date: Tue Jun 17 00:56:59 2025 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.cmodel | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff

[gcc(refs/users/meissner/heads/work211-cmodel)] PR target/120681 - allow -mcmodel=large with prefixed addressing

https://gcc.gnu.org/g:9cb7f4f09185c9e723de84d571a7c9eb309332fe commit 9cb7f4f09185c9e723de84d571a7c9eb309332fe Author: Michael Meissner Date: Tue Jun 17 00:53:53 2025 -0400 PR target/120681 - allow -mcmodel=large with prefixed addressing When I implemented the pc-relative support

[gcc(refs/users/meissner/heads/work211-cmodel)] PR target/120681 - allow -mcmodel=large with prefixed addressing

https://gcc.gnu.org/g:ea7962211ffa96fc13cf8eba60c396a3cf9dfd97 commit ea7962211ffa96fc13cf8eba60c396a3cf9dfd97 Author: Michael Meissner Date: Mon Jun 16 19:30:47 2025 -0400 PR target/120681 - allow -mcmodel=large with prefixed addressing When I implemented the pc-relative support

[gcc(refs/users/meissner/heads/work211-bugs)] Fix PR 118541, do not generate unordered fp cmoves for IEEE compares.

https://gcc.gnu.org/g:0699f24c700e5f6f203b258d074e903e6a6fe210 commit 0699f24c700e5f6f203b258d074e903e6a6fe210 Author: Michael Meissner Date: Mon Jun 16 16:38:26 2025 -0400 Fix PR 118541, do not generate unordered fp cmoves for IEEE compares. In bug PR target/118541 on power9, pow

[gcc(refs/users/meissner/heads/work211-cmodel)] Update ChangeLog.*

https://gcc.gnu.org/g:fba06f42f9c47fa74ef41686efc064f3631ee984 commit fba06f42f9c47fa74ef41686efc064f3631ee984 Author: Michael Meissner Date: Mon Jun 16 19:33:44 2025 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.cmodel | 32 1 file changed, 32 inserti

[gcc(refs/users/meissner/heads/work211-bugs)] Update ChangeLog.*

https://gcc.gnu.org/g:fb0d449b9081f5f4b32c0b16528d52dd6a646724 commit fb0d449b9081f5f4b32c0b16528d52dd6a646724 Author: Michael Meissner Date: Mon Jun 16 16:46:55 2025 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.bugs | 230 + 1 file

[gcc(refs/users/meissner/heads/work211-bugs)] PR target/108958 -- simplify mtvsrdd to zero extend GPR DImode to VSX TImode

https://gcc.gnu.org/g:3ca6fd8cbb8fc89b552ba220773bb3c972a5b77d commit 3ca6fd8cbb8fc89b552ba220773bb3c972a5b77d Author: Michael Meissner Date: Mon Jun 16 16:40:52 2025 -0400 PR target/108958 -- simplify mtvsrdd to zero extend GPR DImode to VSX TImode Before this patch GCC would zer

[gcc(refs/users/meissner/heads/work211-bugs)] PR target/120528 -- Simplify zero extend from memory to VSX register on power10

https://gcc.gnu.org/g:7e60829c19ac18dd39071d8877f5df4258531e8d commit 7e60829c19ac18dd39071d8877f5df4258531e8d Author: Michael Meissner Date: Mon Jun 16 16:44:46 2025 -0400 PR target/120528 -- Simplify zero extend from memory to VSX register on power10 Previously GCC would zero e

[gcc r16-1530] aarch64: Add support for unpacked SVE FP conversions

https://gcc.gnu.org/g:a26c5fc8fe2bdb4973d114732238d95c3896bc08 commit r16-1530-ga26c5fc8fe2bdb4973d114732238d95c3896bc08 Author: Spencer Abson Date: Mon Jun 16 19:31:30 2025 + aarch64: Add support for unpacked SVE FP conversions This patch introduces expanders for FP<-FP conve

[gcc r16-1529] aarch64: Extend iterator support for partial SVE FP modes

https://gcc.gnu.org/g:35b8acbd76caec349ec70972ee9e8cb8535343d0 commit r16-1529-g35b8acbd76caec349ec70972ee9e8cb8535343d0 Author: Spencer Abson Date: Mon Jun 16 16:43:07 2025 + aarch64: Extend iterator support for partial SVE FP modes Define new iterators for partial floating-p

[gcc r16-1528] Fortran: fix checking of MOLD= in ALLOCATE statements [PR51961]

https://gcc.gnu.org/g:3b276fe0d22f9052657dbbffbb8ad6f8585bd304 commit r16-1528-g3b276fe0d22f9052657dbbffbb8ad6f8585bd304 Author: Harald Anlauf Date: Sun Jun 15 21:09:28 2025 +0200 Fortran: fix checking of MOLD= in ALLOCATE statements [PR51961] In ALLOCATE statements where the MOLD

[gcc r16-1527] c++: add -Wsfinae-incomplete

https://gcc.gnu.org/g:117782e0c2a81a4b8170f87f0fe7190ee22548e2 commit r16-1527-g117782e0c2a81a4b8170f87f0fe7190ee22548e2 Author: Jason Merrill Date: Thu Jun 12 11:19:19 2025 -0400 c++: add -Wsfinae-incomplete We already error about a type or function definition causing a concept c

[gcc r16-1526] RISC-V: Refine VX combine test case 0 to avoid code duplication

https://gcc.gnu.org/g:ad909d5c0ce7fcd0bcbacd0ee20c15bf479fd990 commit r16-1526-gad909d5c0ce7fcd0bcbacd0ee20c15bf479fd990 Author: Pan Li Date: Sun Jun 15 16:28:38 2025 +0800 RISC-V: Refine VX combine test case 0 to avoid code duplication The case 0 for vx combine def functions are

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vmaxu.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:529fb26142fbc712f700d72e23f63df4add7ff08 commit 529fb26142fbc712f700d72e23f63df4add7ff08 Author: Pan Li Date: Sat Jun 14 22:32:23 2025 +0800 RISC-V: Add test for vec_duplicate + vmaxu.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check test for

[gcc r16-1525] aarch64: add support for AEABI Build Attributes

https://gcc.gnu.org/g:98f5547dce2503d9d0f0cd454184d6870a315538 commit r16-1525-g98f5547dce2503d9d0f0cd454184d6870a315538 Author: Matthieu Longo Date: Wed Sep 11 16:11:55 2024 +0100 aarch64: add support for AEABI Build Attributes GCS (Guarded Control Stack, an Armv9.4-a extension)

[gcc r16-1524] aarch64: encapsulate note.gnu.property emission into a class

https://gcc.gnu.org/g:0b4a3c146312fa9edde12abba31b1f285b5a378d commit r16-1524-g0b4a3c146312fa9edde12abba31b1f285b5a378d Author: Matthieu Longo Date: Wed Jun 4 12:10:05 2025 +0100 aarch64: encapsulate note.gnu.property emission into a class The code emitting the GNU properties was

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Update Profiles string in RV23.

https://gcc.gnu.org/g:b5c60ee96b72e26334979441f2877b316a3cb7ed commit b5c60ee96b72e26334979441f2877b316a3cb7ed Author: Jiawei Date: Mon Jun 16 11:21:29 2025 +0800 RISC-V: Update Profiles string in RV23. Add b-ext in RVA/B23 as independent extension flags and add supm in RVA23.

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vmaxu.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:5298cd82fc46751a476226988f17fc073577a080 commit 5298cd82fc46751a476226988f17fc073577a080 Author: Pan Li Date: Sat Jun 14 22:34:36 2025 +0800 RISC-V: Add test for vec_duplicate + vmaxu.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check test for v

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vmaxu.vv to vmaxu.vx on GR2VR cost

https://gcc.gnu.org/g:bab882c77c3013e42141ac032c4a3158e9287f6b commit bab882c77c3013e42141ac032c4a3158e9287f6b Author: Pan Li Date: Sat Jun 14 22:29:40 2025 +0800 RISC-V: Combine vec_duplicate + vmaxu.vv to vmaxu.vx on GR2VR cost This patch would like to combine the vec_duplicate

[gcc r16-1523] c++: ICE with unexpanded pack in asm

https://gcc.gnu.org/g:138d0a20f8d81670bb616d440fc8990833e70aab commit r16-1523-g138d0a20f8d81670bb616d440fc8990833e70aab Author: yxj-github-437 <2457369...@qq.com> Date: Wed Jun 4 21:18:45 2025 +0800 c++: ICE with unexpanded pack in asm Here an unexpanded parameter pack pass into a

[gcc r16-1522] aarch64: add debug comments to feature properties in .note.gnu.property

https://gcc.gnu.org/g:6eb0dc067dad1fe745e83d4e113c1b2ea0ffed8c commit r16-1522-g6eb0dc067dad1fe745e83d4e113c1b2ea0ffed8c Author: Matthieu Longo Date: Mon Sep 23 14:38:57 2024 +0100 aarch64: add debug comments to feature properties in .note.gnu.property GNU properties are emitted t

[gcc r16-1521] Combine static and afdo branch predictions

https://gcc.gnu.org/g:2ef043c5a05d9914e3c3dbff6f2c521eb665d971 commit r16-1521-g2ef043c5a05d9914e3c3dbff6f2c521eb665d971 Author: Jan Hubicka Date: Mon Jun 16 10:19:05 2025 +0200 Combine static and afdo branch predictions Currently afdo reads the profile and anotates basic blocks c