[gcc r16-728] RISC-V: Support Zilsd code gen

https://gcc.gnu.org/g:a3e78dda4d51bc37adcfa088237e2b8567e76da2 commit r16-728-ga3e78dda4d51bc37adcfa088237e2b8567e76da2 Author: Kito Cheng Date: Mon May 12 02:38:39 2025 -0700 RISC-V: Support Zilsd code gen This commit adds the code gen support for Zilsd, which is a newly adde

[gcc r16-727] regcprop: Return from copy_value for unordered modes

https://gcc.gnu.org/g:2ec5082dd24cef5149ba645ee88a9acd8b4c290a commit r16-727-g2ec5082dd24cef5149ba645ee88a9acd8b4c290a Author: Jennifer Schmitz Date: Thu May 15 07:16:15 2025 -0700 regcprop: Return from copy_value for unordered modes The ICE in PR120276 resulted from a comparison

[gcc r16-726] RISC-V: Add new operand constraint: cR

https://gcc.gnu.org/g:c9eb473fb9946f642506d24f4131d7c83855fd78 commit r16-726-gc9eb473fb9946f642506d24f4131d7c83855fd78 Author: Kito Cheng Date: Mon May 12 14:36:07 2025 +0800 RISC-V: Add new operand constraint: cR This commit introduces a new operand constraint `cR` for the RISC-

[gcc r16-724] i386: Refactor AVX10.2 runtime test

https://gcc.gnu.org/g:34caeae39f67d8a2423e8b2086c433b44d504afb commit r16-724-g34caeae39f67d8a2423e8b2086c433b44d504afb Author: Haochen Jiang Date: Mon Mar 24 17:02:44 2025 +0800 i386: Refactor AVX10.2 runtime test Since everything is under avx10.2, we could use a header file

[gcc r16-722] i386: Remove duplicate iterators in md

https://gcc.gnu.org/g:5bdb72212919e1335838d32cee81a7981b5a1da1 commit r16-722-g5bdb72212919e1335838d32cee81a7981b5a1da1 Author: Haochen Jiang Date: Fri Mar 14 14:27:36 2025 +0800 i386: Remove duplicate iterators in md There are several iterators no longer needed in md files since

[gcc r16-718] emit-rtl: Allow extra checks for paradoxical subregs [PR119966]

https://gcc.gnu.org/g:eb2ea476db2182939f585df7d806225649ee4f62 commit r16-718-geb2ea476db2182939f585df7d806225649ee4f62 Author: Dimitar Dimitrov Date: Sat May 3 22:38:30 2025 +0300 emit-rtl: Allow extra checks for paradoxical subregs [PR119966] When a paradoxical subreg is detecte

[gcc r16-717] Partially lift restriction from loc_list_from_tree_1

https://gcc.gnu.org/g:809b46d2ccc9a4a0ab3a5b6015cbe9738b74b0a5 commit r16-717-g809b46d2ccc9a4a0ab3a5b6015cbe9738b74b0a5 Author: Eric Botcazou Date: Sun May 18 19:10:26 2025 +0200 Partially lift restriction from loc_list_from_tree_1 The function accepts all handled_component_p expr

[gcc r16-716] phiopt: Use mark_lhs_in_seq_for_dce instead of doing it inline

https://gcc.gnu.org/g:98129ff8c08056f6a7d395fbe46d577b856871e7 commit r16-716-g98129ff8c08056f6a7d395fbe46d577b856871e7 Author: Andrew Pinski Date: Sat May 17 17:21:39 2025 -0700 phiopt: Use mark_lhs_in_seq_for_dce instead of doing it inline Right now phiopt has the same code as m

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Regen riscv-ext.opt.urls

https://gcc.gnu.org/g:a4d3735c33c133d9eb7d029cf2525f575b7e3f85 commit a4d3735c33c133d9eb7d029cf2525f575b7e3f85 Author: Kito Cheng Date: Wed May 14 23:19:17 2025 +0800 RISC-V: Regen riscv-ext.opt.urls gcc/ChangeLog: * config/riscv/riscv-ext.opt.urls: Regenerate.

[gcc(refs/users/mikael/heads/refactor_descriptor_v05)] Correction régression {minloc,maxloc}_nan_1

https://gcc.gnu.org/g:f288b88ddbeef9452170083380c27f78dd963de4 commit f288b88ddbeef9452170083380c27f78dd963de4 Author: Mikael Morin Date: Sun May 18 16:47:43 2025 +0200 Correction régression {minloc,maxloc}_nan_1 Diff: --- libgfortran/generated/maxloc0_16_i1.c | 6 ++ libgfortran/g

[gcc(refs/users/mikael/heads/refactor_descriptor_v05)] Correction partielle allocate_with_source_11

https://gcc.gnu.org/g:051482b5e45076f1de061546b5ddd1ce251fc939 commit 051482b5e45076f1de061546b5ddd1ce251fc939 Author: Mikael Morin Date: Sun May 18 15:02:49 2025 +0200 Correction partielle allocate_with_source_11 Diff: --- gcc/fortran/trans-expr.cc | 8 1 file changed, 4 insert

[gcc(refs/users/mikael/heads/refactor_descriptor_v05)] Correction régression allocate_with_source_11

https://gcc.gnu.org/g:551a0e231b710ddf692cf8d7ce3f0c0845d2c510 commit 551a0e231b710ddf692cf8d7ce3f0c0845d2c510 Author: Mikael Morin Date: Sun May 18 15:37:02 2025 +0200 Correction régression allocate_with_source_11 Diff: --- gcc/fortran/trans-expr.cc | 21 + 1 file ch

[gcc r16-715] Regenerate cobol/lang.opt.urls

https://gcc.gnu.org/g:f32946cc54a7de59498b42e3450ff124dffeb2d7 commit r16-715-gf32946cc54a7de59498b42e3450ff124dffeb2d7 Author: Mark Wielaard Date: Sun May 18 16:20:10 2025 +0200 Regenerate cobol/lang.opt.urls The Cobol frontend lang.opt got -M added, but lang.opt.urls wasn't

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Extract vector duplicate for expand_const_vector [NFC]

https://gcc.gnu.org/g:11dcc4942eb0edf04ebe897427a938640e56bea2 commit 11dcc4942eb0edf04ebe897427a938640e56bea2 Author: Pan Li Date: Wed Apr 16 15:47:21 2025 +0800 RISC-V: Extract vector duplicate for expand_const_vector [NFC] Consider the expand_const_vector is quit long (about 50

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Adjust vx combine test case to avoid name conflict

https://gcc.gnu.org/g:8776c190ce92c478b83f5ad092bdc46b0e6a1f6a commit 8776c190ce92c478b83f5ad092bdc46b0e6a1f6a Author: Pan Li Date: Tue May 13 11:12:53 2025 +0800 RISC-V: Adjust vx combine test case to avoid name conflict Given we will put all vx combine for int8 in a single file,

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] Make end_sequence return the insn sequence

https://gcc.gnu.org/g:49278dd284fab03788b4e69ba385261ecf6bb05b commit 49278dd284fab03788b4e69ba385261ecf6bb05b Author: Richard Sandiford Date: Fri May 16 13:24:01 2025 +0100 Make end_sequence return the insn sequence The start_sequence/end_sequence interface was a big improvement

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Minimal support for sdtrig and ssstrict extensions.

https://gcc.gnu.org/g:71b176096c00f0f77b1734294ec30f209209cc46 commit 71b176096c00f0f77b1734294ec30f209209cc46 Author: Dongyan Chen Date: Tue May 6 17:09:54 2025 -0600 [PATCH] RISC-V: Minimal support for sdtrig and ssstrict extensions. This patch support sdtrig and ssstrict extens

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/118410] Improve code generation for some logical ops

https://gcc.gnu.org/g:512a79ec2725187235d9564db48ba47f0c7bb27d commit 512a79ec2725187235d9564db48ba47f0c7bb27d Author: Jeff Law Date: Sat Apr 19 12:30:42 2025 -0600 [RISC-V][PR target/118410] Improve code generation for some logical ops I'm posting this on behalf of Shreya Munnang

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix register move cost for SIBCALL_REGS/JALR_REGS

https://gcc.gnu.org/g:2bf7f4274e6d02515570496676a22f36ba3c7d15 commit 2bf7f4274e6d02515570496676a22f36ba3c7d15 Author: Zhijin Zeng Date: Mon Apr 28 09:24:16 2025 +0800 RISC-V: Fix register move cost for SIBCALL_REGS/JALR_REGS SIBCALL_REGS/JALR_REGS are also subset of GR_REGS and n

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Separate the test running of rvv vx_vf

https://gcc.gnu.org/g:e6cdd9834132cf9a46557c659df1578231e2bdaf commit e6cdd9834132cf9a46557c659df1578231e2bdaf Author: Pan Li Date: Thu May 8 10:00:50 2025 +0800 RISC-V: Separate the test running of rvv vx_vf The default test running in rvv.exp takes the -fno-vect-cost-model f

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Adjust rvv tests after recent jump threading change

https://gcc.gnu.org/g:1cc79df281ac98d1efcd431ec0da7ae91a1012b7 commit 1cc79df281ac98d1efcd431ec0da7ae91a1012b7 Author: Jeff Law Date: Sun May 4 11:05:44 2025 -0600 [RISC-V] Adjust rvv tests after recent jump threading change Richi's jump threading patch is resulting in new jump th

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vsub.vv combine case 1 with GR2VR cost 0

https://gcc.gnu.org/g:1a93ea8c5c40ea8d1772c2251e134b4efe8e082f commit 1a93ea8c5c40ea8d1772c2251e134b4efe8e082f Author: Pan Li Date: Tue May 13 22:32:03 2025 +0800 RISC-V: Add test for vec_duplicate + vsub.vv combine case 1 with GR2VR cost 0 Add asm dump check test for vec_duplicat

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [V2][RISC-V] Synthesize more efficient IOR/XOR sequences

https://gcc.gnu.org/g:7866e62f125b108b76c994715fc6078618296d4c commit 7866e62f125b108b76c994715fc6078618296d4c Author: Shreya Munnangi Date: Sat May 10 07:18:33 2025 -0600 [V2][RISC-V] Synthesize more efficient IOR/XOR sequences So mvconst_internal's primary benefit is in constant

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Avoid scalar unsigned SAT_ADD test data duplication

https://gcc.gnu.org/g:6e73320a5f1b2af6c099644e8f7cbdc6f11fec58 commit 6e73320a5f1b2af6c099644e8f7cbdc6f11fec58 Author: Pan Li Date: Fri May 16 15:34:51 2025 +0800 RISC-V: Avoid scalar unsigned SAT_ADD test data duplication Some of the previous scalar unsigned SAT_ADD test data are

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Fix ICE due to bogus use of gen_rtvec

https://gcc.gnu.org/g:5159c19cb2a8375fe73e7ab90b118fa55a5e0bbd commit 5159c19cb2a8375fe73e7ab90b118fa55a5e0bbd Author: Jeff Law Date: Sat May 17 09:37:01 2025 -0600 [RISC-V] Fix ICE due to bogus use of gen_rtvec Found this while setting up the risc-v coordination branch off of gcc

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Avoid setting output object more than once in IOR/XOR synthesis

https://gcc.gnu.org/g:8010f9802a62912ee149ff44b07bd4cf80ec44fc commit 8010f9802a62912ee149ff44b07bd4cf80ec44fc Author: Jeff Law Date: Sat May 17 07:16:50 2025 -0600 [RISC-V] Avoid setting output object more than once in IOR/XOR synthesis While evaluating Shreya's logical AND synth

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Since the loop increment i++ is unreachable, the loop body will never execute more than once

https://gcc.gnu.org/g:99d801c0191641da7b313517454cf8f6b9d39415 commit 99d801c0191641da7b313517454cf8f6b9d39415 Author: Jin Ma Date: Fri May 16 15:27:13 2025 +0800 RISC-V: Since the loop increment i++ is unreachable, the loop body will never execute more than once Reported-by: hua

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] Partial cherry-pick of 4dd13988c93c24ba3605f4b9cafc97515c34f2ac, just the RISC-V backend bits.

https://gcc.gnu.org/g:84adfa2f4d281c7ae14c52d8b3ee92e7544afdbe commit 84adfa2f4d281c7ae14c52d8b3ee92e7544afdbe Author: Jeff Law Date: Fri May 16 11:27:25 2025 -0600 Partial cherry-pick of 4dd13988c93c24ba3605f4b9cafc97515c34f2ac, just the RISC-V backend bits. commit 4dd13988c93c2

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Reuse test name for vx combine test data [NFC]

https://gcc.gnu.org/g:9a8ca2f4b34ed39f5d17ab7798864d46c7788f45 commit 9a8ca2f4b34ed39f5d17ab7798864d46c7788f45 Author: Pan Li Date: Tue May 13 22:54:17 2025 +0800 RISC-V: Reuse test name for vx combine test data [NFC] For run test, we have a name like add/sub to indicate the t

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vsub.vv combine case 1 with GR2VR cost 2

https://gcc.gnu.org/g:76ecd7693326497809e517d0f19f06f59cd2aec2 commit 76ecd7693326497809e517d0f19f06f59cd2aec2 Author: Pan Li Date: Tue May 13 22:47:13 2025 +0800 RISC-V: Add test for vec_duplicate + vsub.vv combine case 1 with GR2VR cost 2 Add asm dump check test for vec_duplica

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vsub.vv combine case 1 with GR2VR cost 1

https://gcc.gnu.org/g:13a6e9fcd051f3c3435b40c328ce7d6ddadcff0d commit 13a6e9fcd051f3c3435b40c328ce7d6ddadcff0d Author: Pan Li Date: Tue May 13 22:38:57 2025 +0800 RISC-V: Add test for vec_duplicate + vsub.vv combine case 1 with GR2VR cost 1 Add asm dump check test for vec_duplica

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vsub.vv combine case 0 with GR2VR cost 15

https://gcc.gnu.org/g:04f07eebc1b0717952fe683e84243710a8f87242 commit 04f07eebc1b0717952fe683e84243710a8f87242 Author: Pan Li Date: Sun May 11 16:32:51 2025 +0800 RISC-V: Add test for vec_duplicate + vsub.vv combine case 0 with GR2VR cost 15 Add asm dump check test for vec_duplic

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vsub.vv combine case 0 with GR2VR cost 1

https://gcc.gnu.org/g:c0cb19a9b46d4fbdb14006a6f9759c0f81672700 commit c0cb19a9b46d4fbdb14006a6f9759c0f81672700 Author: Pan Li Date: Sun May 11 16:31:16 2025 +0800 RISC-V: Add test for vec_duplicate + vsub.vv combine case 0 with GR2VR cost 1 Add asm dump check test for vec_duplica

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vsub.vv combine case 0 with GR2VR cost 0

https://gcc.gnu.org/g:7195b881e26fd641735c9da502650bf3b1fd16c2 commit 7195b881e26fd641735c9da502650bf3b1fd16c2 Author: Pan Li Date: Sun May 11 16:27:48 2025 +0800 RISC-V: Add test for vec_duplicate + vsub.vv combine case 0 with GR2VR cost 0 Add asm dump check and run test for vec_

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Rename vx_vadd-* testcase to vx-* for all vx combine [NFC]

https://gcc.gnu.org/g:f6ae7c882d926e0b0b0478093c9660bfaaa7ef8e commit f6ae7c882d926e0b0b0478093c9660bfaaa7ef8e Author: Pan Li Date: Tue May 13 10:00:35 2025 +0800 RISC-V: Rename vx_vadd-* testcase to vx-* for all vx combine [NFC] We would like to arrange all vx combine asm check t

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR cost

https://gcc.gnu.org/g:6785ad35b45c2800262b63b1db05ceaa10dc0e0d commit 6785ad35b45c2800262b63b1db05ceaa10dc0e0d Author: Pan Li Date: Sun May 11 16:20:28 2025 +0800 RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR cost This patch would like to combine the vec_duplicate +

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/120223] Don't use bset/binv for XTHEADBS

https://gcc.gnu.org/g:103da6a7a8262f4fd2b81568bb15686dc5669760 commit 103da6a7a8262f4fd2b81568bb15686dc5669760 Author: Jeff Law Date: Thu May 15 09:03:13 2025 -0600 [RISC-V][PR target/120223] Don't use bset/binv for XTHEADBS Thead has the XTHEADBB extension which has a lot of over

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Drop riscv_ext_flag_table in favor of riscv_ext_info_t data

https://gcc.gnu.org/g:8b77ff652532617fd584e2eb8886d1ffcf8690f0 commit 8b77ff652532617fd584e2eb8886d1ffcf8690f0 Author: Kito Cheng Date: Wed May 7 21:27:20 2025 +0800 RISC-V: Drop riscv_ext_flag_table in favor of riscv_ext_info_t data Refactor extension flag handling by removing th

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix uninit riscv_subset_list::m_allow_adding_dup issue

https://gcc.gnu.org/g:5e6cb89649ad4a4305d69e8f1cd030adad3a6b47 commit 5e6cb89649ad4a4305d69e8f1cd030adad3a6b47 Author: Kito Cheng Date: Tue May 13 10:34:34 2025 +0800 RISC-V: Fix uninit riscv_subset_list::m_allow_adding_dup issue We forgot to initialize m_allow_adding_dup in the c

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add augmented hypervisor series extensions.

https://gcc.gnu.org/g:fa7576e1c7e99079abf40c3a3cd73c502bbed93c commit fa7576e1c7e99079abf40c3a3cd73c502bbed93c Author: Jiawei Date: Tue May 13 15:23:39 2025 +0800 RISC-V: Add augmented hypervisor series extensions. The augmented hypervisor series extensions 'sha'[1] is a new profi

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Drop duplicate build rule for riscv-ext.opt [NFC]

https://gcc.gnu.org/g:b0fb9ba6b2024256d26746875c58a441f47da19d commit b0fb9ba6b2024256d26746875c58a441f47da19d Author: Kito Cheng Date: Wed May 14 23:19:38 2025 +0800 RISC-V: Drop duplicate build rule for riscv-ext.opt [NFC] gcc/ChangeLog: * config/riscv/t-riscv:

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Drop riscv_ext_version_table in favor of riscv_ext_info_t data

https://gcc.gnu.org/g:1931c493c4ba1336f83d14c35ad1bedec6d3943f commit 1931c493c4ba1336f83d14c35ad1bedec6d3943f Author: Kito Cheng Date: Thu May 8 16:23:29 2025 +0800 RISC-V: Drop riscv_ext_version_table in favor of riscv_ext_info_t data This commit drops the riscv_ext_version_tabl

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned integer SAT_ADD form 7

https://gcc.gnu.org/g:24f53c2781a919deaf098a7514428e679d4866c0 commit 24f53c2781a919deaf098a7514428e679d4866c0 Author: Pan Li Date: Mon Apr 28 20:35:09 2025 +0800 RISC-V: Add testcases for scalar unsigned integer SAT_ADD form 7 This patch will add testcase for unsigned integer SAT

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Introduce riscv-ext*.def to define extensions

https://gcc.gnu.org/g:f63e8d39f3335c04eddd55f5e2e6bccd071f17c4 commit f63e8d39f3335c04eddd55f5e2e6bccd071f17c4 Author: Kito Cheng Date: Wed May 7 18:02:10 2025 +0800 RISC-V: Introduce riscv-ext*.def to define extensions Adding a new ISA extension to RISC-V GCC requires modifying s

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Drop riscv_implied_info and riscv_combine_info in favor of riscv_ext_info_t data

https://gcc.gnu.org/g:d5d13d9b68966c608b8eb25d519143f39d4378c5 commit d5d13d9b68966c608b8eb25d519143f39d4378c5 Author: Kito Cheng Date: Wed May 7 21:21:01 2025 +0800 RISC-V: Drop riscv_implied_info and riscv_combine_info in favor of riscv_ext_info_t data Consolidate implied-exten

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Introduce riscv_ext_info_t to hold extension metadata

https://gcc.gnu.org/g:1c2a37393d26b08c0d89d7b89bc31253197417d4 commit 1c2a37393d26b08c0d89d7b89bc31253197417d4 Author: Kito Cheng Date: Wed May 7 20:59:15 2025 +0800 RISC-V: Introduce riscv_ext_info_t to hold extension metadata Define a new riscv_ext_info_t struct to aggregate all

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Generate extension table in documentation from riscv-ext.def

https://gcc.gnu.org/g:ac1cfc515717bb6f3dfb5d1c9da88e3b132be6c2 commit ac1cfc515717bb6f3dfb5d1c9da88e3b132be6c2 Author: Kito Cheng Date: Wed May 7 21:10:53 2025 +0800 RISC-V: Generate extension table in documentation from riscv-ext.def Automatically build the ISA extension referenc

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Adjust riscv_can_inline_p

https://gcc.gnu.org/g:4d7dafbf4efe456e23f20e0cb325b6c04b8a6487 commit 4d7dafbf4efe456e23f20e0cb325b6c04b8a6487 Author: Kito Cheng Date: Wed May 7 18:30:34 2025 +0800 RISC-V: Adjust riscv_can_inline_p We don't hold any extenison flags in `target_flags`, so no need to gather the

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Use riscv-ext.def to generate target options and variables

https://gcc.gnu.org/g:dff806ebade211593493b6824d59bf406af84d42 commit dff806ebade211593493b6824d59bf406af84d42 Author: Kito Cheng Date: Wed May 7 18:28:18 2025 +0800 RISC-V: Use riscv-ext.def to generate target options and variables Leverage the centralized riscv-ext.def definitio

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcases for vector unsigned integer SAT_ADD form 7

https://gcc.gnu.org/g:194d03f429fa776eba7ed9beed9bf121f5740672 commit 194d03f429fa776eba7ed9beed9bf121f5740672 Author: Pan Li Date: Mon Apr 28 20:35:10 2025 +0800 RISC-V: Add testcases for vector unsigned integer SAT_ADD form 7 This patch will add testcase for unsigned integer SAT

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Minimal support for ssnpm, smnpm and smmpm extensions.

https://gcc.gnu.org/g:9df770e9932140bee41efb8849ab1ba057712199 commit 9df770e9932140bee41efb8849ab1ba057712199 Author: Dongyan Chen Date: Mon May 12 17:19:24 2025 +0800 RISC-V: Minimal support for ssnpm, smnpm and smmpm extensions. This patch support ssnpm, smnpm, smmpm, sspm and

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support for zilsd and zclsd extensions.

https://gcc.gnu.org/g:543db94d75024a6ca09498983112e8cc48df7a2a commit 543db94d75024a6ca09498983112e8cc48df7a2a Author: Dongyan Chen Date: Mon Mar 17 22:23:18 2025 +0800 RISC-V: Support for zilsd and zclsd extensions. This patch support zilsd and zclsd[1] extensions. To enable

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] testsuite: Fix RISC-V arch-52.c format issue.

https://gcc.gnu.org/g:e63c2075e730fa4e1374b828bdd86f18838406e4 commit e63c2075e730fa4e1374b828bdd86f18838406e4 Author: Jiawei Date: Mon May 12 13:23:50 2025 +0800 testsuite: Fix RISC-V arch-52.c format issue. Fix incorrect regular expression. gcc/testsuite/ChangeLog:

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH v2] RISC-V: Use vclmul for CRC expansion if available

https://gcc.gnu.org/g:ea263e8517348924e46c86b2377da13f40343668 commit ea263e8517348924e46c86b2377da13f40343668 Author: Anton Blanchard Date: Sat May 10 07:07:39 2025 -0600 [PATCH v2] RISC-V: Use vclmul for CRC expansion if available If the vector version of clmul (vclmul) is avail

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support RISC-V Profiles 23.

https://gcc.gnu.org/g:e887f88194ffa0fd62111d6f357063e6f83c65a1 commit e887f88194ffa0fd62111d6f357063e6f83c65a1 Author: Jiawei Date: Sat May 10 19:26:35 2025 +0800 RISC-V: Support RISC-V Profiles 23. This patch introduces support for RISC-V Profiles RV23A and RV23B [1], enablin

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support RISC-V Profiles 20/22.

https://gcc.gnu.org/g:7f87d18ebf76b77d9808275a2f16e89ed8df4897 commit 7f87d18ebf76b77d9808275a2f16e89ed8df4897 Author: Jiawei Date: Sat May 10 20:25:52 2025 +0800 RISC-V: Support RISC-V Profiles 20/22. This patch introduces support for RISC-V Profiles RV20 and RV22 [1], enabli

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/120137][PR target/120154] Don't create out-of-range permutation constants

https://gcc.gnu.org/g:8ad57623b394796b3dd2a8f22d7535df430cb53d commit 8ad57623b394796b3dd2a8f22d7535df430cb53d Author: Jeff Law Date: Wed May 7 15:06:58 2025 -0600 [RISC-V][PR target/120137][PR target/120154] Don't create out-of-range permutation constants To make hashing sensibl

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcases for vec_duplicate + vadd.vv combine case 1 with GR2VR cost 0

https://gcc.gnu.org/g:1072dae78cb698415023be373ce18c24e434f972 commit 1072dae78cb698415023be373ce18c24e434f972 Author: Pan Li Date: Thu May 8 11:19:11 2025 +0800 RISC-V: Add testcases for vec_duplicate + vadd.vv combine case 1 with GR2VR cost 0 Add asm dump check and for vec_dupl

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcases for vec_duplicate + vadd.vv combine case 1 with GR2VR cost 2

https://gcc.gnu.org/g:c118441b67c334fbb810bb6ffece8940706b75e0 commit c118441b67c334fbb810bb6ffece8940706b75e0 Author: Pan Li Date: Thu May 8 11:25:04 2025 +0800 RISC-V: Add testcases for vec_duplicate + vadd.vv combine case 1 with GR2VR cost 2 Add asm dump check and for vec_dupl

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcases for vec_duplicate + vadd.vv combine case 1 with GR2VR cost 1

https://gcc.gnu.org/g:621d37036de337277e1e942423cb7d98ddcae76f commit 621d37036de337277e1e942423cb7d98ddcae76f Author: Pan Li Date: Thu May 8 11:21:35 2025 +0800 RISC-V: Add testcases for vec_duplicate + vadd.vv combine case 1 with GR2VR cost 1 Add asm dump check and for vec_dupl

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Minimal support for zama16b extension.

https://gcc.gnu.org/g:1953b5ece3e2fc105d6760806b08a8ef0e368585 commit 1953b5ece3e2fc105d6760806b08a8ef0e368585 Author: Dongyan Chen Date: Wed May 7 11:33:06 2025 -0600 [PATCH] RISC-V: Minimal support for zama16b extension. This patch support zama16b extension[1]. To enable GCC

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Rename VX_BINARY test helper to VX_BINARY_CASE_0

https://gcc.gnu.org/g:3045c158c7fc484d012aa38d00a01d0caf00ab00 commit 3045c158c7fc484d012aa38d00a01d0caf00ab00 Author: Pan Li Date: Wed May 7 20:48:40 2025 +0800 RISC-V: Rename VX_BINARY test helper to VX_BINARY_CASE_0 This patch would like to rename the VX_BINARY within CASE_0 su

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Avoid unnecessary andi with -1 argument

https://gcc.gnu.org/g:832d5bcef5e49b31358e61525f0d001e776cec34 commit 832d5bcef5e49b31358e61525f0d001e776cec34 Author: Jeff Law Date: Tue May 6 19:20:14 2025 -0600 [RISC-V] Avoid unnecessary andi with -1 argument I was preparing to do some testing of Shreya's next patch on spec an

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Recognized svadu and svade extension

https://gcc.gnu.org/g:a67f729717304f4bb533f305ee0f4aae7b1879b9 commit a67f729717304f4bb533f305ee0f4aae7b1879b9 Author: Mingzhu Yan Date: Tue May 6 16:59:09 2025 -0600 [PATCH] RISC-V: Recognized svadu and svade extension This patch support svadu and svade extension. To enable G

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcases for vec_duplicate + vadd.vv combine when GR2VR cost 0

https://gcc.gnu.org/g:39e81979866a62ef67a2d0bbd7ce4c33a2e4011f commit 39e81979866a62ef67a2d0bbd7ce4c33a2e4011f Author: Pan Li Date: Sat May 3 10:40:20 2025 +0800 RISC-V: Add testcases for vec_duplicate + vadd.vv combine when GR2VR cost 0 Add asm dump check and run test for vec_dup

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR middle-end/114512] Recognize more bext idioms for RISC-V

https://gcc.gnu.org/g:65d4610c7e794a3310ddfca0b16636e26e624685 commit 65d4610c7e794a3310ddfca0b16636e26e624685 Author: Shreya Munnangi Date: Tue May 6 06:38:00 2025 -0600 [RISC-V][PR middle-end/114512] Recognize more bext idioms for RISC-V This is Shreya's next chunk of work. Whe

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcases for vec_duplicate + vadd.vv combine when GR2VR cost 15

https://gcc.gnu.org/g:9d9135afb3f72c1dfd308aa2ea8ea633a987d1df commit 9d9135afb3f72c1dfd308aa2ea8ea633a987d1df Author: Pan Li Date: Sat May 3 11:37:09 2025 +0800 RISC-V: Add testcases for vec_duplicate + vadd.vv combine when GR2VR cost 15 Add asm dump check and for vec_duplicate +

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcases for vec_duplicate + vadd.vv combine when GR2VR cost 1

https://gcc.gnu.org/g:11b0993fb65e83a2298851de58ba264a3cac320b commit 11b0993fb65e83a2298851de58ba264a3cac320b Author: Pan Li Date: Sat May 3 11:27:50 2025 +0800 RISC-V: Add testcases for vec_duplicate + vadd.vv combine when GR2VR cost 1 Add asm dump check and for vec_duplicate +

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR cost

https://gcc.gnu.org/g:c5d906ddb149012d82dadade77265d8046329f73 commit c5d906ddb149012d82dadade77265d8046329f73 Author: Pan Li Date: Thu May 1 21:23:54 2025 +0800 RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR cost This patch would like to combine the vec_duplicate + v

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add gr2vr cost helper function

https://gcc.gnu.org/g:2ee71e58696e6b52f5f91d6daacc2a441c1b565e commit 2ee71e58696e6b52f5f91d6daacc2a441c1b565e Author: Pan Li Date: Tue May 6 16:42:16 2025 +0800 RISC-V: Add gr2vr cost helper function After we introduced the --param=gpr2vr-cost option to set the cost value of

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add new option --param=gpr2vr-cost= for rvv insn

https://gcc.gnu.org/g:9b6166da407a99002840f41515260dfc1b1f541f commit 9b6166da407a99002840f41515260dfc1b1f541f Author: Pan Li Date: Tue May 6 16:26:06 2025 +0800 RISC-V: Add new option --param=gpr2vr-cost= for rvv insn During investigate the combine from vec_dup and vop.vv into

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/119971] Avoid losing shift count masking

https://gcc.gnu.org/g:f792a2e3714dceb4c1b3a8db2fa8b6066928d386 commit f792a2e3714dceb4c1b3a8db2fa8b6066928d386 Author: Jeff Law Date: Mon May 5 17:14:29 2025 -0600 [RISC-V][PR target/119971] Avoid losing shift count masking As is outlined in the PR, we have a few define_insn_and_s

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix gcc.target/riscv/predef-19.c [PR120054]

https://gcc.gnu.org/g:b4ff83abf7386acdec9b8c3c32e99a8b339be977 commit b4ff83abf7386acdec9b8c3c32e99a8b339be977 Author: Kito Cheng Date: Mon May 5 10:08:22 2025 +0800 RISC-V: Fix gcc.target/riscv/predef-19.c [PR120054] gcc/testsuite/ChangeLog: PR target/120054

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Apply clang-format to genrvv-type-indexer.cc [NFC]

https://gcc.gnu.org/g:6b9a26181b57b70d2fc478cd2cd7da5fd14f178f commit 6b9a26181b57b70d2fc478cd2cd7da5fd14f178f Author: Kito Cheng Date: Mon May 5 10:16:14 2025 +0800 RISC-V: Apply clang-format to genrvv-type-indexer.cc [NFC] Tweak the formatting of the genrvv-type-indexer.cc file

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [V2][RISC-V] Trivial permutation constant derivation

https://gcc.gnu.org/g:10057e3958cad6bde4963382422cd759e04feb7f commit 10057e3958cad6bde4963382422cd759e04feb7f Author: Jeff Law Date: Sun May 4 16:59:51 2025 -0600 [V2][RISC-V] Trivial permutation constant derivation This is a patch from late 2024 (just before stage1 freeze), but

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Allow different dynamic floating point mode to be merged [PR119832]

https://gcc.gnu.org/g:5179fed0c70da4bf756af61a3ec8bdb93524673c commit 5179fed0c70da4bf756af61a3ec8bdb93524673c Author: Kito Cheng Date: Tue Apr 29 11:35:00 2025 +0800 RISC-V: Allow different dynamic floating point mode to be merged [PR119832] Although we already try to set the mod

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Implment H modifier for printing the next register name

https://gcc.gnu.org/g:f597a596cf8cb7f89b7d1e944ddd4baaccff9019 commit f597a596cf8cb7f89b7d1e944ddd4baaccff9019 Author: Jin Ma Date: Sun May 4 08:44:27 2025 -0600 [PATCH] RISC-V: Implment H modifier for printing the next register name For RV32 inline assembly, when handling 64-bit

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [to-be-committed][RISC-V] Adjust testcases and finish register move costing fix

https://gcc.gnu.org/g:f7d0410edf094d607da120f958c3d0b47d006e2c commit f7d0410edf094d607da120f958c3d0b47d006e2c Author: Jeff Law Date: Sun May 4 08:28:56 2025 -0600 [to-be-committed][RISC-V] Adjust testcases and finish register move costing fix The recent adjustment to more correc

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Remove unnecessary frm restore volatile define_insn

https://gcc.gnu.org/g:19829091ddc47d7fdcd47cfcde5c7d2c0be20c13 commit 19829091ddc47d7fdcd47cfcde5c7d2c0be20c13 Author: Pan Li Date: Sun May 4 09:26:02 2025 +0800 RISC-V: Remove unnecessary frm restore volatile define_insn After we add the frm register to the global_regs, we may no

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix missing implied Zicsr from Zve32x

https://gcc.gnu.org/g:5561ed024de75fd73b8d11e578b54fa7fb21bd6e commit 5561ed024de75fd73b8d11e578b54fa7fb21bd6e Author: Jerry Zhang Jian Date: Wed Apr 30 15:34:07 2025 +0800 RISC-V: Fix missing implied Zicsr from Zve32x The Zve32x extension depends on the Zicsr extension. Curre

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add intrinsics support for SiFive Xsfvcp extensions.

https://gcc.gnu.org/g:86335353527ef510a9fe6229418f313f6764c00e commit 86335353527ef510a9fe6229418f313f6764c00e Author: yulong Date: Tue Apr 29 21:12:02 2025 +0800 RISC-V: Add intrinsics support for SiFive Xsfvcp extensions. This version is same as v5, but rebase to trunk, send out

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions.

https://gcc.gnu.org/g:2e800ed614cc8596c462576cddb0afa47114a62c commit 2e800ed614cc8596c462576cddb0afa47114a62c Author: yulong Date: Tue Apr 29 21:12:03 2025 +0800 RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions. This commit adds testcases for Xsfvcp. Co-Auth

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Imply C from Zca whenever possible [PR119122]

https://gcc.gnu.org/g:e7e5a1180b0e6b1be3ffd9c1222e492139607c67 commit e7e5a1180b0e6b1be3ffd9c1222e492139607c67 Author: Yuriy Kolerov Date: Thu Apr 24 21:22:16 2025 -0600 [PATCH] RISC-V: Imply C from Zca whenever possible [PR119122] GCC must imply C extension from Zca extension whe

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Extract vector stepped for expand_const_vector [NFC]

https://gcc.gnu.org/g:f789cdaede74d5cbdb60bef631a14a6fb7025efb commit f789cdaede74d5cbdb60bef631a14a6fb7025efb Author: Pan Li Date: Thu Apr 17 10:27:17 2025 +0800 RISC-V: Extract vector stepped for expand_const_vector [NFC] Consider the expand_const_vector is quit long (about 500

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Extract vec_series for expand_const_vector [NFC]

https://gcc.gnu.org/g:8146b6eb1b61ab37a65397b7ee7abe5a49a173a0 commit 8146b6eb1b61ab37a65397b7ee7abe5a49a173a0 Author: Pan Li Date: Wed Apr 16 14:43:23 2025 +0800 RISC-V: Extract vec_series for expand_const_vector [NFC] Consider the expand_const_vector is quit long (about 500 line

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/119865] Don't free ggc allocated memory

https://gcc.gnu.org/g:f8d5c0a670b4cc7856f26a8722e60c082b26405b commit f8d5c0a670b4cc7856f26a8722e60c082b26405b Author: Jeff Law Date: Sat Apr 19 12:35:29 2025 -0600 [RISC-V][PR target/119865] Don't free ggc allocated memory Kaiweng's patch to stop freeing riscv_arch_string was cor

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Extract vec_duplicate for expand_const_vector [NFC]

https://gcc.gnu.org/g:84be3beef5084731e5936395f22a87b8a10b4f5c commit 84be3beef5084731e5936395f22a87b8a10b4f5c Author: Pan Li Date: Wed Apr 16 11:16:21 2025 +0800 RISC-V: Extract vec_duplicate for expand_const_vector [NFC] Consider the expand_const_vector is quit long (about 500 l

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] riscv: Add support for riscv*-gnu (GNU/Hurd on RISC-V)

https://gcc.gnu.org/g:dd04c59701a2f416ed7b1c0a22a3ec9296240f8d commit dd04c59701a2f416ed7b1c0a22a3ec9296240f8d Author: Hakan Candar Date: Fri Apr 18 07:08:44 2025 -0600 [PATCH] riscv: Add support for riscv*-gnu (GNU/Hurd on RISC-V) This produces a toolchain that can successfully b

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] [RISC-V]Support -mcpu for Xuantie cpu

https://gcc.gnu.org/g:3cbe4098f7865e3fb07aa0a6e35784e5bd583466 commit 3cbe4098f7865e3fb07aa0a6e35784e5bd583466 Author: Yixuan Chen Date: Tue Apr 22 04:45:44 2025 -0600 [PATCH] [RISC-V]Support -mcpu for Xuantie cpu Support -mcpu=xt-c908, xt-c908v, xt-c910, xt-c910v2, xt-c920, xt-c9

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [riscv] vec_dup immediate constants in pred_broadcast expand [PR118182]

https://gcc.gnu.org/g:9849e5ffa9cec8664b4ff4232b74ee0e33b4a537 commit 9849e5ffa9cec8664b4ff4232b74ee0e33b4a537 Author: Alexandre Oliva Date: Mon Apr 21 22:48:55 2025 -0300 [riscv] vec_dup immediate constants in pred_broadcast expand [PR118182] pr118182-2.c fails on gcc-14 because

[gcc/riscv/heads/gcc-15-with-riscv-opts] (83 commits) [RISC-V] Fix ICE due to bogus use of gen_rtvec

The branch 'riscv/heads/gcc-15-with-riscv-opts' was updated to point to: 5159c19cb2a8... [RISC-V] Fix ICE due to bogus use of gen_rtvec It previously pointed to: e968c7311c62... Alpha: Fix base block alignment calculation regression Diff: Summary of changes (added commits): -

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Fix missed bext discovery

https://gcc.gnu.org/g:9c84211ac0e0012622da9a63f1fbb30d3f64caef commit 9c84211ac0e0012622da9a63f1fbb30d3f64caef Author: Jeff Law Date: Fri Apr 18 12:19:30 2025 -0600 [RISC-V] Fix missed bext discovery RISC-V has the ability to extract a single bit out of a register from a fixed

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] [RISC-V] Tune for removal unnecessary sext in builtin overflows [PR108016]

https://gcc.gnu.org/g:ec8bf88125b77b8533eb9f8b74a0697a5ed99dee commit ec8bf88125b77b8533eb9f8b74a0697a5ed99dee Author: Alexey Merzlyakov Date: Fri Apr 18 06:45:10 2025 -0600 [PATCH] [RISC-V] Tune for removal unnecessary sext in builtin overflows [PR108016] It fixes one of the PR1

[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Do not free a riscv_arch_string when handling target-arch attribute

https://gcc.gnu.org/g:8b34e03a0527699f36e69fff4627ba60abe99cdc commit 8b34e03a0527699f36e69fff4627ba60abe99cdc Author: 翁愷邑 Date: Thu Apr 17 16:24:20 2025 -0600 [PATCH] RISC-V: Do not free a riscv_arch_string when handling target-arch attribute The build_target_option_node() funct

[gcc(refs/users/mikael/heads/refactor_descriptor_v05)] gimple-exec: Prise en charge TARGET_MEM_REF sans index ni step.

https://gcc.gnu.org/g:d2dd4bfabe8db40f740b18a6254035d2dc054627 commit d2dd4bfabe8db40f740b18a6254035d2dc054627 Author: Mikael Morin Date: Sun May 18 10:43:40 2025 +0200 gimple-exec: Prise en charge TARGET_MEM_REF sans index ni step. Diff: --- gcc/cgraphunit.cc | 67 ++

[gcc(refs/users/mikael/heads/refactor_descriptor_v05)] Correction régression class_67

https://gcc.gnu.org/g:cb16a9e756c1b6bbe15282a684a21c101ff79d89 commit cb16a9e756c1b6bbe15282a684a21c101ff79d89 Author: Mikael Morin Date: Sun May 18 11:20:40 2025 +0200 Correction régression class_67 Diff: --- gcc/fortran/trans-expr.cc | 4 +++- 1 file changed, 3 insertions(+), 1 deletio