[Bug target/110751] New: RISC-V: Suport undefined value that allows VSETVL PASS use TA/MA

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110751 Bug ID: 110751 Summary: RISC-V: Suport undefined value that allows VSETVL PASS use TA/MA Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal

[Bug target/110751] RISC-V: Suport undefined value that allows VSETVL PASS use TA/MA

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110751 --- Comment #16 from xuli1 at eswincomputing dot com --- (In reply to rguent...@suse.de from comment #12) > On Thu, 20 Jul 2023, juzhe.zhong at rivai dot ai wrote: > > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110751 > > > > --- Comment #

[Bug target/111076] RISC-V: segmentation fault during RTL pass: shorten (debug build)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111076 xuli1 at eswincomputing dot com changed: What|Removed |Added CC||xuli1 at eswincomputin

[Bug target/109725] [14 Regression] ICE: RTL check: expected code 'const_int', have 'reg' in riscv_print_operand, at config/riscv/riscv.cc:4430

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109725 xuli1 at eswincomputing dot com changed: What|Removed |Added CC||xuli1 at eswincomputin

[Bug target/109725] [14 Regression] ICE: RTL check: expected code 'const_int', have 'reg' in riscv_print_operand, at config/riscv/riscv.cc:4430

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109725 --- Comment #5 from xuli1 at eswincomputing dot com --- (In reply to xu...@eswincomputing.com from comment #4) > The gcc-13 branch also has the same issue > (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61), can I backport this > patch to gc

[Bug target/111161] [13 Regression] ICE: RTL check: expected code 'const_int', have 'reg' in riscv_print_operand, at config/riscv/riscv.cc:4394 during build

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61 xuli1 at eswincomputing dot com changed: What|Removed |Added CC||xuli1 at eswincomputin

[Bug target/111412] New: [release/gcc13 bug]RISC-V:ICE in phase 6 of vsetvl pass

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111412 Bug ID: 111412 Summary: [release/gcc13 bug]RISC-V:ICE in phase 6 of vsetvl pass Product: gcc Version: 13.0 Status: UNCONFIRMED Severity: normal Prior

[Bug target/110751] RISC-V: Suport undefined value that allows VSETVL PASS use TA/MA

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110751 xuli1 at eswincomputing dot com changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Reso

[Bug target/110751] RISC-V: Suport undefined value that allows VSETVL PASS use TA/MA

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110751 xuli1 at eswincomputing dot com changed: What|Removed |Added Status|RESOLVED|CLOSED --- Comment #4

[Bug target/111533] [14 Regression] ICE: RTL check: expected code 'reg', have 'const_int' in rhs_regno, at rtl.h:1934

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111533 xuli1 at eswincomputing dot com changed: What|Removed |Added CC||xuli1 at eswincomputin

[Bug target/111533] [14 Regression] ICE: RTL check: expected code 'reg', have 'const_int' in rhs_regno, at rtl.h:1934

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111533 --- Comment #3 from xuli1 at eswincomputing dot com --- The problem has been reproduced, thank you.

[Bug target/117283] [RISC-V] Miscompilation triggered by `__riscv_vsseg7e32_v_i32m1x7`, GCC 14.2.0 at `-O1`, `-O2`, `-O3`, and `-Os`.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117283 --- Comment #4 from xuli1 at eswincomputing dot com --- (In reply to xu...@eswincomputing.com from comment #3) > (In reply to Yibo He from comment #1) > > The data initialization is long, because I find that this bug is triggered > > when long d

[Bug target/117283] [RISC-V] Miscompilation triggered by `__riscv_vsseg7e32_v_i32m1x7`, GCC 14.2.0 at `-O1`, `-O2`, `-O3`, and `-Os`.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117283 xuli1 at eswincomputing dot com changed: What|Removed |Added CC||xuli1 at eswincomputin