[Bug modula2/112825] New: Modula 2 builds target objects as part of all-gcc

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112825 Bug ID: 112825 Summary: Modula 2 builds target objects as part of all-gcc Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component

[Bug rtl-optimization/112278] lra: ICE in partial_subreg_p for mixture of AdvSIMD & SVE register asms

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112278 Richard Sandiford changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/112891] [11/12/13/14 Regression] Missing vzeroupper insert

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112891 --- Comment #4 from Richard Sandiford --- (In reply to Hongtao Liu from comment #2) > So it looks like we need to handle ix86_avx_u128_mode_after > > --- a/gcc/config/i386/i386.cc > +++ b/gcc/config/i386/i386.cc > @@ -15177,7 +15177,14 @@ ix86

[Bug target/109078] Missing optimization on aarch64 for types like `float32x4x2_t`

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109078 Richard Sandiford changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/106694] Redundant move instructions in ARM SVE intrinsics use cases

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106694 Richard Sandiford changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug middle-end/101926] [meta-bug] struct/complex/other argument passing and return should be improved

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101926 Bug 101926 depends on bug 109391, which changed state. Bug 109391 Summary: Inefficient codegen on AArch64 when structure types are returned https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109391 What|Removed |Add

[Bug rtl-optimization/109391] Inefficient codegen on AArch64 when structure types are returned

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109391 Richard Sandiford changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/112933] gcc.target/aarch64/sme2/acle-asm/read_za16_vg1x2.c fails on aarch64_be

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112933 Richard Sandiford changed: What|Removed |Added Last reconfirmed||2023-12-09 Assignee|unass

[Bug target/112931] gcc.target/aarch64/sme2/acle-asm/write_za16_vg1x2.c ICEs on aarch64_be

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112931 Richard Sandiford changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org

[Bug target/112930] gcc.target/aarch64/sme/call_sm_switch_7.c ICEs on aarch64_be

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112930 Richard Sandiford changed: What|Removed |Added Last reconfirmed||2023-12-09 Status|UNCON

[Bug target/112930] gcc.target/aarch64/sme/call_sm_switch_7.c ICEs on aarch64_be

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112930 Richard Sandiford changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/112931] gcc.target/aarch64/sme2/acle-asm/write_za16_vg1x2.c ICEs on aarch64_be

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112931 Richard Sandiford changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/112933] gcc.target/aarch64/sme2/acle-asm/read_za16_vg1x2.c fails on aarch64_be

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112933 Richard Sandiford changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/112948] gcc/config/aarch64/aarch64-early-ra.cc:1953: possible cut'n'paste error ?

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112948 Richard Sandiford changed: What|Removed |Added Last reconfirmed||2023-12-11 Status|UNCON

[Bug target/109855] [14 Regression] ICE: in curr_insn_transform, at lra-constraints.cc:4231 unable to generate reloads for {aarch64_mlav4hi_vec_concatz_le} at -O1

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109855 --- Comment #3 from rsandifo at gcc dot gnu.org --- Looking at the mddump file, the output predicate and constraint seem to have gone AWOL: ;; /home/ricsan01/gnu/src/gcc/gcc/config/aarch64/aarch64-simd.md: 1554 (define_insn ("aarch64_mlav4hi_v

[Bug target/109855] [14 Regression] ICE: in curr_insn_transform, at lra-constraints.cc:4231 unable to generate reloads for {aarch64_mlav4hi_vec_concatz_le} at -O1

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109855 --- Comment #4 from rsandifo at gcc dot gnu.org --- I guess the problem is that the define_subst output template has: (match_operand: 0) which creates a new operand 0 with an empty predicate and constraint, as opposed to a (match_dup 0), wh

[Bug rtl-optimization/109940] [14 Regression] ICE in decide_candidate_validity since g:53dddbfeb213ac4ec39f550aa81eaa4264375d2c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109940 rsandifo at gcc dot gnu.org changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |rsandifo at gcc dot

[Bug target/109632] Inefficient codegen when complex numbers are emulated with structs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109632 --- Comment #12 from rsandifo at gcc dot gnu.org --- The patch in comment 11 is just a related spot improvement. The PR itself is still unfixed.

[Bug rtl-optimization/109940] [14 Regression] ICE in decide_candidate_validity since g:53dddbfeb213ac4ec39f550aa81eaa4264375d2c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109940 rsandifo at gcc dot gnu.org changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resoluti

[Bug target/109964] auto-vectorization of shift ignores integral promotions

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109964 --- Comment #4 from rsandifo at gcc dot gnu.org --- (In reply to Richard Biener from comment #3) > So the bug in the vectorizer is that it does > > t.ii:14:5: note: can narrow to signed:16 without loss of precision: _31 = > 1 >> _30; > t.ii:

[Bug target/110039] [14 Regression] FAIL: gcc.target/aarch64/rev16_2.c scan-assembler-times rev16\\tw[0-9]+ 2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110039 rsandifo at gcc dot gnu.org changed: What|Removed |Added CC||rsandifo at gcc dot gnu.or

[Bug target/110105] ARM GCC: underoptimization: expected vfma.f16, actual vcvtb-vfma.f32-vcvtb

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110105 rsandifo at gcc dot gnu.org changed: What|Removed |Added CC||rsandifo at gcc dot gnu.or

[Bug tree-optimization/110248] ivopts could under-cost for some addressing modes on len_{load,store}

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110248 --- Comment #5 from rsandifo at gcc dot gnu.org --- ivopts does have code to treat ifn pointer arguments specially, see get_mem_type_for_internal_fn &co. But like Kewen says, it's still only based on the mode. Personally I'd prefer an interna

[Bug testsuite/70150] Additonal test failures with --enable-default-pie

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70150 --- Comment #32 from rsandifo at gcc dot gnu.org --- (In reply to Xi Ruoyao from comment #31) > Richard: is it allowed to backport them (or the entire > https://gcc.gnu.org/pipermail/gcc-patches/2023-March/613093.html series) for > gcc-12? Yeah,

[Bug middle-end/106081] missed vectorization

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106081 --- Comment #7 from rsandifo at gcc dot gnu.org --- I don't think the splat creates a new layout, but instead a splat should be allowed to change its layout at zero cost.

[Bug tree-optimization/110449] Vect: use a small step to calculate the loop induction if the loop is unrolled during loop vectorization

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110449 rsandifo at gcc dot gnu.org changed: What|Removed |Added CC||rguenth at gcc dot gnu.org

[Bug tree-optimization/110485] vectorizing simd clone calls without loop masking applied

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110485 rsandifo at gcc dot gnu.org changed: What|Removed |Added CC||avieira at gcc dot gnu.org

[Bug middle-end/110495] fre introduces signed wrap for vector

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110495 --- Comment #2 from rsandifo at gcc dot gnu.org --- The point of the builder is that, if you know the pattern, you don't need to supply every element value to the builder. (And indeed you can't when the vector is variable length.) So something

[Bug target/110625] [AArch64] Vect: SLP fails to vectorize a loop as the reduction_latency calculated by new costs is too large

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110625 rsandifo at gcc dot gnu.org changed: What|Removed |Added CC||rsandifo at gcc dot gnu.or

[Bug target/110625] [AArch64] Vect: SLP fails to vectorize a loop as the reduction_latency calculated by new costs is too large

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110625 rsandifo at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED |ASSIGNED Assign

[Bug target/110625] [AArch64] Vect: SLP fails to vectorize a loop as the reduction_latency calculated by new costs is too large

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110625 --- Comment #7 from rsandifo at gcc dot gnu.org --- The current issue rate framework was originally written for Neoverse V1 and Neoverse V2. For those cores, it wasn't necessary to make a distinction between scalar integer operations and scala

[Bug middle-end/80283] [11/12/13/14 Regression] bad SIMD register allocation

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80283 --- Comment #39 from Richard Sandiford --- (In reply to Andrew Pinski from comment #38) > For aarch64, the test from comment #11 is so much worse on the trunk than in > GCC 13.2.0. I've been working on a fix for that. I'm hoping to post it today

[Bug tree-optimization/109543] Avoid using BLKmode for unions with a non-BLKmode member when possible

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109543 --- Comment #5 from Richard Sandiford --- I think the loop in compute_mode_layout needs to be smarter for unions. At the moment it's sensitive to field order, which doesn't make much conceptual sense. E.g. for the admittedly contrived example:

[Bug target/113027] New: aarch64 is missing vec_set and vec_extract for structure modes

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113027 Bug ID: 113027 Summary: aarch64 is missing vec_set and vec_extract for structure modes Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal

[Bug rtl-optimization/111702] [14 Regression] ICE: in insert_regs, at cse.cc:1114 with -O2 -fstack-protector-all -frounding-math

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111702 Richard Sandiford changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug target/113094] [14 Regression][aarch64] ICE in extract_constrain_insn, at recog.cc:2713 since r14-6290-g9f0f7d802482a8

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113094 Richard Sandiford changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org

[Bug target/112948] gcc/config/aarch64/aarch64-early-ra.cc:1953: possible cut'n'paste error ?

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112948 Richard Sandiford changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/113094] [14 Regression][aarch64] ICE in extract_constrain_insn, at recog.cc:2713 since r14-6290-g9f0f7d802482a8

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113094 Richard Sandiford changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug tree-optimization/113091] Over-estimate SLP vector-to-scalar cost for non-live pattern statement

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113091 --- Comment #5 from Richard Sandiford --- > The issue here is that because the "outer" pattern consumes > patt_64 = (int) patt_63 it should have adjusted _2 = (int) _1 > stmt-to-vectorize > as being the outer pattern root stmt for all this logi

[Bug tree-optimization/113104] Suboptimal loop-based slp node splicing across iterations

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113104 Richard Sandiford changed: What|Removed |Added Status|UNCONFIRMED |ASSIGNED Last reconfirmed|

[Bug target/113196] New: [14 Regression] Failure to use ushll{,2}

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113196 Bug ID: 113196 Summary: [14 Regression] Failure to use ushll{,2} Product: gcc Version: 14.0 Status: UNCONFIRMED Keywords: missed-optimization Severity: normal

[Bug target/113196] [14 Regression] Failure to use ushll{,2}

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113196 Richard Sandiford changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org

[Bug target/113220] [aarch64] ICE Segmentation fault with r14-6178-g8d29b7aca15133

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113220 Richard Sandiford changed: What|Removed |Added CC|richard.sandiford at arm dot com |rsandifo at gcc dot gnu.org

[Bug c++/68703] __attribute__((vector_size(N))) template member confusion

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68703 Richard Sandiford changed: What|Removed |Added CC||rsandifo at gcc dot gnu.org --- Comm

[Bug tree-optimization/113104] Suboptimal loop-based slp node splicing across iterations

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113104 Richard Sandiford changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/113270] [14 Regression] AArch64 ICEs in register_tuple_type since r14-6524

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113270 --- Comment #6 from Richard Sandiford --- I think we want the patch in comment 3, but in addition, I then also needed to use the following for a similar SVE case: extern GTY(()) tree scalar_types[NUM_VECTOR_TYPES + 1]; tree scalar_types[NUM_VEC

[Bug target/113270] [14 Regression] AArch64 ICEs in register_tuple_type since r14-6524

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113270 --- Comment #8 from Richard Sandiford --- Thanks for trying it, and sorry for not doing it myself. The patch LGTM FWIW, so preapproved if it passes testing (which I'm sure it will :))

[Bug target/112989] [14 Regression] GC ICE with C++, `#include ` and `-fsanitize=address`

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112989 Richard Sandiford changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org

[Bug target/112989] [14 Regression] GC ICE with C++, `#include ` and `-fsanitize=address`

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112989 --- Comment #12 from Richard Sandiford --- > another is try > #pragma GCC aarch64 "arm_sve.h" > after a couple of intentional declarations of the SVE builtins with > non-standard return/argument types and make sure that while it emits some > err

[Bug target/112989] [14 Regression] GC ICE with C++, `#include ` and `-fsanitize=address`

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112989 Richard Sandiford changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/113196] [14 Regression] Failure to use ushll{,2}

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113196 Richard Sandiford changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug rtl-optimization/111267] [14 Regression] Codegen regression from i386 argument passing changes

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111267 --- Comment #12 from Richard Sandiford --- I don't object to the patch, but for the record: the current heuristics go back a long way. Although I reworked the pass to use rtl-ssa a few years ago, I tried as far as possible to preserve the old h

[Bug target/109929] profiledbootstrap failure on aarch64-linux-gnu with graphite optimization

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109929 --- Comment #7 from Richard Sandiford --- Hmm, yeah, like you say, neither of those commits should have made a different to whether bootstrap works. I guess the problem is just latent now.

[Bug target/113485] [14 regression] ICE with -fno-guess-branch-probability on aarch64 starting with r14-7187-g74e3e839ab2d36

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113485 Richard Sandiford changed: What|Removed |Added Status|NEW |ASSIGNED --- Comment #7 from Richar

[Bug target/113572] [14 Regression] aarch64: internal compiler error in aarch64_sve::vector_cst_all_same

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113572 Richard Sandiford changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org

[Bug tree-optimization/113281] [14 Regression] Wrong code due to vectorization of shift reduction and missing promotions since r14-3027

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113281 Richard Sandiford changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org

[Bug tree-optimization/113576] [14 regression] 502.gcc_r hangs r14-8223-g1c1853a70f9422169190e65e568dcccbce02d95c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113576 --- Comment #13 from Richard Sandiford --- I don't think there's any principle that upper bits must be zero. How do we end up with a pattern that depends on that being the case?

[Bug target/113572] [14 Regression] aarch64: internal compiler error in aarch64_sve::vector_cst_all_same

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113572 Richard Sandiford changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/113485] [14 regression] ICE with -fno-guess-branch-probability on aarch64 starting with r14-7187-g74e3e839ab2d36

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113485 Richard Sandiford changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/113550] data512_t initializers dereference a clobbered register

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113550 Richard Sandiford changed: What|Removed |Added CC||rsandifo at gcc dot gnu.org

[Bug tree-optimization/113576] [14 regression] 502.gcc_r hangs r14-8223-g1c1853a70f9422169190e65e568dcccbce02d95c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113576 --- Comment #16 from Richard Sandiford --- (In reply to Richard Biener from comment #15) > I think the problem is the cbranch pattern which looks at all of the > QImode mask - but of course it doesn't know it's really V4BImode it's > working on

[Bug tree-optimization/113576] [14 regression] 502.gcc_r hangs r14-8223-g1c1853a70f9422169190e65e568dcccbce02d95c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113576 --- Comment #18 from Richard Sandiford --- (In reply to Tamar Christina from comment #17) > Well the mid-end has generated the right precision. The type it generates is > vector(4) vexit_reduc_67; > so it does say it's a single bit boolean. >

[Bug target/113613] [14 Regression] Missing ldp/stp optimization since r14-6290-g9f0f7d802482a8

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113613 Richard Sandiford changed: What|Removed |Added Status|NEW |ASSIGNED Assignee|unassig

[Bug tree-optimization/113281] Wrong code due to vectorization of shift reduction and missing promotions since r14-3027

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113281 --- Comment #24 from Richard Sandiford --- Fixed on trunk so far, but it's latent on branches. I'll see what the trunk fallout is like before asking about backports.

[Bug debug/113636] [14 Regression] internal compiler error: in dead_debug_global_find, at valtrack.cc:275 since r14-6290-g9f0f7d802482a8

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113636 Richard Sandiford changed: What|Removed |Added Status|UNCONFIRMED |ASSIGNED Ever confirmed|0

[Bug target/113623] [14 Regression] ICE in aarch64_pair_mem_from_base since r14-6605

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113623 Richard Sandiford changed: What|Removed |Added Status|NEW |ASSIGNED Assignee|unassig

[Bug target/111677] [12/13 Regression] darktable build on aarch64 fails with unrecognizable insn due to -fstack-protector changes

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111677 --- Comment #21 from Richard Sandiford --- (In reply to Alex Coplan from comment #13) > The problem seems to be this code in aarch64_process_components: > > while (regno != last_regno) > { > bool frame_related_p = aarch64_emit_cfi_f

[Bug target/113623] [14 Regression] ICE in aarch64_pair_mem_from_base since r14-6605

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113623 Richard Sandiford changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug debug/113636] [14 Regression] internal compiler error: in dead_debug_global_find, at valtrack.cc:275 since r14-6290-g9f0f7d802482a8

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113636 Richard Sandiford changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug tree-optimization/113576] [14 regression] 502.gcc_r hangs r14-8223-g1c1853a70f9422169190e65e568dcccbce02d95c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113576 --- Comment #30 from Richard Sandiford --- (In reply to Richard Biener from comment #29) > But that's just for CONSTRUCTORs, we got the VIEW_CONVERT_EXPR path for > VECTOR_CSTs. But yeah, that _might_ argue we should perform the same > masking

[Bug tree-optimization/113576] [14 regression] 502.gcc_r hangs r14-8223-g1c1853a70f9422169190e65e568dcccbce02d95c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113576 --- Comment #34 from Richard Sandiford --- (In reply to Richard Biener from comment #32) > Btw, AVX512 knotb will invert all 8 bits and there's no knot just affecting > the lowest 4 or 2 bits. > > It all feels like desaster waiting to happen ;)

[Bug target/113763] [14 Regression] build fails with clang++ host compiler because aarch64.cc uses C++14 constexpr.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113763 --- Comment #11 from Richard Sandiford --- Currently away so can't try it myself, but how about just using an ad-hoc structure instead?

[Bug target/113763] [14 Regression] build fails with clang++ host compiler because aarch64.cc uses C++14 constexpr.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113763 --- Comment #14 from Richard Sandiford --- AFAIK, the constructor shouldn't be necessary. (And without it, the whole thing would fit on one line.) LGTM (and preapproved) otherwise. Thanks for doing this.

[Bug rtl-optimization/115281] [14 Regression] aarch64 ICE in go_through_subreg after r14-5129

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115281 Richard Sandiford changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/115464] ICE when building libaom on arm64 (neon sve bridge usage with tbl/perm)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115464 Richard Sandiford changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org

[Bug target/115464] [14 Backport] ICE when building libaom on arm64 (neon sve bridge usage with tbl/perm)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115464 Richard Sandiford changed: What|Removed |Added Known to work||15.0 Known to fail|

[Bug target/115464] [14 Backport] ICE when building libaom on arm64 (neon sve bridge usage with tbl/perm)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115464 --- Comment #11 from Richard Sandiford --- Yeah, like I mentioned in the commit message, I'm in the process of rolling this fix out to more places. Was just testing the waters with the minimal fix for comment 4. But yeah, maybe more of it will

[Bug target/115518] New: aarch64: Poor codegen for arm_neon_sve_bridge.h

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115518 Bug ID: 115518 Summary: aarch64: Poor codegen for arm_neon_sve_bridge.h Product: gcc Version: 15.0 Status: UNCONFIRMED Keywords: aarch64-sve Severity: normal P

[Bug rtl-optimization/114996] [15 Regression] [RISC-V] 2->2 combination no longer occurring

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114996 Richard Sandiford changed: What|Removed |Added CC||rsandifo at gcc dot gnu.org --- Com

[Bug rtl-optimization/106594] [13/14/15 Regression] sign-extensions no longer merged into addressing mode

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106594 Richard Sandiford changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug rtl-optimization/114515] [15 Regression] Failure to use aarch64 lane forms after PR101523

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114515 Richard Sandiford changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/115610] New: -flate-combine disabled by default for x86 port

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115610 Bug ID: 115610 Summary: -flate-combine disabled by default for x86 port Product: gcc Version: 15.0 Status: UNCONFIRMED Keywords: missed-optimization Severity: enhancemen

[Bug target/115612] New: powerpc: define_insn_and_splits calling gen_reg_rtx unconditionally

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115612 Bug ID: 115612 Summary: powerpc: define_insn_and_splits calling gen_reg_rtx unconditionally Product: gcc Version: 15.0 Status: UNCONFIRMED Keywords: ice-on-val

[Bug target/115613] New: xtensa: splits dependent on can_create_pseudo_p

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115613 Bug ID: 115613 Summary: xtensa: splits dependent on can_create_pseudo_p Product: gcc Version: 15.0 Status: UNCONFIRMED Keywords: ice-on-valid-code Severity: normal

[Bug target/115478] [15 Regression] gcc.target/aarch64/bitint-args.c fails since r15-1120-g2277f987979445

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115478 Richard Sandiford changed: What|Removed |Added CC||rsandifo at gcc dot gnu.org --- Com

[Bug other/115622] gcc.dg/ipa/iinline-attr.c fails after r15-1579-g792f97b44ffc5e

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115622 --- Comment #1 from Richard Sandiford --- Are you sure about the bisection? late-combine only affects RTL, and in any case is disabled by default for powerpc.

[Bug target/115631] [15 Regression] GCN: [-PASS:-]{+FAIL:+} c-c++-common/torture/builtin-arith-overflow-6.c -O2 execution test

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115631 --- Comment #2 from Richard Sandiford --- I suppose for issues like this, it would be useful to have a debug counter to bisect on. I'll post a patch for doing that today, but I'm afraid I'll be relying on someone with gcn access to actually do

[Bug target/115633] [15 Regression] powerpc64le: "relocation truncated to fit: R_PPC64_TOC16 against `.rodata.cst4'" with (default) '-flate-combine-instructions'

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115633 --- Comment #2 from Richard Sandiford --- -flate-combine-instructions is supposed to be disabled by default for all powerpc targets. Could you look at why that isn't the case for you?

[Bug target/115631] [15 Regression] GCN: [-PASS:-]{+FAIL:+} c-c++-common/torture/builtin-arith-overflow-6.c -O2 execution test

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115631 --- Comment #3 from Richard Sandiford --- I've now pushed a debug counter for late_combine. Sorry to ask, but could you bisect on N in -fdbg-cnt=late_combine:N to see which transformation is causing the problem?

[Bug target/115631] [15 Regression] GCN: [-PASS:-]{+FAIL:+} c-c++-common/torture/builtin-arith-overflow-6.c -O2 execution test

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115631 --- Comment #4 from Richard Sandiford --- Created attachment 58513 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=58513&action=edit A patch for a bug seen on arm*-*-* Also, could you check whether the attached patch makes any difference?

[Bug ipa/114531] Feature proposal for an `-finline-functions-aggressive` compiler option

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114531 --- Comment #17 from Richard Sandiford --- I can see that it's useful to ask whether the current -O2 & -O3 inlining heuristics are making the right trade-off. But I think that's really a different issue from the one that is raised in the PR. (

[Bug target/115634] [15 regression] s390 bootstrap failure since r15-1579-g792f97b44ffc5e

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115634 --- Comment #3 from Richard Sandiford --- Yeah, I agree that sounds like the right fix. Specifically, I assume s390_decompose_addrstyle_without_index, when doing: if (op && GET_CODE (op) != REG) return false; should check whether the re

[Bug rtl-optimization/115677] ICE when building argon2 with -flate-combine-instructions on amd64

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115677 Richard Sandiford changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org

[Bug rtl-optimization/115677] ICE when building argon2 with -flate-combine-instructions on amd64

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115677 Richard Sandiford changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug tree-optimization/115629] Inefficient if-convert of masked conditionals

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115629 Richard Sandiford changed: What|Removed |Added CC||rsandifo at gcc dot gnu.org --- Com

[Bug rtl-optimization/115782] ICE on valid code at -O{2,3} with "-fno-guess-branch-probability -fgcse-sm -fno-expensive-optimizations -fno-gcse" on x86_64-linux-gnu: in possibly_queue_changes, at rtl-

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115782 Richard Sandiford changed: What|Removed |Added Last reconfirmed||2024-07-05 Status|UNCON

[Bug rtl-optimization/115785] ICE when building embree-4.3.1 on amd64 with -flate-combine-instructions

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115785 Richard Sandiford changed: What|Removed |Added Status|UNCONFIRMED |ASSIGNED Assignee|unassig

[Bug ipa/114531] Feature proposal for an `-finline-functions-aggressive` compiler option

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114531 --- Comment #20 from Richard Sandiford --- (In reply to Jan Hubicka from comment #18) > I am trying to understand how useful this is. I am basically worried > about two things > 1) we have other optimization passes that behave differently at -

[Bug rtl-optimization/115785] ICE when building embree-4.3.1 on amd64 with -flate-combine-instructions

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115785 --- Comment #2 from Richard Sandiford --- The patch in #c1 is just part 1. Part 2 will fix the bug.

[Bug rtl-optimization/115782] [15 Regression] ICE on valid code at -O{2,3} with "-fno-guess-branch-probability -fgcse-sm -fno-expensive-optimizations -fno-gcse" on x86_64-linux-gnu: in possibly_queue_

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115782 Richard Sandiford changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

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