[Bug target/99143] Bad section alignment on AArch64

2021-03-01 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99143 Richard Earnshaw changed: What|Removed |Added Status|WAITING |RESOLVED Resolution|---

[Bug target/99271] [10 regression] Wrong code for Arm-v8-m.main CMSE calling __gnu_cmse_nonsecure_call

2021-03-01 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99271 Richard Earnshaw changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/99551] aarch64: csel is used for cold scalar computation which affects performance

2021-03-11 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99551 --- Comment #1 from Richard Earnshaw --- probably one of the if-conversion passes.

[Bug target/99724] [11 Regression] CE in in extract_insn, at recog.c:2770

2021-03-23 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99724 Richard Earnshaw changed: What|Removed |Added Last reconfirmed||2021-03-23 Status|UNCONFI

[Bug target/99773] ARM v8.1-m MVE interaction with -mfloat-abi not clear

2021-03-25 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99773 --- Comment #1 from Richard Earnshaw --- -march=armv8.1-m.main+mve -mfloat-abi=hard should use the VFP registers for passing any FP arguments so the build attribute for Tag_ABI_VFP_args should be set to show that. It's true that soft-float routi

[Bug target/99773] ARM v8.1-m MVE interaction with -mfloat-abi not clear

2021-03-26 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99773 --- Comment #4 from Richard Earnshaw --- (In reply to Christophe Lyon from comment #3) > I tried changing TARGET_HARD_FLOAT_SUB in arm.h to: > #define TARGET_HARD_FLOAT_SUB (arm_float_abi != ARM_FLOAT_ABI_SOFT\ >

[Bug target/99836] aarch64: -fpatchable-function-entry=N[,0] should place .cfi_startproc before NOPs

2021-03-31 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99836 Richard Earnshaw changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug debug/98776] DW_AT_low_pc is inconsistent with function entry address, when enabling -fpatchable-function-entry

2021-03-31 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98776 Richard Earnshaw changed: What|Removed |Added CC||i at maskray dot me --- Comment #1 fr

[Bug target/99890] The -mstrict-align doesn't support the ARM targets

2021-04-06 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99890 Richard Earnshaw changed: What|Removed |Added Status|WAITING |RESOLVED Resolution|---

[Bug target/100067] New: Unexpected warning for -mcpu=neoverse-n1 when configured with --with-fpu

2021-04-13 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100067 Bug ID: 100067 Summary: Unexpected warning for -mcpu=neoverse-n1 when configured with --with-fpu Product: gcc Version: 11.0 Status: UNCONFIRMED Severity: norma

[Bug target/100067] Unexpected warning for -mcpu=neoverse-n1 when configured with --with-fpu

2021-04-14 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100067 Richard Earnshaw changed: What|Removed |Added Ever confirmed|0 |1 Last reconfirmed|

[Bug target/100067] Unexpected warning for -mcpu=neoverse-n1 when configured with --with-fpu

2021-04-15 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100067 --- Comment #4 from Richard Earnshaw --- (In reply to Christophe Lyon from comment #3) > Unfortunately this is causing many regressions in the GCC testsuite. Sigh! I'm not entirely surprised. I suspect most of this is testisms, though. > >

[Bug target/84547] Suboptimal code for int128 masked shifts (ARM64)

2021-04-19 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84547 --- Comment #2 from Richard Earnshaw --- (In reply to Andrew Pinski from comment #1) > Yes int128 (or rather double wide register) shifts are not optimized that > well. They are not used by many people even. I wonder if there is a way to > use

[Bug target/95816] Aarch64 jumps between Hot/Cold sections does not clobber registers x16/x17

2021-04-21 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95816 --- Comment #2 from Richard Earnshaw --- (In reply to Andrew Pinski from comment #1) > Confirmed, I wonder if x16 and x17 should not be considered as temps alive > across all jumps in aarch64 really; not just jumps between hot and cold > sections

[Bug target/95816] Aarch64 jumps between Hot/Cold sections does not clobber registers x16/x17

2021-04-21 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95816 --- Comment #3 from Richard Earnshaw --- The best thing to do for now is to disable hot/cold partitioning, as we do on Arm.

[Bug target/100214] UB in arm.c:optimal_immediate_sequence_1 (left shift of 255 by 30 places cannot be represented in type 'int')

2021-04-23 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100214 Richard Earnshaw changed: What|Removed |Added Last reconfirmed||2021-04-23 Status|UNCONF

[Bug target/100216] arm: UB in arm_canonicalize_comparison (shift exponent 127 is too large for 64-bit type)

2021-04-23 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100216 Richard Earnshaw changed: What|Removed |Added Ever confirmed|0 |1 Last reconfirmed|

[Bug target/97534] [10/11 Regression] ICE in decompose, at rtl.h:2280 (arm-linux-gnueabihf)

2020-11-12 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97534 --- Comment #5 from Richard Earnshaw --- No, I don't think it's related to that, in fact, I think this is just a latent bug that's been in the code for a long time. At one point we have a 32-bit signed integer containing INT_MIN, which is intern

[Bug target/97534] [10/11 Regression] ICE in decompose, at rtl.h:2280 (arm-linux-gnueabihf)

2020-11-24 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97534 Richard Earnshaw changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug target/95908] [AArch64] wrong code with ILP32 and -fwrapv

2020-11-25 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95908 --- Comment #1 from Richard Earnshaw --- I'm sure the code we generate doesn't match your expectations. What's more, I don't think it's really practical to meet them. To do so would require emitting a mask operation after practically every ar

[Bug target/94993] aarch64 incompatible with -mgeneral-regs-only

2020-11-25 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94993 Richard Earnshaw changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[Bug target/98759] arm cortex-r5 single precisions flotaing point generation

2021-01-20 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98759 Richard Earnshaw changed: What|Removed |Added Resolution|--- |INVALID Status|UNCONFIRME

[Bug target/98681] [8/9/10/11 Regression] aarch64: Invalid ubfiz instruction rejected by assembler

2021-01-22 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98681 --- Comment #5 from Richard Earnshaw --- Patch looks generally sensible, but I think all the INTVALs in that expression should be converted to UINTVAL. The mask, in particular, is unsigned and it is weird that one moment we're using a unsigned v

[Bug target/82150] Produces a branch prefetch which causes a hang

2021-01-28 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82150 Richard Earnshaw changed: What|Removed |Added Resolution|--- |INVALID Status|UNCONFIRME

[Bug target/82150] Produces a branch prefetch which causes a hang

2021-01-29 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82150 Richard Earnshaw changed: What|Removed |Added Last reconfirmed||2021-01-29 Ever confirmed|0

[Bug target/82150] Produces a branch prefetch which causes a hang

2021-01-29 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82150 Richard Earnshaw changed: What|Removed |Added Status|WAITING |RESOLVED Resolution|---

[Bug target/99271] New: [10/11 regression] Wrong code for Arm-v8-m.main CMSE calling __gnu_cmse_nonsecure_call

2021-02-25 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99271 Bug ID: 99271 Summary: [10/11 regression] Wrong code for Arm-v8-m.main CMSE calling __gnu_cmse_nonsecure_call Product: gcc Version: 10.0 Status: UNCONFIRMED Key

[Bug target/99271] [10/11 regression] Wrong code for Arm-v8-m.main CMSE calling __gnu_cmse_nonsecure_call

2021-02-25 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99271 Richard Earnshaw changed: What|Removed |Added Ever confirmed|0 |1 Last reconfirmed|

[Bug target/99271] [10 regression] Wrong code for Arm-v8-m.main CMSE calling __gnu_cmse_nonsecure_call

2021-02-25 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99271 Richard Earnshaw changed: What|Removed |Added Summary|[10/11 regression] Wrong|[10 regression] Wrong code

[Bug target/100236] arm: UB in arm_compute_save_core_reg_mask (shift exponent 4294967295 is too large for 32-bit type 'int')

2021-04-26 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100236 Richard Earnshaw changed: What|Removed |Added Ever confirmed|0 |1 Last reconfirmed|

[Bug target/100236] arm: UB in arm_compute_save_core_reg_mask (shift exponent 4294967295 is too large for 32-bit type 'int')

2021-04-27 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100236 --- Comment #4 from Richard Earnshaw --- Fixed on master so far.

[Bug rtl-optimization/100311] UB in sel-sched.c:init_regs_for_mode with -march=armv8-m.base

2021-04-28 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100311 Richard Earnshaw changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[Bug rtl-optimization/100311] UB in sel-sched.c:init_regs_for_mode with -march=armv8-m.base

2021-04-29 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100311 Richard Earnshaw changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug other/63426] [meta-bug] Issues found with -fsanitize=undefined

2021-04-29 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63426 Bug 63426 depends on bug 100311, which changed state. Bug 100311 Summary: UB in sel-sched.c:init_regs_for_mode with -march=armv8-m.base https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100311 What|Removed |Added --

[Bug c++/100412] New: [11/12 regression] PASS & FAIL for same test aarch64-qemu: gcc.dg/Wvla-parameter-[23].c pr?????

2021-05-04 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100412 Bug ID: 100412 Summary: [11/12 regression] PASS & FAIL for same test aarch64-qemu: gcc.dg/Wvla-parameter-[23].c pr? Product: gcc Version: 11.0 Status: UNCONFIRMED

[Bug target/63521] The AArch64 backend doesn't define REG_ALLOC_ORDER.

2021-05-04 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63521 Richard Earnshaw changed: What|Removed |Added Status|ASSIGNED|NEW Assignee|jiwang at gcc

[Bug target/86209] Peephole does not happen because the type of zero/sign extended operands is not the same.

2021-05-04 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86209 Richard Earnshaw changed: What|Removed |Added Status|ASSIGNED|NEW Assignee|sameerad at gc

[Bug c++/100412] [11/12 regression] PASS & FAIL for same test aarch64-qemu: gcc.dg/Wvla-parameter-[23].c pr?????

2021-05-04 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100412 --- Comment #2 from Richard Earnshaw --- The test name comes from the file name, the 'test for warnings' and the line number. Since both warnings are on the same line, that would require some major hackery (unless that can be encoded in the dg-

[Bug target/100432] gcc arm compilation binary output is bigger with -Os than -O2

2021-05-05 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100432 Richard Earnshaw changed: What|Removed |Added Status|UNCONFIRMED |WAITING Ever confirmed|0

[Bug target/100563] [10/11/12 Regression] arm: ICE in arm_gen_dicompare_reg, at config/arm/arm.c:15976

2021-05-12 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100563 --- Comment #2 from Richard Earnshaw --- Er, wow, I'm surprised this hasn't come up before. The problem is that the cstore_cc pattern in arm.md has no predicates on the operands and no constraints on the modes of those operands and yet it then

[Bug target/100563] [10/11/12 Regression] arm: ICE in arm_gen_dicompare_reg, at config/arm/arm.c:15976

2021-05-12 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100563 Richard Earnshaw changed: What|Removed |Added Ever confirmed|0 |1 Assignee|unassigned at g

[Bug target/99908] SIMD: negating logical + if_else has a suboptimal codegen.

2021-05-12 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99908 --- Comment #7 from Richard Earnshaw --- (In reply to Hongtao.liu from comment #6) > Should be fixed in trunk. The original report was about arm. None of your changes are outside of the x86 backend, so no, this is not fixed for the original rep

[Bug target/99908] SIMD: negating logical + if_else has a suboptimal codegen.

2021-05-12 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99908 --- Comment #8 from Richard Earnshaw --- Never mind, the original reference to arm was not the 'arm cpu', my mistake.

[Bug target/100563] [10/11 Regression] arm: ICE in arm_gen_dicompare_reg, at config/arm/arm.c:15976

2021-05-13 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100563 Richard Earnshaw changed: What|Removed |Added Summary|[10/11/12 Regression] arm: |[10/11 Regression] arm: ICE

[Bug target/100563] [10/11 Regression] arm: ICE in arm_gen_dicompare_reg, at config/arm/arm.c:15976

2021-05-13 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100563 Richard Earnshaw changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug testsuite/100713] New: g++.dg/cpp1y/lambda-generic-90842.C has ambiguous pass and fail

2021-05-21 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100713 Bug ID: 100713 Summary: g++.dg/cpp1y/lambda-generic-90842.C has ambiguous pass and fail Product: gcc Version: 11.0 Status: UNCONFIRMED Severity: normal

[Bug testsuite/100713] g++.dg/cpp1y/lambda-generic-90842.C has ambiguous pass and fail

2021-05-21 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100713 Richard Earnshaw changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/100767] New: arm: ice when inlining at -flto with different cpu and arch settings

2021-05-26 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100767 Bug ID: 100767 Summary: arm: ice when inlining at -flto with different cpu and arch settings Product: gcc Version: 11.0 Status: UNCONFIRMED Severity: normal

[Bug target/100767] arm: ice when inlining at -flto with different cpu and arch settings

2021-05-26 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100767 Richard Earnshaw changed: What|Removed |Added Status|UNCONFIRMED |ASSIGNED Last reconfirmed|

[Bug target/100767] arm: ice when inlining at -flto with different cpu and arch settings

2021-05-26 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100767 --- Comment #1 from Richard Earnshaw --- The problem is that we call arm_configure_build_target() with arm_configure_build_target (&caller_target, caller_opts, &global_options_set, false); But that doesn't make sense in reality - global_opti

[Bug target/100767] arm: ice when inlining at -flto with different cpu and arch settings

2021-05-27 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100767 --- Comment #3 from Richard Earnshaw --- fixed on master so far.

[Bug target/100767] arm: ice when inlining at -flto with different cpu and arch settings

2021-05-27 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100767 --- Comment #5 from Richard Earnshaw --- Also fixed for gcc-11. Will consider backporting further, but patches no-longer apply cleanly on gcc-10.

[Bug target/95650] aarch64: Missed optimization storing addition of two shorts

2021-06-01 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95650 --- Comment #6 from Richard Earnshaw --- AArch32 is able to produce the optimal sequence because the ABI specifies caller widening of parameters. For safety reasons AArch64 takes the opposite approach and requires the callee to narrow arguments.

[Bug target/84467] Choosing between Integer and NEON for 64-bit operations

2021-06-01 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84467 Richard Earnshaw changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug rtl-optimization/87871] [9/10/11/12 Regression] testcases fail after r265398 on arm

2021-06-01 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87871 Richard Earnshaw changed: What|Removed |Added Status|NEW |WAITING --- Comment #66 from Richard

[Bug rtl-optimization/87871] [9/10/11/12 Regression] testcases fail after r265398 on arm

2021-06-01 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87871 --- Comment #68 from Richard Earnshaw --- (In reply to Christophe Lyon from comment #67) > According to gcc-testresults, we still see: > FAIL: gcc.dg/ira-shrinkwrap-prep-1.c scan-rtl-dump pro_and_epilogue > "Performing shrink-wrapping" > FAIL: gc

[Bug target/108442] arm: MVE's vld1* and vst1* do not work when __ARM_MVE_PRESERVE_USER_NAMESPACE is defined

2023-01-18 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108442 Richard Earnshaw changed: What|Removed |Added Last reconfirmed||2023-01-18 Ever confirmed|0

[Bug target/108442] arm: MVE's vld1* and vst1* do not work when __ARM_MVE_PRESERVE_USER_NAMESPACE is defined

2023-01-18 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108442 --- Comment #3 from Richard Earnshaw --- https://gcc.gnu.org/pipermail/gcc-patches/2021-December/587296.html

[Bug target/108442] arm: MVE's vld1* and vst1* do not work when __ARM_MVE_PRESERVE_USER_NAMESPACE is defined

2023-01-18 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108442 --- Comment #5 from Richard Earnshaw --- Fixed on master. While this is not a regression, we should consider a backport.

[Bug target/103100] [11/12/13 Regression] unaligned access generated with memset or {} and -O2 -mstrict-align

2023-01-20 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103100 --- Comment #14 from Richard Earnshaw --- (In reply to Richard Biener from comment #13) > (In reply to Andrew Pinski from comment #10) > > Updated patch submitted: > > https://gcc.gnu.org/pipermail/gcc-patches/2022-January/589254.html > > I thi

[Bug target/108515] Fails to link fixincl with unresolvable R_ARM_MOVW_ABS_NC reloca tion against symbol `stderr@@GLIBC_2.4'

2023-01-24 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108515 --- Comment #10 from Richard Earnshaw --- Almost certainly this is related to the need for a copyreloc and presumably the linker has not created one for some reason. So I suspect this is most likely a binutils issue rather than a compiler one.

[Bug target/108515] Fails to link fixincl with unresolvable R_ARM_MOVW_ABS_NC reloca tion against symbol `stderr@@GLIBC_2.4'

2023-01-24 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108515 Richard Earnshaw changed: What|Removed |Added Resolution|INVALID |FIXED --- Comment #13 from Richard E

[Bug target/108515] Fails to link fixincl with unresolvable R_ARM_MOVW_ABS_NC reloca tion against symbol `stderr@@GLIBC_2.4'

2023-01-24 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108515 Richard Earnshaw changed: What|Removed |Added Resolution|FIXED |INVALID

[Bug target/100000] non-leaf epologue/prologue used if MVE v4sf is used for load/return

2023-01-25 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=10 --- Comment #2 from Richard Earnshaw --- If the testcase is built with -march=armv8.1-m.main+mve.fp then the useless stack adjustments go away. I think that's because V4SFmode is not a supported vector mode for integer MVE - see arm_vector_mode

[Bug target/100000] non-leaf epologue/prologue used if MVE v4sf is used for load/return

2023-01-25 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=10 --- Comment #3 from Richard Earnshaw --- Given that the hard-float ABI essentially requires V4SF as a type, it might be better to consider this mode supported unconditionally in this case, and although that might make the compiler try some point

[Bug target/103100] [11/12/13 Regression] unaligned access generated with memset or {} and -O2 -mstrict-align

2023-01-31 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103100 --- Comment #19 from Richard Earnshaw --- (In reply to Andrew Pinski from comment #18) > I should say that testcase happens at `-Os -mstrict-align`, at `-O2 > -mstrict-align` it works. Because for -Os we don't forcibly align arrays - see AARCH

[Bug ipa/108470] Missing documentation for alternate uses of __attribute__((noinline))

2023-02-09 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108470 --- Comment #3 from Richard Earnshaw --- The manual entry for this says "This attribute is supported mainly for the purpose of testing the compiler." which suggests a lack of long-term commitment to the option. Perhaps it would be better to rem

[Bug target/108943] ARM Unaligned memory access with high optimizer levels

2023-02-27 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108943 Richard Earnshaw changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug driver/104614] New: "Undocumented" option flag ignored with --help=target

2022-02-21 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104614 Bug ID: 104614 Summary: "Undocumented" option flag ignored with --help=target Product: gcc Version: 12.0 Status: UNCONFIRMED Severity: normal Priority: P3 Compo

[Bug driver/104614] "Undocumented" option flag ignored with --help=target

2022-02-21 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104614 --- Comment #1 from Richard Earnshaw --- Note the manual says for 'Undocumented' @item Undocumented The option is deliberately missing documentation and should not be included in the @option{--help} output.

[Bug driver/104614] "Undocumented" option flag ignored with --help=target

2022-02-21 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104614 --- Comment #2 from Richard Earnshaw --- This case is also wrong: mhard-float Target RejectNegative Alias(mfloat-abi=, hard) Undocumented produces: -mhard-floatSame as -mfloat-abi=hard. Which, while not inaccurate, means th

[Bug other/102664] contrib/gcc-git-customization.sh uses echo -n, which isn't portable

2022-03-09 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102664 --- Comment #28 from Richard Earnshaw --- I think the 'echo -n' problem can be solved by changing the one instance of that operation (in ask()) to printf "%s" "$question [$default]? " But I don't have the machines that are problematic to test

[Bug other/102664] contrib/gcc-git-customization.sh uses echo -n, which isn't portable

2022-03-09 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102664 --- Comment #29 from Richard Earnshaw --- Suggested patch: https://gcc.gnu.org/pipermail/gcc-patches/2022-March/591455.html

[Bug other/102664] contrib/gcc-git-customization.sh uses echo -n, which isn't portable

2022-03-11 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102664 --- Comment #36 from Richard Earnshaw --- Can this be closed now?

[Bug tree-optimization/105090] BFI instructions are not generated on arm-none-eabi-g++

2022-03-29 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105090 --- Comment #1 from Richard Earnshaw --- This was fallout from some changes made internally in the compiler in around the gcc-10 timeframe, but it really just exposed a more general problem with the failure to detect opportunities to use bitfiel

[Bug tree-optimization/105090] BFI instructions are not generated on arm-none-eabi-g++

2022-03-29 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105090 Richard Earnshaw changed: What|Removed |Added Last reconfirmed||2022-03-29 Ever confirmed|0

[Bug target/104414] [AArch64] About the condition of calls_alloca in aarch64_layout_frame

2022-03-30 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104414 Richard Earnshaw changed: What|Removed |Added Resolution|--- |INVALID Status|UNCONFIRM

[Bug target/100106] [10 Regression] ICE in gen_movdi, at config/arm/arm.md:6187 since r10-2840-g70cdb21e

2022-04-08 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100106 --- Comment #8 from Richard Earnshaw --- (In reply to CVS Commits from comment #7) > The releases/gcc-11 branch has been updated by Richard Biener > : > > https://gcc.gnu.org/g:5155015ce57dc133e006f87fdf0237a5f259bebd > Just to note that on m

[Bug target/68605] Add -mno-crt0 to disable automatic crt0 injection

2022-04-08 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68605 Richard Earnshaw changed: What|Removed |Added Resolution|--- |WONTFIX Status|UNCONFIRME

[Bug target/68605] Add -mno-crt0 to disable automatic crt0 injection

2022-04-08 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68605 --- Comment #5 from Richard Earnshaw --- If you look at the examples I cite you'll find they rarely, if ever, change because of changes to GCC. This interface has been stable for year.

[Bug target/68605] Add -mno-crt0 to disable automatic crt0 injection

2022-04-08 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68605 --- Comment #6 from Richard Earnshaw --- That should have said 'years'.

[Bug target/104144] [12 Regression] build fails due to: Error: unknown architecture `armv9-a'

2022-04-12 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104144 Richard Earnshaw changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug tree-optimization/101755] [12 regression] gcc.target/arm/reg_equal_test.c fails on arm since r12-2637

2022-04-12 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101755 Richard Earnshaw changed: What|Removed |Added Status|UNCONFIRMED |ASSIGNED Last reconfirmed|

[Bug tree-optimization/101755] [12 regression] gcc.target/arm/reg_equal_test.c fails on arm since r12-2637

2022-04-12 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101755 Richard Earnshaw changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/105090] BFI instructions are not generated on arm-none-eabi-g++

2022-04-12 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105090 Richard Earnshaw changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |rearnsha at gcc dot gnu.org

[Bug tree-optimization/102516] [12 regression] pr65947-13.c and vect-alias-check-18.c fail on armeb since r12-3893

2022-04-12 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102516 Richard Earnshaw changed: What|Removed |Added Status|WAITING |NEW --- Comment #4 from Richard Earn

[Bug tree-optimization/104010] [12 regression] short loop no longer vectorized with Neon after r12-3362

2022-04-13 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104010 Richard Earnshaw changed: What|Removed |Added Status|WAITING |NEW --- Comment #6 from Richard Earn

[Bug tree-optimization/104010] [12 regression] short loop no longer vectorized with Neon after r12-3362

2022-04-13 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104010 --- Comment #7 from Richard Earnshaw --- Options to reproduce on arm-none-eabi: -O3 -mcpu=cortex-a9 -mfpu=neon-fp16 -mfloat-abi=hard -o - vect.c -S -fdump-tree-all-details

[Bug target/106187] armhf: Miscompilation at O2 level (O0 / O1 are working)

2022-07-21 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106187 Richard Earnshaw changed: What|Removed |Added CC||rearnsha at gcc dot gnu.org --- Comm

[Bug target/106187] armhf: Miscompilation at O2 level (O0 / O1 are working)

2022-07-22 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106187 Richard Earnshaw changed: What|Removed |Added Last reconfirmed|2022-07-04 00:00:00 |2022-07-22 Status|UNCONF

[Bug target/106187] armhf: Miscompilation at O2 level (O0 / O1 are working)

2022-07-22 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106187 --- Comment #33 from Richard Earnshaw --- I suspect there is still a question, though, as to whether it is safe in general for two objects with non-conflicting alias sets to share a stack slot.

[Bug target/106187] armhf: Miscompilation at O2 level (O0 / O1 are working)

2022-07-25 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106187 --- Comment #35 from Richard Earnshaw --- > There's no union involved here though but a memcpy used in BitCast. Agreed, but by creating a shared stack slot, the compiler is effectively creating a union of its own, and I think that needs to be ac

[Bug target/106187] armhf: Miscompilation at O2 level (O0 / O1 are working)

2022-07-25 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106187 --- Comment #37 from Richard Earnshaw --- (In reply to rguent...@suse.de from comment #36) > Note that the only thing we have to do is fix points-to info, the TBAA > info should be correct and OK even when objects share location, so there's > n

[Bug rtl-optimization/106187] armhf: Miscompilation at O2 level (O0 / O1 are working)

2022-07-25 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106187 --- Comment #40 from Richard Earnshaw --- reload_cse_noop_set_p is the function that decides the store is redundant. For this parallel case it's being called once for each set, but all the cases return true, so the store insn gets removed.

[Bug rtl-optimization/106187] armhf: Miscompilation at O2 level (O0 / O1 are working)

2022-07-25 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106187 --- Comment #42 from Richard Earnshaw --- That would be unfortunate, it removes a lot of pointless loads in this case; and even the store it removes ought to be safe, if it weren't for the corrupted alias info that results (the values /are/ the

[Bug rtl-optimization/106187] armhf: Miscompilation at O2 level (O0 / O1 are working)

2022-07-25 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106187 --- Comment #45 from Richard Earnshaw --- The problem with changing rtx_equal_for_cselib_1 is that it is essentially commutative in its operands - it doesn't disambiguate with x substituting for y or vice-versa, so we cannot tell if an operation

[Bug target/106442] Build time error "vadd.i32 q3, q3, q0'" in case of -mcpu=cortex-m55+nofp+nomve.fp

2022-07-26 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106442 --- Comment #6 from Richard Earnshaw --- possibly a dup of pr101723. Please try gcc-11.3

[Bug target/106442] Build time error "vadd.i32 q3, q3, q0'" in case of -mcpu=cortex-m55+nofp+nomve.fp

2022-07-26 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106442 --- Comment #8 from Richard Earnshaw --- (In reply to sherry.zhang2 from comment #7) > (In reply to Richard Earnshaw from comment #6) > > possibly a dup of pr101723. Please try gcc-11.3 > > The latest version I can get is 11.2 > https://develo

[Bug rtl-optimization/106187] armhf: Miscompilation at O2 level (O0 / O1 are working)

2022-07-27 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106187 --- Comment #47 from Richard Earnshaw --- Created attachment 53361 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=53361&action=edit Possible patch A slightly more thorough attempt to avoid the problem by detecting when the alias sets are

[Bug rtl-optimization/106187] armhf: Miscompilation at O2 level (O0 / O1 are working)

2022-07-28 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106187 --- Comment #48 from Richard Earnshaw --- Improved version posted here: https://gcc.gnu.org/pipermail/gcc-patches/2022-July/598993.html

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