[Bug target/113742] ICE: RTL check: expected elt 1 type 'i' or 'n', have 'e' (rtx set) in riscv_macro_fusion_pair_p, at config/riscv/riscv.cc:8416 with -O2 -finstrument-functions -mtune=sifive-p600-se

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113742 --- Comment #1 from Kito Cheng --- Thanks, forward and assigned this to our (SiFive) engineer :)

[Bug target/115725] RISC-V: Use wrong AVL for rv64gcv_zfh_zvl512b

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115725 --- Comment #2 from Kito Cheng --- TU may not help for this case since we can't guarantee it's use v1 outside, I mean the argument is passed via a1 (pointer) rather than passed via v1.

[Bug target/115725] RISC-V: Use wrong AVL for rv64gcv_zfh_zvl512b

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115725 --- Comment #12 from Kito Cheng --- Qemu has provide two option to fill up all-one to agnostic policy: rvv_ta_all_1s and rvv_ma_all_1s*, I guess we could enable that by default in riscv-gnu-toolchain to discover more potential bugs. * qemu-r

[Bug target/115725] RISC-V: Use wrong AVL for rv64gcv_zfh_zvl512b

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115725 --- Comment #13 from Kito Cheng --- FYI: PR for riscv-gnu-toolchain: https://github.com/riscv-collab/riscv-gnu-toolchain/pull/1501

[Bug target/115795] RISC-V: vsetvl step causes wrong codegen after fusing info

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115795 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org --- Comment #3

[Bug target/115995] RISC-V: Can't generate portable RVV code for rv64gcv_zvl512b

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115995 --- Comment #3 from Kito Cheng --- We have an internal qemu patch for adding an option to trigger this damm behavior by default, and plan to upstream soon...let me ask our Qemu folk if I can get the patch out first.

[Bug target/116111] RISC-V: 'd' extension allowed with -mabi=ilp32e

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116111 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org --- Comment #2

[Bug target/117544] New: Lack of vsetvli after function call for whole register move

Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: kito at gcc dot gnu.org CC: jeffreyalaw at gmail dot com, juzhe.zhong at rivai dot ai, palmer at gcc dot gnu.org, pan2.li at intel dot com

[Bug target/117955] [15 Regression] GCC generate illegal riscv instruction `vsetvli zero,zero,e64,mf4,ta,ma` with -O2 and -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117955 --- Comment #4 from Kito Cheng --- I can't reproduce that by the top of trunk with your option, could you check does the bug still can be reproduced by trunk?

[Bug target/118827] riscv scalar and vector are all saved when __attribute__((interrupt)) used

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118827 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org --- Comment #3

[Bug target/118182] New: RISC-V: Miscompile for 410.bwaves, 416.gamess and 465.tonto from spec2006

: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: kito at gcc dot gnu.org Target Milestone: --- Created attachment 59955 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=59955&action=edit Reduced testcase f

[Bug target/118182] RISC-V: Miscompile for 410.bwaves, 416.gamess and 465.tonto from spec2006

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118182 --- Comment #2 from Kito Cheng --- （on the train yet but I can describe few details for my current solution 1. Always use vl=1 for vfmv.s.f - this will introduce one extra vsetvli, but at least it correct, and LLVM use same code gen as well 2

[Bug target/118384] unexpected call to __muldi3 generated for riscv target

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118384 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org --- Comment #5

[Bug target/118182] RISC-V: Miscompile for 410.bwaves, 416.gamess and 465.tonto from spec2006

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118182 Kito Cheng changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug tree-optimization/119477] RISC-V: -fno-tree-vectorize -fno-tree-loop-vectorize -fno-tree-slp-vectorize can't turn off auto-vectorization

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119477 Kito Cheng changed: What|Removed |Added CC||kito at gcc dot gnu.org --- Comment #1

[Bug tree-optimization/116125] [12/13/14 Regression] Does not fully checking for overlapping memory regions with the vectorizer

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116125 --- Comment #10 from Kito Cheng --- ping, does it possible to back port to release branches? it seems land on trunk for a while :)

[Bug target/119832] New: RISC-V: Redundant floating point rounding mode store/restore

-optimization Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: kito at gcc dot gnu.org Target Milestone: --- Target: riscv How to reproduce: ```shell $ riscv64-unknown-linux-gnu-gcc test.cc -S

[Bug target/119832] RISC-V: Redundant floating point rounding mode store/restore

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119832 --- Comment #1 from Kito Cheng --- Created attachment 61135 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=61135&action=edit 0001-RISC-V-Implement-TARGET_MODE_CONFLUENCE.patch My working patch for this bug

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